AP62200/AP62201/AP62200T: 4.2V to 18V Input, 2A Low IQ Synchronous Buck Converter

Description

The AP62200/AP62201/AP62200T is a 2A, synchronous buck converter with a wide input voltage range of 4.2V to 18V. The device fully integrates a 90mΩ high-side power MOSFET and a 65mΩ low-side power MOSFET to provide high-efficiency step-down DC-DC conversion.

The AP62200/AP62201/AP62200T device is easily used by minimizing the external component count due to its adoption of Constant On-Time (COT) control to achieve fast transient response, easy loop stabilization, and low output voltage ripple.

The AP62200/AP62201/AP62200T design is optimized for Electromagnetic Interference (EMI) reduction. The device has a proprietary gate driver scheme to resist switching node ringing without sacrificing MOSFET turn-on and turn-off times, which reduces high-frequency radiated EMI noise caused by MOSFET switching.

The AP62200/AP62201 is available in SOT563 (Standard) and TSOT26 (Standard) packages. The AP62200T is available in a TSOT26 (Standard) package.

Features

• VIN: 4.2V to 18V
• Output Voltage (VOUT): 0.8V to 7V
• 2A Continuous Output Current
• 0.8V ± 1% Reference Voltage (TA = +25°C) for AP62200 and AP62201
• 0.763V ± 1% Reference Voltage (TA = +25°C) for AP62200T
• 135µA Low Quiescent Current (Pulse Frequency Modulation)
• 750kHz Switching Frequency (VIN = 12V, VOUT = 5V)
• Up to 84% Efficiency at 5mA Light Load
• Proprietary Gate Driver Design for Best EMI Reduction
• Protection Circuitry: Undervoltage Lockout (UVLO), Cycle-by-Cycle Valley Current Limit, Thermal Shutdown
• Totally Lead-Free & Fully RoHS Compliant
• Halogen and Antimony Free. "Green" Device

For automotive applications requiring specific change control (e.g., parts qualified to AEC-Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact Diodes Incorporated representatives.

More information on product definitions can be found at: https://www.diodes.com/quality/product-definitions/

Pin Assignments

Applications

• 5V and 12V distributed power bus supplies
• Flat screen TV sets and monitors
• White goods and small home appliances
• FPGA, DSP, and ASIC supplies
• Home audio
• Network systems
• Consumer electronics
• Gaming consoles
• General purpose point of load

Typical Application Circuit

A typical application circuit diagram shows the AP62200/AP62201/AP62200T connected with input capacitors (C1), an inductor (L1), output capacitors (C2, C5), and resistors (R1, R2) for feedback. The VIN pin connects to the input voltage, SW to the inductor and output, GND to ground, BST to the bootstrap capacitor, EN to the enable pin, and FB to the feedback network.

Functional Block Diagram

The functional block diagram illustrates the internal components and signal flow. Key blocks include VIN, BST, SW, GND, FB, EN, VCC Regulator, UVLO, OCP, UVP, Control Logic, Soft-Start, and the power MOSFETs (Q1, Q2).

Absolute Maximum Ratings

The absolute maximum ratings specify the limits beyond which the device may be damaged. These include Supply Pin Voltage (VIN), Switch Pin Voltage (VSW), Bootstrap Pin Voltage (VBST), Enable/UVLO Pin Voltage (VEN), Feedback Pin Voltage (VFB), Storage Temperature (TSTG), Junction Temperature (TJ), and Lead Temperature (TL). ESD susceptibility for HBM and CDM is also provided.

Recommended Operating Conditions

The recommended operating conditions specify the ranges for Supply Voltage (VIN), Output Voltage (VOUT), and Operating Junction Temperature (TJ) for reliable operation.

Electrical Characteristics

This section details various electrical parameters such as Shutdown Supply Current (ISHDN), Quiescent Supply Current (IQ), VIN Power-on Reset Rising Threshold (POR), VIN Undervoltage Lockout Falling Threshold (UVLO), High-Side and Low-Side Power MOSFET On-Resistance (RDS(ON)1, RDS(ON)2), Valley Current Limit (IVALLEY_LIMIT), Oscillator Frequency (fsw), Minimum On-Time (ton_MIN), Minimum Off-Time (toFF_MIN), Feedback Voltage (VFB), EN Logic High/Low Thresholds (VEN_H, VEN_L), EN Input Current (IEN), Soft-Start Time (tss), and Thermal Shutdown (TSD) and its hysteresis (Thys).

Typical Performance Characteristics

This section presents graphs illustrating the device's performance under various conditions:

• Power MOSFET RDS(ON) vs. Temperature
• Feedback Voltage vs. Temperature
• VIN Power-On Reset and UVLO vs. Temperature
• Startup Using EN, IOUT = 2A
• Shutdown Using EN, IOUT = 2A
• Output Short Protection, IOUT = 2A
• Output Short Recovery, IOUT = 2A
• Efficiency vs. Output Current
• Line Regulation
• Load Regulation
• IQ vs. Temperature
• fsw vs. Load
• fsw vs. Temperature
• Output Voltage Ripple
• Load Transient Response

Application Information

1. Pulse Width Modulation (PWM) Operation

The device operates in PWM mode, utilizing a constant on-time control. The on-time (ton) is calculated based on input voltage (VIN), output voltage (VOUT), and switching frequency (fsw) using the formula: ton = VOUT / (VIN * fsw).

2. Pulse Frequency Modulation (PFM) Operation

The AP62200/AP62200T enters PFM operation at light load conditions for improved efficiency, achieving up to 84% at 5mA. The transition point between light and heavy load conditions is calculated using the formula: ILOAD = (VIN - VOUT) / (2 * L) * ton.

3. Enable

The EN pin controls the device's operation. Applying a voltage above the EN logic high threshold (typically 1.2V) enables the device with a 2.5ms soft-start. An internal pull-up ensures automatic enabling if left floating. Driving the EN pin below the logic low threshold (typically 1.1V) disables the device.

4. Electromagnetic Interference (EMI) Reduction with Ringing-Free Switching Node

The device features a proprietary gate driver scheme designed to minimize switching node ringing and reduce high-frequency radiated EMI noise without compromising performance.

5. Adjusting Undervoltage Lockout (UVLO)

The device has a built-in UVLO comparator. The VIN UVLO threshold can be programmed using an external resistive divider (R3 and R4) connected to the EN pin. The formulas for calculating R1 and R2 are provided.

6. Overcurrent Protection (OCP)

The device offers cycle-by-cycle valley current limit protection by sensing current through the low-side MOSFET (Q2). If the current limit is exceeded, the device enters hiccup mode to reduce power dissipation.

7. Thermal Shutdown (TSD)

The device includes thermal shutdown protection. If the junction temperature reaches +160°C, the device shuts down. It restarts once the temperature drops to +140°C typical.

8. Power Derating Characteristics

To prevent exceeding the maximum operating junction temperature, power derating is necessary. The temperature rise is calculated as TRISE = PD * ΘJA, and the junction temperature is TJ = TA + TRISE. Typical derating curves are provided for SOT563 and TSOT26 packages, showing output current versus ambient temperature at VIN = 12V for various output voltages.

9. Setting the Output Voltage

Output voltages are adjustable starting from 0.8V (AP62200/AP62201) or 0.763V (AP62200T) using an external resistive divider. The formula R1 = R2 * (VOUT / VFB - 1) is used to determine resistor values. Table 1 provides recommended component selections for common output voltages.

10. Inductor

Inductor value selection is critical. The formula L = (VOUT * (VIN - VOUT)) / (VIN * ΔIL * fsw) can be used. For this device, ΔIL should be 30% to 50% of the maximum load current (2A). The inductor peak current is calculated as ILPEAK = ILOAD + ΔIL / 2. It is recommended to select an inductor with a saturation current rating at least 35% higher than the maximum load current and a DC resistance less than 50mΩ for optimal efficiency.

11. Input Capacitor

Input capacitors reduce surge current and switching noise. They must sustain the ripple current and have a low ESR. A rule of thumb is to select an input capacitor with an RMS current rating greater than half of the maximum load current. Electrolytic or ceramic capacitors with low ESR are recommended. A 10µF or greater ceramic capacitor is sufficient for most applications.

12. Output Capacitor

Output capacitors ensure small output voltage ripple, stable feedback loop, and reduced overshoots/undershoots during load transients. The ESR of the output capacitor dominates the ripple. The formula for ripple is VOUTRipple = ΔIL * (ESR + 1 / (8 * fsw * COUT)). For load transient requirements, COUT must satisfy the inequality provided in the document.

13. Bootstrap Capacitor

A ceramic capacitor (100nF recommended, 330nF for VOUT > 3V) must be connected between BST and SW pins to supply the high-side power MOSFET drive voltage.

Layout

PCB Layout

Heat dissipation is a major concern due to the 2A load current. 2oz copper for top and bottom layers is recommended. Input capacitors should be placed close to VIN and GND. The inductor should be close to SW. Output capacitors should be close to GND. Feedback components should be close to FB. Using four or more layers with GND on the 2nd and 3rd layers maximizes thermal performance. Vias should be added around GND and VIN pins and under their respective planes for heat dissipation. Figures 42 and 43 show recommended PCB layouts for SOT563 and TSOT26 packages.

Ordering Information

The ordering information table lists available product versions (AP62200, AP62201, AP62200T), packages (SOT563, TSOT26), and packing (Tape & Reel). It details orderable part numbers, package type, operation mode, feedback voltage (VFB), package code, quantity (Qty), and carrier.

Marking Information

The marking information section explains the product code, year, week, and internal code markings on the device packages.

Package Outline Dimensions

Detailed dimensions for the SOT563 (Standard) and TSOT26 (Standard) packages are provided in millimeters, including diagrams illustrating top view and side view options.

Suggested Pad Layout

Suggested pad layouts for SOT563 (Standard) and TSOT26 (Standard) packages are shown with dimensions in millimeters for C, C1, G, X, X1, Y, and Y1.

Mechanical Data

Mechanical data includes moisture sensitivity level (Level 1 per J-STD-020) and terminal finish (Matte Tin Plated Leads) for both SOT563 and TSOT26 packages. Approximate weights are also provided.