AP62150: 4.2V to 18V Input, 1.5A Low IQ Synchronous Buck Converter

Description

The AP62150 is a 1.5A, synchronous buck converter with a wide input voltage range of 4.2V to 18V. The device integrates a 90mΩ high-side power MOSFET and a 65mΩ low-side power MOSFET to provide high-efficiency step-down DC-DC conversion. It utilizes Constant On-Time (COT) control for fast transient response, easy loop stabilization, and low output voltage ripple. The AP62150 is designed to minimize Electromagnetic Interference (EMI) through a proprietary gate driver scheme that reduces switching node ringing without sacrificing MOSFET turn-on and turn-off times. The device is available in SOT563 (Standard) and TSOT26 (Standard) packages.

Features

• Input Voltage (VIN): 4.2V to 18V
• Output Voltage (VOUT): 0.8V to 7V
• Continuous Output Current: 1.5A
• Reference Voltage: ±1% at +25°C
• Low Quiescent Current: 135µA (Pulse Frequency Modulation)
• Switching Frequency: 1.3MHz (Typical)
• Proprietary Gate Driver Design for EMI Reduction
• Protection Features: Undervoltage Lockout (UVLO), Cycle-by-Cycle Valley Current Limit, Thermal Shutdown
• RoHS Compliant and Halogen/Antimony Free

Pin Assignments

SOT563 (Standard) / TSOT26 (Standard) Pin Assignments:

• PIN 1 (SOT563) / 3 (TSOT26): VIN - Power Input
• PIN 2 (SOT563) / 2 (TSOT26): SW - Power Switching Output
• PIN 3 (SOT563) / 1 (TSOT26): GND - Power Ground
• PIN 4 (SOT563) / 6 (TSOT26): BST - High-Side Gate Drive Boost Input
• PIN 5 (SOT563) / 5 (TSOT26): EN - Enable Input
• PIN 6 (SOT563) / 4 (TSOT26): FB - Feedback Sensing Terminal

Typical Application Circuit

The typical application circuit includes the AP62150, an inductor (L), input capacitors (C1, C3), output capacitors (C2), and feedback resistors (R1, R2). The circuit diagram shows VIN connected to the input, GND to ground, SW connected to the inductor and output, BST connected to the inductor and SW, EN for enabling the device, and FB connected to the feedback network.

Figure 1: Typical Application Circuit

Figure 2: Efficiency vs. Output Current shows efficiency curves for different output voltages (5V and 3.3V) at a fixed input voltage (12V) and inductor value (3.3µH). Efficiency is high across a range of output currents, peaking above 90% for both configurations.

Electrical Characteristics

Key electrical characteristics include:

• Shutdown Supply Current (VEN=0V): 1.3µA (Typ)
• Quiescent Supply Current (VFB=0.85V): 135µA (Typ)
• Power-On Reset Rising Threshold: 3.90V to 4.15V
• Undervoltage Lockout Falling Threshold: 3.6V (Typ)
• High-Side MOSFET On-Resistance: 90mΩ (Typ)
• Low-Side MOSFET On-Resistance: 65mΩ (Typ)
• Valley Current Limit: 2.8A (Typ)
• Oscillator Frequency: 1.3MHz (Typ)
• Minimum On-Time: 65ns (Typ)
• Minimum Off-Time: 200ns (Typ)
• Feedback Voltage: 0.800V (Typ)
• EN Logic High Threshold: 1.20V to 1.25V
• EN Logic Low Threshold: 1.04V to 1.10V
• Soft-Start Time: 2.5ms (Typ)
• Thermal Shutdown: +160°C (Typ)
• Thermal Shutdown Hysteresis: +20°C (Typ)

Typical Performance Characteristics

Various graphs illustrate the typical performance:

• Figure 4: Efficiency vs. Output Current shows efficiency at different load currents for 5V and 3.3V outputs.
• Figure 5: Line Regulation demonstrates output voltage stability across varying input voltages for different load currents.
• Figure 6: Load Regulation shows output voltage stability under varying load currents for a 5V output.
• Figure 7: Feedback Voltage vs. Temperature illustrates the stability of the feedback voltage across temperature.
• Figure 8: Power MOSFET RDS(ON) vs. Temperature shows how the MOSFET on-resistance changes with temperature.
• Figure 9: IQ vs. Temperature displays quiescent current variation with temperature.
• Figure 10: ISHDN vs. Temperature shows shutdown current variation with temperature.
• Figure 11: VIN Power-On Reset and UVLO vs. Temperature plots the power-on reset and UVLO thresholds against temperature.
• Figure 12: fsw vs. Load shows switching frequency variation with output current.
• Figures 13-16: Output Voltage Ripple illustrate the output voltage ripple under different load conditions.
• Figures 17-19: Load Transient graphs show the output voltage response to load changes.
• Figures 20-23: Startup, Shutdown, and Short Protection waveforms demonstrate the device's behavior during these events.

Application Information

1. Pulse Width Modulation (PWM) Operation

The AP62150 operates in PWM mode for most conditions. The on-time (ton) is determined by the input and output voltages and the switching frequency (fsw) using the formula: ton = VOUT / (VIN * fsw). The off-time (toFF) begins after the on-time expires and ends when the feedback voltage drops below the reference voltage.

2. Pulse Frequency Modulation (PFM) Operation

For high efficiency at light loads, the AP62150 enters PFM mode, reducing the switching frequency. The transition between Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM) occurs when the inductor current reaches zero. The boundary condition is calculated using: ILOAD = (VIN - VOUT) / (2 * L) * ton.

3. Enable

The EN pin controls the device's operation. Applying a voltage above the logic high threshold (typically 1.2V) enables the device and initiates the soft-start sequence. An internal pull-up current source ensures enablement even if the EN pin is left floating. The EN pin can also be used to program Undervoltage Lockout (UVLO) thresholds. A small capacitor on the EN pin can delay startup for power rail sequencing.

4. Electromagnetic Interference (EMI) Reduction

The AP62150 features a proprietary gate driver scheme to achieve a ringing-free switching node, reducing EMI without compromising efficiency.

5. Adjusting Undervoltage Lockout (UVLO)

The device has a default UVLO threshold. Higher VIN UVLO thresholds can be programmed using an external resistive divider (R3, R4) connected to the EN pin, as shown in Figure 24. The formulas for calculating R3 and R4 are provided.

6. Overcurrent Protection (OCP)

The AP62150 employs cycle-by-cycle valley current limit protection. If the current exceeds a limit, the device enters hiccup mode after a delay, reducing power dissipation during overcurrent conditions. The VLIMIT has a temperature coefficient to compensate for RDS(ON) variations.

7. Thermal Shutdown (TSD)

The device shuts down if the junction temperature reaches +160°C and restarts after cooling to +140°C (typical).

8. Power Derating Characteristics

Thermal analysis is required to prevent exceeding the maximum operating junction temperature. The temperature rise is calculated using TRISE = PD * θJA, and the junction temperature is TJ = TA + TRISE. Figures 25 and 26 show typical output current derating curves versus ambient temperature for SOT563 and TSOT26 packages, respectively.

9. Setting the Output Voltage

The output voltage is adjustable from 0.8V using an external resistive divider (R1, R2). The formula R1 = R2 * (VOUT / 0.8V) - 1 is used to determine R1. Table 1 provides recommended component selections for various output voltages.

10. Inductor Selection

The inductor value is critical for buck converter design. The formula L = (VOUT * (VIN - VOUT)) / (VIN * ΔIL * fsw) can be used for calculation, where ΔIL is the inductor current ripple. For AP62150, ΔIL should be 30% to 50% of the maximum load current. Peak current is calculated by ILPEAK = ILOAD + (ΔIL / 2). Inductors with a saturation current rating at least 35% higher than the maximum load current and a DC resistance less than 50mΩ are recommended.

11. Input Capacitor

Input capacitors reduce surge current and switching noise. They must have a low ESR to minimize power dissipation. The RMS current rating should be greater than half the maximum load current. Electrolytic or ceramic capacitors with low ESR are recommended.

12. Output Capacitor

Output capacitors ensure stable feedback loop operation and reduce voltage ripple, overshoots, and undershoots during load transients. The output voltage ripple is affected by ESR and capacitance, calculated by VOUTRipple = ΔIL * (ESR + 1 / (8 * fsw * COUT)). A 22µF to 68µF ceramic capacitor is generally sufficient. The COUT must also satisfy the load transient requirements.

13. Bootstrap Capacitor

A 100nF ceramic capacitor connected between BST and SW provides the drive voltage for the high-side power MOSFET.

Layout

Proper PCB layout is crucial for managing heat dissipation at 1.5A load current. Recommendations include:

• Use 2oz copper for top and bottom layers.
• Place input capacitors close to VIN and GND.
• Place the inductor close to SW.
• Place output capacitors close to GND.
• Place feedback components close to FB.
• Utilize GND and VIN planes for heat dissipation.
• Add vias around GND and VIN pins and planes to improve thermal performance.

Refer to Figure 27 and Figure 28 for recommended PCB layouts for SOT563 and TSOT26 packages.

Ordering Information

The AP62150 is available in SOT563 (Z6) and TSOT26 (WU) packages, supplied in Tape & Reel (7) packing. Orderable part numbers include AP62150Z6-7 and AP62150WU-7.

Package Outline Dimensions

Detailed dimensions for the SOT563 (Standard) and TSOT26 (Standard) packages are provided, including pin configurations and overall dimensions in millimeters.

Suggested Pad Layout

Recommended pad layouts for SOT563 and TSOT26 packages are illustrated, showing component placement and dimensions.

Mechanical Data

Mechanical data for both packages includes moisture sensitivity level (Level 1 per J-STD-020), terminal finish (Matte Tin Plated Leads), and approximate weight.

Important Notice

Diodes Incorporated provides this document for informational purposes only. It assumes no liability for the application or use of its products. Customers are responsible for ensuring their applications comply with all applicable laws, regulations, and safety standards. Diodes' products are subject to their Standard Terms and Conditions of Sale. This document may contain technical inaccuracies, omissions, or typographical errors, and Diodes reserves the right to make changes without further notice.