Introduction
This document serves as a comprehensive guide for the IGLOO2 FPGA CoreTSE MAC 1000 Base-T Loopback Demo. It outlines the necessary steps for setting up, simulating, and testing the Ethernet loopback functionality on the IGLOO2 Evaluation Kit. The guide covers essential design requirements, prerequisites, and detailed procedures for both simulation and hardware execution, utilizing tools such as Libero SoC, FlashPro Express, Cat Karat, Wireshark, and Spirent Test Center.
Explore the capabilities of the CoreTSE MAC IP core in implementing high-performance Ethernet solutions for various networking applications. This demo facilitates a practical understanding of Ethernet packet transmission and reception through a loopback mechanism.
Key Features and Procedures
- Design Overview: Understand the architecture and components of the IGLOO2 FPGA CoreTSE MAC 1000 Base-T loopback design.
- Setup and Configuration: Follow step-by-step instructions for configuring the IGLOO2 Evaluation Kit and connecting it to a host PC.
- Simulation: Learn how to simulate the design using Libero SoC and ModelSim, including packet generation and analysis.
- Hardware Testing: Implement the demo on the IGLOO2 Evaluation Kit using FlashPro Express for programming and test tools like Cat Karat and Wireshark for verification.
- Advanced Testing: Utilize Spirent Test Center for more in-depth performance analysis and validation of the Ethernet loopback functionality.
Resources
For detailed information and to download the necessary design files, please refer to the official Microsemi website.