DG0889: PolarFire 12G-SDI Design Demo Guide
This document provides a comprehensive guide for setting up and running the PolarFire 12G-SDI design demo.
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Revision History
The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.
Revision 1.0
The first publication of the document.
PolarFire SDI Design
This document describes the method to run the SDI demo on the PolarFire video kit and the HD-SDI daughter card.
The demo design demonstrates the following functions:
- Dual camera module featuring IMX334 Sony image sensor
- YCbCr 422 converter
- SDI Transmitter (TX) IP
- HD-SDI daughter card for the loopback of the SDI data
- SDI Receiver (RX) IP
- HDMI 2.0 IP
The PolarFire Video Kit (DVP-102-000512-001) features:
- A 300K LE FPGA (MPF300TS, FCG11521)
- HDMI 2.0 with rail clamps, ReDrivers and corresponding connectors
- DSI Interface
- A High Pin Count (HPC) FMC connector to connect to high-speed interfaces (like 6G-SDI, 12G-SDI and USXGMII)
For more information about this video kit, see https://www.microsemi.com/existing-parts/parts/150747.
Description of the PolarFire Video Kit board, showing various connectors and components including: 12V Power Supply Input, USB-UART Terminal, HDMI 2.0 TX, HDMI 2.0 RX, MIPI CSI-2 RX Connector, MIPI CSI-2 TX Connector, SPI Flash Connector, JTAG Programming Header, Reset Switch, HPC FMC Connector, HDMI 1.4 TX, Dual Camera Sensor, and the PolarFire FPGA.
Design Requirements
The following table lists the hardware and software required to run the demo.
Design Requirement | Description |
---|---|
Hardware | |
PolarFire VIDEO KIT | DVP-102-000512-001 REV 1.0 |
USB A to mini-B cable | Required for FPGA programming |
HDMI cable | HDMI A Male to Male cable |
HDMI monitor | HDMI monitor for the HDMI 2.0 TX port. |
Power Adapter | 12V, 5A |
Host PC | A host PC with USB port |
HD-SDI daughter card | HDSDI daughter card with Coaxial BNC to BNC Male to Male Cable |
Software | |
Program_Debug_v12.2_win.exe | This executable file installs FlashPro Express, used to program the FPGA. |
Prerequisites
Before you start:
- Download the programming job file from: http://soc.microsemi.com/download/rsc/?f=mpf_dg0889_liberosoc_jb
- Download and install the GUI from: http://soc.microsemi.com/download/rsc/?f=mpf_dg0849_liberosoc_gui
- Download and install the Program and Debug software from: http://soc.microsemi.com/download/reg/download.aspx?p=f=ProgramDebug_v12_2_WIN
Note: On this web page, download the Program Debug v12.2 win.exe binary file. Installation of this executable file installs FlashPro Express used for FPGA programming. FlashPro Express is used in this demo.
Note: The Program and Debug Software also installs the drivers on the host PC to detect the COM port for running the demo. Install this software whenever the demo is run on a different host PC.
Demo Resources
The mpf_dg0889_liberosoc_jb folder contains the following resources:
- A job file (JOB file): This file includes the FPGA bitstream and the SPI Flash image to be programmed. For programming the FPGA using the job file, see Programming the PolarFire Device, page 8.
Demo Design
The following block diagram shows the SDI demo design implemented in the PolarFire FPGA using Libero SoC.
Description of the Top-Level Block Diagram: The diagram illustrates the data flow within the PolarFire FPGA for the SDI demo. It shows the interaction between the PolarFire FPGA, SPI Flash, Mi-V Configurator Subsystem, Camera Sensor, MIPI CSI-2 RX IP, Bayer Interpolation IP, YCbCr 422 ISP, TX Line Buffer, 4K Display Transceiver, HDMI 2.0 ISP, RX Line Buffer, 1080P ISP, Display Line Buffer, TX Line Buffer, 12G SDI TX IP, DDR Arbiter, 12G SDI RX IP, DDR Controller, SDI FMC Daughter Board, BNC TX Connector, BNC RX Connector, and BNC Cable.
The following points summarize the data flow in the design:
- The demo uses a dual camera module that captures the real-time video data. This video data is received by the PolarFire FPGA via the MIPI-CSI2 RX interface on the board.
- The real-time video data is converted to the YCbCr 422 format by an Image Signal Processing (ISP) IP and stored in the DDR memory as frame buffer.
- The SDI TX IP fetches these frames and transmits the data at 12G using PolarFire Transceiver (XCVR). The 12G-SDI data is looped back via the BNC cable on the SDI daughter card and received at the receive end of the XCVR.
- The SDI RX IP receives the data and stores the frame buffer in the DDR memory in a different address space. Finally, the received data is fetched by the HDMI 2.0 IP and displayed on a HDMI monitor.
The PolarFire 12G-SDI Libero design is available at http://soc.microsemi.com/download/rsc/?f=mpf_dg0889_liberosoc_df.
The Libero project must be opened using Libero SoC v12.2. The Libero SoC v12.2 is available for download at https://www.microsemi.com/product-directory/design-resources/1750-libero-soc#downloads.
Clocking Structure
The clocks generated from the onboard oscillator are used in the demo design. Using the 27 MHz reference frequency from the onboard oscillator, PF_CCC_C0 generates a 40 MHz clock for the XCVR_ERM_C1 (SDI_RX), and a 50 MHz clock for the Mi-V processor subsystem and DDR Controller. Using the reference frequency of 200 MHz (DDR System clock), PF_CCC_C1 generates a 148.5 MHz clock for XCVR_ERM_C0 (HDMI) and Display Controller.
Using the 148.5 MHz onboard oscillator, PF_XCVR_REF_CLK generates the following clocks:
- 148.5 MHz clock (LANE0_TX_CLK_G) for the SDI User Logic.
- 148.5 MHz clock (LANE0_RX_CLK_R) for the DDR Write Logic.
Using the reference frequency of 150 MHz, PF_CCC generates a 120 MHz clock for MIPI_RX_DECODER. Figure 3, page 5 shows the clocking structure of the design.
Description of the Clocking Structure diagram: This diagram illustrates the clock generation and distribution within the PolarFire FPGA. It shows various clock sources like 150 MHz, 148.5 MHz, 27 MHz, and 200 MHz, and how they are processed by clock management circuits (PF_CCC, PF_XCVR_REF_CLK) to generate clocks for different functional blocks such as MIPI_RX_DECODER, SDI USER LOGIC, DDR WRITE, XCVR_C1, HDMI_TX, DISPLAY_CONTROLLER, and PROC_SUBSYSTEM.
Reset Structure
The Mi-V processor subsystem, XCVR, UART, SDI, ISP, and all other blocks are reset when the following signals are asserted:
- DEVICE_INIT_DONE from PF_INIT_MONITOR
- DDR_CTRL_RDY from DDR Controller
- DDR PLL LOCK
- PLL_LOCK of PF_CCC_CO
The reset structure is shown in Figure 4, page 6.
Description of the Reset Structure diagram: This diagram shows the reset logic for various components within the PolarFire FPGA. It illustrates how signals like PF_POWER_INIT, PF_DDR4_PLL_LOCK, PF_DDR4_CTRL_READY, PF_CCC_CO_LOCK, PF_CCC_C1, and PF_CCC_C0 contribute to generating the core reset signals (CORE_RESET, FAB_RESET_N) for different subsystems like DDR_READ, Video_Arbiter, AXI_BUS, DDR_WRITE, ISP_BLOCK, HDMI_TX, Display_Controller, Color Space Conversion, UART_Interface, and PROC_SUBSYSTEM.
Setting Up the Demo
Setting up the demo involves the following processes:
- Setting Up the Hardware, page 6.
- Programming the PolarFire Device, page 8.
Setting Up the Hardware
Setting up the hardware involves interfacing the HD-SDI daughter board rev 1 card with the PolarFire Video Kit along with the HDMI monitor and verifying the jumper settings.
Description of the Board Setup: This image shows the physical connections required for the demo. It details connecting the camera sensor module to the video kit, connecting the HDMI monitor to the video kit's HDMI ports, connecting the host PC via USB, connecting the power supply, and connecting the HD-SDI daughter board to the FMC connector. It also highlights the coaxial BNC to BNC cable connection between the HD-SDI daughter board's transmit and receive ports.
Jumper | Default Position | Functionality |
---|---|---|
J15 | Open | SPI Slave and Master mode selection. By default, SPI master. |
J17 | Open | 100K PD for TRSTn. By default, 1K PD is connected. |
J19 | Pin 1&2 | Default: XCVR_VREF is connected to GND. |
J28 | Pin 1&2 | Default: Programming through the FTDI. |
J24 | Pin 2&4 | Default: VDDAUX4 voltage is set to 3V3. |
J25 | Pin 3&4 | Bank4 voltage is set to 2V5. |
J36 | Pin 1&2 | Default: Board power up through the SW4. |
SW4 | OFF | Power ON\OFF switch. |
SW6 | ON | User slide switch. |
J20 | 12 Volts input | 12V input to the board. |
Follow these steps:
- Connect the J1 connector of the dual camera sensor module to J38 interface of the video kit.
- Connect the Full HD HDMI monitor to J2 (HDMI 1.4 TX port) of the video kit using the HDMI cable.
- Connect the HDMI monitor to J1 (HDMI 2.0 TX port) of the video kit (for 4k video output).
- Connect the host PC and the video kit through J12 of the video kit using the USB mini cable.
- Connect the power supply cable to J20 of the video kit.
- Connect the 3_J4 of HD-SDI daughter board rev1 card to J14 of the FMC connector of video kit.
- On HDSDI DAUGHTER BOARD connect HD_TX(3_J1) to HD_RX(3_J2) with coaxial BNC to BNC male to male connector.
- Ensure that the following jumper settings are set on the video kit.
- Power-up the HDMI monitor.
- Power-up the board using the SW4 slide switch.
Programming the PolarFire Device
This chapter describes how to program the PolarFire device with the job file using Flashpro Express. The job file is available at the following design files folder location:
<$Download_Directory>\mpf_dg0889_liberosoc_jb
Follow these steps:
- On the host PC, start the FlashPro Express software from its installation directory.
- Select New or New Job Project from FlashPro Express Job from Project menu to create a new job project, as shown in the following figure.
Description of the FlashPro Express Job Project interface: This image shows the main window of FlashPro Express with options to create a new job project or open an existing one. The 'Project' menu is highlighted, showing 'New...' and 'Open...' options.
Description of the New Job Project dialog box: This image displays the 'New Job Project from FlashPro Express Job' dialog. It shows fields for 'Programming job file', 'FlashPro Express job project name', and 'FlashPro Express job project location', with 'Browse...' buttons for selecting files and directories. The 'OK' and 'Cancel' buttons are also visible.
- Enter the following in the New Job Project from FlashPro Express Job dialog box:
- Programming job file: Click Browse and navigate to the location where the job file is located and select the file. The default location is: <$Download_Directory>\mpf_dg0889_liberosoc_jb
- FlashPro Express job project location: Select Browse and navigate to the location where you want to save the project.
- Click OK. The required programming file is selected and ready to be programmed in the device.
- The FlashPro Express window appears as shown in Figure 4, page 7. Confirm that a programmer number appears in the Programmer field. If it does not, confirm the board connections and click Refresh/Rescan Programmers.
Description of the Programming the Device interface: This image shows the FlashPro Express window after a programmer has been detected. It displays the programmer ID, device information (MPF300T), and the status of programming (IDLE).
- Click RUN to program the device. When the device is programmed successfully, a RUN PASSED status is displayed as shown in Figure 5, page 7. See Running the Demo, page 8.
Description of the FlashPro Express-RUN PASSED status: This image shows the FlashPro Express window indicating a successful programming operation. The status for the programmer is 'RUN PASSED', and a message confirms that chain programming finished successfully.
- Close FlashPro Express (Project > Exit).
The PolarFire device and SPI Flash are programmed. Power cycle the board using switch SW4. After power cycling, the HDMI monitor displays the live video from camera.
Running the Demo
The demo features receiving the MIPI Rx data from the IMX334 camera with 4K resolution at 30 frames per second (fps). The frames from camera are converted to YCbCr 422 format and stored in DDR. The 12G SDI Tx IP transmits the DDR video frames using PolarFire XCVR. The 12G SDI Rx IP receives the SDI video and stores the frames in DDR. The HDMI IP reads the frame buffer written by SDI Rx IP and sends out to HDMI display using XCVR. The image processing IPs are enabled on the display side of the video pipeline.
In the demo design, two display controllers are used to provide two video outputs:
- Full HD output (1920x1080 60Hz resolution)
- 4K output (3840x2160 30Hz resolution)
The Full HD output supports panning and Image enhancements such as contrast, brightness and color balance. The 4K output supports Image enhancements. The GUI application for image enhancements is common for both the video outputs.
Running the demo involves verifying the imaging and video settings using the Video_Control GUI and then observing the result on the HDMI monitor.
To use the demo GUI:
- Start the Video_Control GUI from the installation directory. The GUI is displayed as shown in the following figure.
Description of the Video Control GUI: This image shows the graphical user interface for controlling video settings. It includes sliders for Alpha, Contrast, Brightness, and Color Balance (Red, Green, Blue). It also has options for Bayer/Edge Select, Reset, PIP Menu, and Panning. A COM port selection dropdown is visible, along with a 'Connect' button.
- Select the second largest COM port on the GUI and select the Connect option.
Description of the Connecting the GUI and Video kit interface: This image shows the COM port selection dropdown in the Video Control GUI. It highlights the selection of COM31, which is indicated as the second largest COM port, followed by the 'Connect' button.
3. The Connect button turns green indicating a successful connection.
Description of the Connection Successful status: This image shows the Video Control GUI after a successful connection. The 'Connect' button is now green, indicating a stable connection to the video kit.
- Use the Contrast and Brightness sliders to adjust the contrast and brightness and observe the change on the HDMI monitor. The sliders are highlighted in the following figure.
Description of Adjusting Contrast and Brightness: This image highlights the Contrast and Brightness sliders within the Video Control GUI. The Contrast slider is shown adjusted to approximately 175, and the Brightness slider to approximately 128.
- Similarly, adjust the color balance of the image using the color balance sliders.
- In the main video control GUI window, select the Panning option to view a particular area of the main or the PIP image within a 4K image.
- In the Panning Menu, use Image Select to select the image to be panned (Main image or PIP image). Any area of the 4K camera feed can be viewed by dragging the pink box horizontally or vertically. The Reset option sets the view of the Main image and PIP image to its default center position.
Description of the Panning Menu: This image shows the Panning Menu window. It includes an 'Image Select' option with radio buttons for 'Main Image' and 'PIP Image'. A preview window displays a pink box that can be dragged to pan the image. 'Reset' and 'Pan' buttons are also present.
- Close the Panning Menu to return to the main GUI.
- Close the GUI to exit from the demo.
Note: The following features in the GUI are not supported in the current SDI design:
- Alpha
- Edge
- PIP
This concludes the demo.
File Info : application/pdf, 17 Pages, 2.37MB
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