AL58812 12-CHANNEL LINEAR LED DRIVER

Description

The AL58812 is comprised of 12 programmable LED current channels, each with an internal 12-bit PWM for color and brightness control through an I2C or SPI digital interface. The AL58812 is ideal for up to 4 RGB LED module lighting applications, with 3 programmable banks (A, B, C) for software control of each color. An external resistor can set the global output current of all 12 channels. Each channel current can digitally be configured up to 70mA under the thermal limitation of the package.

Features of the AL58812 are controlled via an I2C/SPI digital interface, which is selectable by the INT_SEL pin. The AL58812 has a 30kHz, 12-bit PWM generator for each channel, as well as channel/module independent color mixing and brightness control registers to enable vivid LED effects with zero audible noise. Users can benefit from the device's ultra-low shutdown IQ Power-Saving Mode and easy software programming.

The device operates over -40°C to +85°C ambient temperature range. The AL58812 is available in W-QFN5050-40/SWP (Type A1) MSL level 1 package.

Pin Assignments

(Top View - Not to Scale)

The AL58812 is a 40-pin device in a W-QFN5050-40/SWP (Type A1) package. The thermal exposed pad serves as a ground connection.

Features

• Input Voltage 2.7V to 5.5V
• 12 Precision LED Current Sinks
• OUT Pins Voltage max 5.5V
• 70mA per Channel Current
• 12-Bit PWM Register with 30kHz PWM Generator
• PWM Phase Shifting
• 6-Bit Global Current Dimming
• Independent Color-Mixing Register
• Independent Brightness Control Registers
• Logarithmic or Linear-Scale Brightness Control
• Three Programmable Banks (A, B, C)
• Low-Dropout VSAT 200mV Typical at 70mA
• Hardware-Selectable I2C or SPI Digital Interface
• Support 400kHz I2C Interface and 4MHz SPI
• Diagnosis and Protections: Open-Drain Fault Indication Pin and Registers, Individual Fault Mask Registers for Each Channel, Overtemperature Protection (OTP) with Pre-OTP Warning, LED Open/Short, Undervoltage
• Ultra-Low Quiescent Shutdown 1µA
• Power-Saving Mode: 15µA (max)
• Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
• Halogen and Antimony Free. "Green" Device (Note 3)
• For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact Diodes Incorporated or your local Diodes representative.
• Link: https://www.diodes.com/quality/product-definitions/

Applications

• Smart home appliances
• Electric vehicle charging stations
• Infotainment displays
• IoT information indicators
• Computing hardware

Device Information

Note 12: For packaging details, visit https://www.diodes.com/design/support/packaging/diodes-packaging/.

Functional Block Diagram

The functional block diagram illustrates the AL58812's architecture. Key components include the VIN power input, VCC and Vio power rails, a 1.8V LDO, an INT_SEL pin for interface selection, and a Translator block that interfaces with the Digital Core. The Digital Core contains the SPI/I2C Digital Interface, an Oscillator (16MHz), and a 12-bit, 30kHz PWM Generator. The PWM Generator is controlled by Color-Mixing and Brightness-Control inputs, with a Dither Decoder. The device features Thermal Shutdown and Diagnostics. The output stage consists of 12 channels (OUT0-OUT11) driven by the PWM generators, with an IREF pin for setting the global output current via an external resistor (RIREF). Protection features like FAULT, RSTn, and EN pins are also shown.

Absolute Maximum Ratings

Note 4: Stresses beyond these ratings can cause permanent damage. These are stress ratings only; functional operation outside recommended conditions is not implied. Exposure to absolute maximum ratings for extended periods can affect reliability. Devices are ESD sensitive; take appropriate precautions.

Package Thermal Information

Note 5: Test condition: device mounted on FR-4 PCB (51mm x 51mm 2oz copper, minimum recommended pad layout on top layer and thermal vias to bottom layer with maximum area ground plane. For better thermal performance, larger copper pad for heatsink is needed.

Recommended Operating Conditions

Note 6: Dependent on ambient temperature, LED voltage, package thermal limitation, and PCB layout. Set Max_Current_Option = 1 for 70mA.

Electrical Characteristics

(VIN = 3.3V, -40°C < TA < +85°C, unless otherwise specified.)

POWER SUPPLY

CURRENT SINK (Note 7)

(Max_Current_Option set in Device Config 1 Register, G5:G0 set in LED Global Dimming Register (See page 24))

Notes: 7. For understanding of PWM generation process, please refer to Section 2.1.3. 8. ID2D: accuracy of average of all 12 channels current with respect to design target. 9. IC2C: accuracy of individual channel current with respect to the average of all 12 channels current within a device. Channel current: average, or mean current (not RMS current) on a channel. Not production tested, guaranteed by design. 10. Not production tested, guaranteed by design.

Electrical Characteristics (continued)

(VIN = 3.3V, -40°C < TA < +85°C, unless otherwise specified.)

PWM GROUP DIMMING

PROTECTION (Note 10)

Note: 10. Not production tested, guaranteed by design.

Typical Performance Characteristics

(VIN = 5V, -40°C < TA < +85°C. Max_Current_Option = 1 for 70mA, unless otherwise specified.)

Figure 1. Channel to Channel Accuracy vs. Temperature: This graph shows the channel-to-channel accuracy across temperature for VIN=5V. It plots accuracy (%) against temperature (°C) from -40°C to 85°C, with lines representing 70mA Min/Max, 39mA Min/Max, and 10mA Min/Max.

Figure 2. OUT Current vs. Temperature: This graph displays the output LED current (Average mA) against temperature (°C) for VIN=5V. It shows curves for 70mA, 39mA, 20mA, 12mA, and 4mA settings.

Figure 3. IOUT vs. RIREF: This graph illustrates the relationship between output current (IOUT in mA) and the external dimming resistor (RIREF in kOhms). It shows two curves for Global Dimming = 000000 and Global Dimming = 011111.

Figure 4. IOUT vs. VOUT: This graph shows the output current (IOUT in mA) versus output voltage (VOUT in V). It plots multiple curves for different RIREF values (14kΩ, 7kΩ, 4.7kΩ, 3.5kΩ, 2.8kΩ, 2.1kΩ) and global dimming settings (000000 and 011111).

Functional Descriptions

1. General Operation

The AL58812 can be controlled via I2C or SPI interface, selected by the INT_SEL pin. It offers four primary mechanisms for controlling LED color and brightness: setting the full range LED current with RIREF, using a 6-bit global dimming register, configuring color/brightness registers, and selecting various dimming and protection features.

2. Feature Description

2.1 Each Channel PWM Control

The AL58812 provides independent color mixing and brightness control for each channel, enabling complex RGB LED effects. Each channel features an 8-bit color-setting register and a brightness-control register. The output PWM generator offers 12-bit resolution and 30kHz dimming frequency for smooth effects and noise elimination. For example, achieving yellow color involves setting R, G, and B components (e.g., 255, 255, 0) in color registers and adjusting brightness via the brightness register.

Figure 5. PWM Control Scheme for Each Channel: Depicts how 8-bit color registers (R, G, B) and an 8-bit brightness control register feed into 12-bit PWM generators, with a dither decoder, to control the output channels (OUT0, OUT1, OUT2).

2.1.1 Independent Color Mixing per RGB LED Module

Each output channel has an individual 8-bit color-setting register (OUTx_COLOR), allowing for over 16 million color combinations per RGB LED module.

2.1.2 Independent Brightness Control per RGB LED Module

This feature allows for accurate and flexible dimming control for each RGB LED module when the color is fixed. Brightness is controlled via respective brightness-control registers (RGBx_BRIGHTNESS), with 256-step control for smooth dimming. Setting the register to FFh provides 100% brightness.

2.1.2.1 Brightness-Control Register Configuration

Output channels are grouped into sets of three for brightness control registers (e.g., LED0, LED1, LED2 use RGB0_BRIGHTNESS). Table 1 shows the bank number and RGB module assignment.

2.1.2.2 Logarithmic- or Linear-Scale Brightness Control

The device supports both logarithmic and linear dimming scales, selectable via the Log_Scale_EN register bit. The logarithmic scale is implemented for natural visual performance, while the linear scale allows for software correction for custom dimming curves. Color distortion issues common with logarithmic scales in RGB applications are mitigated by the independent color-mixing and brightness-control registers.

Figure 6. Logarithmic vs Linear Dimming Curve: Shows two curves plotting PWM Duty Cycle (%) against RGBx_Brightness Register Input (0-255) for Linear Scale and Logarithmic Scale dimming.

2.1.3 12-Bit, 30kHz PWM Generator per Channel

The final PWM duty cycle is a product of color mixing and brightness control register values. It offers 12 bits of resolution, achieved through 9 bits of pure PWM resolution and 3 bits of dithering. Dithering can be enabled or disabled via the PWM_Dithering_EN register. When enabled, it enhances PWM resolution. The text explains how dithering adds small increments to the duty cycle for finer control.

2.1.4 PWM Phase-Shifting

A PWM phase-shifting scheme delays the activation of LED drivers to reduce peak load current, input-current ripple, and audible ringing. LED drivers are grouped into three phases:

• Phase 1: Fixed rising edge, falling edge varies with duty cycle. Applied to LED0, LED3, etc.
• Phase 2: Fixed middle point, pulse spreads with duty cycle increase. Applied to LED1, LED4, etc.
• Phase 3: Fixed falling edge, rising edge varies with duty cycle. Applied to LED2, LED5, etc.

2.2 LED Bank Control

To simplify LED animation effects, the AL58812 offers LED bank control. Instead of controlling each LED individually, channels can be grouped into banks (A, B, C) via the RGBx_Bank_EN register. When bank control is enabled (RGBx_Bank_EN = 1), color mixing and brightness are governed by bank control registers, simplifying software effort for effects like blinking and breathing. Table 1 details the bank number and RGB module assignment.

Figure 7. Bank PWM Control Example: Illustrates a configuration where RGB0 is in independent mode, while RGB1 to RGB3 are in bank mode.

2.3 Automatic Power-Save Mode

When all LED outputs are inactive, the AL58812 enters a low-power Power-Save mode (idle current down to 25µA max). This mode is enabled by the Power_Save_EN register bit when all LEDs are off for over 30ms. Analog blocks are powered down, but registers retain data. Any I2C/SPI command returns the device to NORMAL mode.

2.4 Protection Features

2.4.1 LED Open-Circuit Diagnostics

The device monitors OUTx voltage for open-circuit conditions. If VOUTx drops below VOPEN_th_rising for a duration exceeding tFAULT_WAIT (determined by Table 2), the FAULT pin is pulled low, and flag registers (Open_Fault_CHx, FLAG_OPEN) are set. The controller must send CLR_FAULT to clear the flag after fault removal.

Table 2. Fault Wait Time: Lists tFAULT_WAIT values (8, 16, 24, 32 PWM clock counts) based on FW1 and FW0 bits.

2.4.2 LED Short-Circuit Diagnostics

The AL58812 monitors the voltage difference between VIN and OUTx. If (VIN - VOUTx) falls below VSC_th_rising for a duration exceeding tFAULT_WAIT, the FAULT pin is pulled low, and flag registers (Short_Fault_CHx, FLAG_SHORT) are set. The MCU should turn off the affected channel to prevent damage. CLR_FAULT is needed to clear the flag.

2.4.3 Pre-OTP Warning & Thermal Shutdown

The device has a pre-thermal warning threshold of +145°C (typical) and a thermal shutdown threshold of +165°C (typical). If the junction temperature exceeds +145°C for more than 33µs, the FAULT pin goes low, and FLAG_PREOTP is set. The warning clears when the temperature drops below +125°C. At +165°C, the device shuts down all outputs and pulls the FAULT pin low. Thermal shutdown is released when the temperature drops to +145°C.

2.4.4 Pre-UVLO Warning

A Pre-UVLO warning is issued if VIN drops below the Pre-UVLO- threshold for more than 33µs. The FAULT pin goes low, and FLAG_PREUVLO is set. The warning clears when VIN rises above the Pre-UVLO+ threshold. CLR_FAULT is required to clear the flag.

2.4.5 UVLO

When VIN falls below the UVLO- threshold, the device enters the INITIALIZATION state. The FAULT pin is pulled low to indicate this fault.

2.4.6 Digital POR Indicator

The FLAG_POR bit indicates a power-on reset. The controller can use CLR_POR to reset this flag for subsequent power-on reset detection.

2.5 Interface Selection

The INT_SEL pin determines the interface: I2C when tied low, SPI when tied high.

2.6 Digital Communication Enhancements

The RSTn pin controls the digital block. A pulse between 1ms and 20ms resets only the digital interface, while a pulse longer than 20ms resets all registers. An internal pullup resistor keeps RSTn high by default.

Current Setting for All Channels

The maximum global output current (IMAX) for all 12 channels is set by the external resistor RIREF and programmed via the Max_Current_Option and LED_GLOBAL_DIMMING registers. The formula is provided:

IMAX = KIREF x VIREF /RIREF x [ (Max_Current_Option/4)+(3/4) ] (1)

Where: IMAX is channel average current (Color Register = FF, Brightness Register = FF), VIREF = 0.7V, RIREF is the external dimming resistor (2.1kΩ recommended), and KIREF is a current multiplication factor derived from the 6-bit global dimming register (G5:G0).

Table 3. IMAX vs. Global Dimming @ RIREF = 2.1kΩ: Shows IMAX values for different global dimming settings (G5:G0) with Max_Current_Option = 1 and 0, along with N and KIREF values. The default IMAX is 39mA, with a minimum of 7mA and a maximum of 70mA.

Table 4. IMAX vs. RIREF @ G5:G0 = 000000: Demonstrates IMAX variation with RIREF for a specific global dimming setting.

Table 5. IMAX vs. Global Dimming Bits @ Various RIREF: Summarizes IMAX ranges for different RIREF values and global dimming settings.

2.7.1 Thermal Considerations

When VIN reaches 5.5V and higher currents are configured, the device may overheat. Junction temperature (TJ) must not exceed the thermal shutdown temperature. The relationship between junction temperature, ambient temperature (TA), junction-to-ambient thermal resistance (θJA), and total power dissipation (PTOTAL) is given by: TJ = TA + (θJA x PTOTAL). Total power dissipation for all 12 channels is calculated based on output voltage and current.

2.8 Microcontroller (MCU) Supply

The AL58812 supports MCU logic levels from 1.8V to 5.5V. The MCU's supply voltage should be connected to the Vio pin to inform the AL58812.

Device Functional Modes

The AL58812 operates in several functional modes:

• INITIALIZATION: Entered when EN is High. All registers reset.
• NORMAL: Entered when Chip_EN = 1. Typical IVIN is 7mA.
• POWER SAVE: Automatic entry when Power_Save_EN = 1 and all LEDs are off for > 30ms. Reduces power consumption to 25µA (max).
• SHUTDOWN: Entered on VIN power down or when EN = Low for > 25ms. IVIN is < 6µA (max).
• STANDBY: Entered when Chip_EN = 0. Registers retain data. Low-power mode with 25µA (max) IVIN.
• THERMAL SHUTDOWN: Automatic entry when junction temperature exceeds +160°C (typical). FAULT pin goes low, and outputs shut down.

Figure 8. Functional Mode: A state diagram illustrating transitions between SHUTDOWN, INITIALIZATION, STANDBY, POWER SAVE, NORMAL, and THERMAL SHUTDOWN modes based on input signals (EN, Chip_EN) and conditions (VIN, TSD).

RETURN TO NORMAL MODE: Requires writing 02h to the MASK and CLR register (68h) to clear fault bits, and then writing 40h to DEVICE_CONFIG0 (00h) to re-enable the device.

Programming (SPI)

3.1 SPI-Compatible Interface

The AL58812 functions as a slave device on an SPI bus. Initialization involves waiting for the chip selection signal (SPICS_SCL). Lead and lag time requirements for SPICS_SCL and SPISCL_ADDR1 must be met. The device operates in SPI Mode 0 (data read on rising edge, clock polarity low).

3.1.1 SPI Initialization

Upon power-on reset (POR), the SPI peripheral waits for the chip selection signal. SPISDA_ADDR0 is high impedance until an active low on the select line is detected. Timing requirements for lead and lag times are specified.

3.1.2 Write Operation

A '1' in the R/W bit of the SPI frame indicates a write request. Bits A6-A0 specify the register address. Data (D7-D0) is written on the last positive edge of SPISCL_ADDR1.

Figure 9. SPI Write Transaction: A timing diagram showing the sequence of signals (SPICS_SCL, SPISCL_ADDR1, SPISDA_ADDR0, SPISDO_SDA) during an SPI write operation.

3.1.3 Read Operation

A '0' in the R/W bit indicates a read request. Bits A6-A0 specify the register address. For valid addresses, 8-bit register contents are read. Invalid addresses return a default value. Data is set up on the falling edge and read on the rising edge of the clock.

Figure 10. SPI Read Transaction: A timing diagram showing the sequence of signals during an SPI read operation.

Programming (I2C)

4.1 I2C Interface

The AL58812 supports an I2C-compatible two-wire serial interface for communication. The interface uses SDA (serial data) and SCL (serial clock) lines. Each device on the bus has a unique address. Pullup resistors are required on SDA and SCL lines.

4.1.1 Data Validity

Data on SDA must be stable during the HIGH period of SCL. Data changes are allowed only when SCL is LOW.

Figure 11. Data Validity: Illustrates the timing for valid data transfer on SDA relative to SCL.

4.1.2 Start and Stop Conditions

START conditions (SDA HIGH-to-LOW transition while SCL is HIGH) signify the beginning of a data transfer. STOP conditions (SDA LOW-to-HIGH transition while SCL is HIGH) signify the end. The bus master generates these conditions. The bus is busy after START and free after STOP. Repeated START conditions are also supported.

Figure 12. Start and Stop Conditions: Depicts the signal transitions for START (S) and STOP (P) conditions.

4.1.3 Transferring Data

Data is transferred in 8-bit bytes, MSB first, followed by an acknowledge (ACK) bit. The master generates the ACK clock pulse. The device pulls SDA low for ACK. A negative acknowledge (NACK) is used to indicate the end of data when the master is the receiver. The communication sequence involves a START condition, chip address (7 bits + R/W bit), register address (8 bits), and data bytes.

Figure 13. Acknowledge and Not Acknowledge on I2C Bus: Shows the ACK/NACK mechanism during I2C data transfer.

4.1.4 I2C Slave Addressing

Four independent slave addresses are available by connecting GND or Vio to the SPISDA_ADDR0 and SPISCL_ADDR1 pins (Tables 6 & 7). A broadcast address is also supported for simultaneous configuration of multiple devices. Global reads are supported, but data is only valid if all devices have the same register value.

Table 6. Slave-Address Combinations: Lists address combinations based on SPISCL_ADDR1 and SPISDA_ADDR0 pin states.

Table 7. Chip Address: Defines the 7-bit slave address structure including R/W bit.

4.1.5 Control-Register Write Cycle

Details the sequence for writing to control registers: START condition, slave address, ACK, register address, ACK, data byte, ACK, and finally STOP condition. Auto-incrementation of register addresses is supported.

Figure 14. Write Cycle: Timing diagram for an I2C control-register write cycle.

4.1.6 Control-Register Read Cycle

Details the sequence for reading from control registers: START, slave address, ACK, register address, ACK, repeated START, slave address (with R/W=1), ACK, data byte, and STOP. Auto-incrementation is supported.

Figure 15. Read Cycle: Timing diagram for an I2C control-register read cycle.

FAULT Output

The FAULT pin is an nMOS open-drain output that signals faults. It can be pulled up externally to the MCU supply. When faults like UVLO, OTP, Pre-UVLO, Pre-OTP, LED Open, or LED Short occur, the FAULT pin is pulled low. The AL58812 takes direct action for UVLO and OTP faults; for others, it reports the fault, and the controller must take action and reset the fault flag using CLR_FAULT.

Figure 16. FAULT Internal Block Diagram: Shows the FAULT pin connected to various fault detection blocks (Pre-UVLO, Pre-OTP, UVLO, OTP, LED Open, LED Short, POR) and pullup resistors.

Protection

4.3 Unused Channel Masking

Write '1' to reserved bits in Open Mask registers (addresses 6Ah-6Eh) to mask faults for unused channels, preventing them from being reported to the FAULT pin. Unused OUTx pins can be left floating or grounded.

4.4 Fault Masking

Masking options (Open_Mask_CHx, Open_Mask, Short_Mask_CHx, Short_Mask, Pre_OTP_Mask, Pre_UVLO_Mask, POR_Mask) are available to prevent specific faults from being reported to the FAULT pin.

Registers Map Description

The AL58812 features a comprehensive register map for configuration and control. Key registers include:

• DEVICE_CONFIG0 (00h): Controls Chip Enable (CHIP_EN).
• DEVICE_CONFIG1 (01h): Configures Phase Shift (Phase_Shift_EN), Logarithmic Scale (Log_Scale_EN), Power Save (Power_Save_EN), Dithering (Dither_EN), Max Current Option, and LED Global Off.
• LED_CONFIG0 (02h): Controls bank enable for RGB2, RGB1, and RGB0 channels.
• LED_CONFIG1 (03h): Controls bank enable for RGB3 channels.
• BANK_BRIGHTNESS (04h): Sets bank brightness (0% to 100%).
• BANK_A/B/C_COLOR (05h-07h): Configure color mixing for banks.
• RGB0-RGB3_BRIGHTNESS (0Bh, 0Ch, 0Fh, 10h): Set brightness for individual RGB channels.
• Rx/Gx/Bx_COLORx (1Dh-2Eh): Configure color mixing for individual channels (R0-R3, G0-G3, B0-B3).
• RESET (38h): Resets all registers to default values.
• FLAG (65h): Status flags for POR, Pre-UVLO, Pre-OTP, Short, and Open faults.
• LED_GLOBAL_DIMMING (66h): 6-bit setting for global current adjustment.
• FAULT_WAIT (67h): Configures fault wait times (FW1, FW0).
• MASK and CLR (68h): Enables fault masking and clearing of fault flags.
• OMx Registers (6Bh-6Eh): Open Mask registers for individual channels.
• SMx Registers (70h-74h, 7Dh-7Eh): Short Mask registers for individual channels.
• OFx Registers (77h-79h): Open Fault registers for individual channels.
• SFx Registers (7Ch-7Eh): Short Fault registers for individual channels.

Detailed register descriptions and bit fields are provided in the original document.

Application Information

Timing Requirements for I2C Interface

Table 38 and Figure 17 detail the timing parameters for I2C communication, including clock frequency, setup and hold times, and bus free times.

Table 38. Input and Output Logic Levels: Specifies logic levels for digital inputs (EN, RSTn, INT_SEL) and digital interface signals (SPICS_SCL, SPISDO_SDA, SPISDA_ADDR0, SPISCL_ADDR1).

Timing Requirements for SPI Interface

Figure 18 and associated text outline the timing requirements for SPI communication, including clock frequency, setup and hold times, and chip select timing.

Ordering Information

The AL58812 is available under the part number AL58812FRZW40-13. It comes in a W-QFN5050-40/SWP (Type A1) package, supplied on 13" tape & reel with a quantity of 5000 units per carrier.

Marking Information

The W-QFN5050-40/SWP (Type A1) package marking includes the Logo, Marking ID (AL58812), Year (YY), Week (WW), and Internal Code (XX).

Package Outline Dimensions

The W-QFN5050-40/SWP (Type A1) package dimensions are provided in millimeters. The drawing shows the overall dimensions (A, A1, A3, b, D, D2, E, E2, e, k, L) and includes a terminal cross-section view.

Suggested Pad Layout: Provides recommended land pattern dimensions (C, C1, C2, X, X1, Y, Y1) for the W-QFN5050-40/SWP (Type A1) package.

Tape and Reel Information

Details on tape and reel specifications can be found at: https://www.diodes.com/assets/Packaging-Support-Docs/AP02007.pdf.

Mechanical Data

Package: W-QFN5050-40/SWP (Type A1)

• Moisture Sensitivity: Level 1 per J-STD-020
• Terminals: Matte Tin Plated Leads, Solderable per JESD22-B102 e3
• Weight: 0.0091 grams (Approximate)

Important Notice

Diodes Incorporated provides information for its products for informational purposes only. It does not warrant the accuracy or completeness of the information and assumes no liability for its use. Customers are responsible for evaluating product suitability, ensuring compliance with regulations, and implementing safeguards. Diodes' products are subject to standard terms and conditions of sale, and may be covered by patents. Unauthorized copying or distribution of this document is prohibited.