MICROCHIP CoreFPU Core Floating Point Unit
소개
- The Core Floating Point Unit (CoreFPU) is designed for floating-point arithmetic and conversion operations, for single and double precision floating-point numbers. CoreFPU supports fixed-point to floating-point and floating-point to fixed-point conversions and floating-point addition, subtraction, and multiplication operations. The IEEE® Standard for Floating-Point Arithmetic (IEEE 754) is a technical standard for floating-point computation.
- Important: CoreFPU supports calculations with normalized numbers only, and only the Verilog language is supported; VHDL is not supported.
요약
The following table provides a summary of the CoreFPU characteristics.
Table 1. CoreFPU Characteristics
코어 버전 | This document applies to CoreFPU v3.0. |
지원되는 장치 제품군 |
|
지원되는 도구 흐름 | Libero® SoC v12.6 이상 릴리스가 필요합니다. |
라이센스 | CoreFPU is not license locked. |
설치 지침 | CoreFPU must be installed to the IP Catalog of Libero SoC automatically through the IP Catalog update function. Alternatively, CoreFPU could be manually downloaded from the catalog. Once the IP core is
installed, it is configured, generated and instantiated within SmartDesign for inclusion in the project. |
장치 활용도 및 성능 | A summary of utilization and performance information for CoreFPU is listed in Device Resource Utilization and Performance. |
CoreFPU Change Log Information
이 섹션에서는 포괄적인view of the newly incorporated features, beginning with the most recent release. For more information about the problems resolved, see the Resolved Issues section.
버전 | 새로운 소식 |
v3.0 | Implemented additional output flags to enhance the accuracy of the IP |
v2.1 | Added the double precision feature |
v2.0 | Updated the timing waveforms |
v1.0 | First production release of CoreFPU |
1. 특징
CoreFPU has the following key features:
- Supports Single and Double Precision Floating Numbers as per IEEE-754 Standard
- Supports Conversions as listed:
- Fixed-point to Floating-point conversion
- Floating-point to Fixed-point conversion
- Supports Arithmetic Operations as listed:
- Floating-point addition
- Floating-point subtraction
- Floating-point multiplication
- Provides the Rounding Scheme (Round to nearest even) for the Arithmetic Operations only
- Provides Flags for Overflow, Underflow, Infinity (Positive Infinity, Negative Infinity), Quiet NaN (QNaN) and Signalling NaN (SNaN) for Floating-Point Numbers.
- Supports Fully pipelined implementation of Arithmetic Operations
- Provides Provision to configure the Core for Design Requirements
기능 설명
- The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a technical standard for floating-point computation. The term floating-point refers to the radix point of the number (decimal point or binary point), which is placed anywhere with respect to the significant digits of the number.
A floating-point number is typically expressed in the scientific notation, with a fraction (F), and an exponent (E) of a certain radix (r), in the form of F × r^E. Decimal numbers use radix of 10 (F × 10^E); while binary numbers use radix of 2 (F × 2^E). - The representation of the floating-point number is not unique. For example, the number 55.66 is represented as 5.566 × 10^1, 0.5566 × 10^2, 0.05566 × 10^3, and so on. The fractional part is normalized. In the normalized form, there is only a single non-zero digit before the radix point. For example, decimal number 123.4567 is normalized as 1.234567 × 10^2; binary number 1010.1011B is normalized as 1.0101011B × 2^3.
- It is important to note that floating-point numbers suffer from loss of precision when represented with a fixed number of bits (for example, 32-bit or 64-bit). This is because there are an infinite number of real numbers (even within a small range from 0.0 to 0.1). On the other hand, an
n- bit binary pattern represents a finite 2^n distinct numbers. Hence, not all the real numbers are represented. The nearest approximation is used instead, which results in the loss of accuracy.
The single precision floating-point number is represented as follows:
- Sign bit: 1-bit
- Exponent width: 8 bits
- Significand precision: 24 bits (23 bits are explicitly stored)
Figure 2-1. 32-bit Frame
The double precision floating-point number is represented as follows:
- Sign bit: 1-bit
- Exponent width: 11 bits
- Significand precision: 53 bits (52 bits are explicitly stored)
Figure 2-2. 64-bit Frame The CoreFPU is the top-level integration of the two conversion modules (Fixed to Float point and Float to Fixed point) and three arithmetic operations (FP ADD, FP SUB, and FP MULT). The user can configure any one of the operations based on the requirement so that the resources are utilized for the selected operation.
The following figure shows the top level CoreFPU block diagram with ports.
Figure 2-3. CoreFPU Ports Block Diagram
The following table lists the width of the Input and Output ports. Table 2-1. Input and Output Port Width
신호 | Single Precision Width | Double Precision Width |
아인 | [31:0] | [63:0] |
큰 상자 | [31:0] | [63:0] |
아웃 | [31:0] | [63:0] |
pout | [31:0] | [63:0] |
Fixed-Point to Floating-Point (Conversion)
CoreFPU configured as fixed to floating-point infers the fixed-point to floating-point conversion module. The input (ain) to CoreFPU is any fixed-point number containing the integer and fractional bits. The CoreFPU configurator has the options to select the input integer and fraction widths. The input is valid on di_valid signal and output is valid on do_valid. The output (aout) of the fixed to float operation is in single or double precision floating-point format.
Example for fixed-point to floating-point conversion operation is listed in the following table.
표 2-2. 전ample for Fixed-Point to Floating-Point Conversion
Fixed-Point Number | Floating-Point Number | |||||
아인 | 정수 | 분수 | 아웃 | 징후 | 멱지수 | 가수 |
0x12153524 (32-bit) | 00010010000101010 | 011010100100100 | 0x4610a9a9 | 0 | 10001100 | 00100001010100110101001 |
0x0000000000008CCC
(64비트) |
0000000000000000000000000000000000000000000000001 | 000110011001100 | 0x3FF199999999999A | 0 | 01111111111 | 0001100110011001100110011001100110011001100110011010 |
Floating-Point to Fixed-Point (Conversion)
CoreFPU configured as floating to fixed-point infers the floating-point to fixed-point conversion module. The input (ain) to CoreFPU is any single or double precision floating-point number and produces an output (aout) in fixed-point format containing integer and fractional bits. The input is valid on di_valid signal and output is valid on do_valid. The CoreFPU configurator has the options to select the output integer and fraction widths.
Example for floating-point to fixed-point conversion operation is listed in the following table.
표 2-3. 전ample for Floating-Point to Fixed-Point Conversion
Floating-Point Number | Fixed-Point Number | |||||
아인 | 징후 | 멱지수 | 가수 | 아웃 | 정수 | 분수 |
0x41bd6783 (32-bit) | 0 | 10000011 | 01111010110011110000011 | 0x000bd678 | 00000000000010111 | 101011001111000 |
0x4002094c447c30d3
(64비트) |
0 | 10000000000 | 0010000010010100110001000100011111000011000011010011 | 0x0000000000012095 | 0000000000000000000000000000000000000000000000010 | 010000010010101 |
Floating-Point Addition (Arithmetic Operation)
CoreFPU configured as FP ADD infers the floating-point addition module. It adds the two floating-point numbers (ain and bin) and provides the output (pout) in floating-point format. The input and output are single or double precision floating-point numbers. The input is valid on di_valid signal and output is valid on do_valid. The core produce ovfl_fg (Overflow), qnan_fg (Quiet Not a Number), snan_fg (Signalling Not a Number), pinf_fg(Positive Infinity), and ninf_fg (Negative Infinity) flags based on the addition operation.
Examples for floating-point addition operation are listed in the following tables.
표 2-4. 전ample for Floating-Point Addition Operation (32-bit)
Floating-Point Value | 징후 | 멱지수 | 가수 |
Floating-point input 1 ain (0x4e989680) | 0 | 10011101 | 00110001001011010000000 |
Floating-point input 2 bin (0x4f191b40) | 0 | 10011110 | 00110010001101101000000 |
Floating-point addition output pout (0x4f656680) | 0 | 10011110 | 11001010110011010000000 |
표 2-5. 전ample for Floating-Point Addition Operation (64-bit)
Floating-Point Value | 징후 | 멱지수 | 가수 |
Floating-point input 1
ain (0x3ff4106ee30caa32) |
0 | 01111111111 | 0100000100000110111011100011000011001010101000110010 |
Floating-point input 2
bin (0x40020b2a78798e61) |
0 | 10000000000 | 0010000010110010101001111000011110011000111001100001 |
Floating-point addition output pout (0x400c1361e9ffe37a) | 0 | 10000000000 | 1100000100110110000111101001111111111110001101111010 |
Floating-Point Subtraction (Arithmetic Operation)
CoreFPU configured as FP SUB infers the floating-point subtraction module. It subtracts the two floating-point numbers (ain and bin) and provides the output (pout) in floating-point format. The input and output are single or double precision floating-point numbers. The input is valid on di_valid signal and output is valid on do_valid. The core produce ovfl_fg (Overflow), unfl_fg (underflow), qnan_fg (Quiet Not a Number), snan_fg (Signalling Not a Number), pinf_fg (Positive Infinity), and ninf_fg (Negative Infinity) flags based on the subtraction operation.
Examples for floating-point subtraction operation are listed in the following tables.
표 2-6. 전ample for Floating-Point Subtraction Operation (32-bit)
Floating-Point Value | 징후 | 멱지수 | 가수 |
Floating-point input 1 ain (0xac85465f) | 1 | 01011001 | 00001010100011001011111 |
Floating-point input 2 bin (0x2f516779) | 0 | 01011110 | 10100010110011101111001 |
Floating-point subtraction output pout (0xaf5591ac) | 1 | 01011110 | 10101011001000110101011 |
Floating-Point Value | 징후 | 멱지수 | 가수 |
Floating-point input 1
ain (0x405569764adff823) |
0 | 10000000101 | 0101011010010111011001001010110111111111100000100011 |
Floating-point input 2
bin (0x4057d04e78dee3fc) |
0 | 10000000101 | 0111110100000100111001111000110111101110001111111100 |
Floating-point subtraction output pout (0xc02336c16ff75ec8) | 1 | 10000000010 | 0011001101101100000101101111111101110101111011001000 |
Floating-Point Multiplication (Arithmetic Operation)
CoreFPU configured as FP MULT infers the floating-point multiplication module. It multiplies the two floating-point numbers (ain and bin) and provides the output (pout) in floating-point format. The input and output are single or double precision floating-point numbers. The input is valid on di_valid signal and output is valid on do_valid. The core produce ovfl_fg (Overflow), unfl_fg (Underflow), qnan_fg (Quiet Not a Number), snan_fg (Signalling Not a Number), pinf_fg (Positive Infinity), and ninf_fg (Negative Infinity) flags based on the multiplication operation.
Examples for floating-point multiplication operation are listed in the following tables.
표 2-8. 전ample for Floating-Point Multiplication Operation (32-bit)
Floating-Point Value | 징후 | 멱지수 | 가수 |
Floating-point input 1 ain (0x1ec7a735) | 0 | 00111101 | 10001111010011100110101 |
Floating-point input 2 bin (0x6ecf15e8) | 0 | 11011101 | 10011110001010111101000 |
Floating-point Multiplication output pout (0x4e21814a) | 0 | 10011100 | 01000011000000101001010 |
Floating-Point Value | 징후 | 멱지수 | 가수 |
Floating-point input 1
ain (0x40c1f5a9930be0df) |
0 | 10000001100 | 0001111101011010100110010011000010111110000011011111 |
Floating-point input 2
bin (0x400a0866c962b501) |
0 | 10000000000 | 1010000010000110011011001001011000101011010100000001 |
Floating-point multiplication output pout (0x40dd38a1c3e2cae9) | 0 | 10000001101 | 1101001110001010000111000011111000101100101011101001 |
Truth Table for Addition and Subtraction
The following truth tables list the values for addition and subtraction operation. Table 2-10. Truth Table for Addition
데이터 A | 데이터 B | 사인 비트 | 결과 | 과다 | 언더플로 | SNaN | QNaN | PINF | NINF |
QNaN/SNaN | x | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
x | QNaN/SNaN | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
영 | 영 | 0 | POSZERO | 0 | 0 | 0 | 0 | 0 | 0 |
영 | posfinite(y) | 0 | posfinite(y) | 0 | 0 | 0 | 0 | 0 | 0 |
영 | negfinite(y) | 1 | negfinite(y) | 0 | 0 | 0 | 0 | 0 | 0 |
영 | posinfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
영 | neginfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
posfinite(y) | 영 | 0 | posfinite(y) | 0 | 0 | 0 | 0 | 0 | 0 |
posfinite | posinfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
테이블 2-10. Truth Table for Addition (continued) | |||||||||
데이터 A | 데이터 B | 사인 비트 | 결과 | 과다 | 언더플로 | SNaN | QNaN | PINF | NINF |
posfinite | neginfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
negfinite(y) | 영 | 1 | negfinite(y) | 0 | 0 | 0 | 0 | 0 | 0 |
negfinite | posinfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
negfinite | neginfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
posinfinite | 영 | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posinfinite | posfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posinfinite | negfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posinfinite | posinfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posinfinite | neginfinite | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
neginfinite | 영 | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
neginfinite | posfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
neginfinite | negfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
neginfinite | posinfinite | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
neginfinite | neginfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
posfinite | posfinite | 0 | posfinite | 0 | 0 | 0 | 0 | 0 | 0 |
posfinite | posfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posfinite | posfinite | 0/1 | QNaN | 0 | 0 | 0 | 1 | 0 | 0 |
posfinite | posfinite | 0/1 | SNaN | 0 | 0 | 1 | 0 | 0 | 0 |
posfinite | posfinite | 0 | POSSNaN | 1 | 0 | 1 | 0 | 0 | 0 |
posfinite | negfinite | 0 | posfinite | 0 | 0 | 0 | 0 | 0 | 0 |
posfinite | negfinite | 1 | negfinite | 0 | 0 | 0 | 0 | 0 | 0 |
posfinite | negfinite | 0 | POSSNaN | 0 | 1 | 1 | 0 | 0 | 0 |
negfinite | posfinite | 0 | posfinite | 0 | 0 | 0 | 0 | 0 | 0 |
negfinite | posfinite | 1 | negfinite | 0 | 0 | 0 | 0 | 0 | 0 |
negfinite | posfinite | 0 | POSSNaN | 0 | 1 | 1 | 0 | 0 | 0 |
negfinite | negfinite | 1 | negfinite | 0 | 0 | 0 | 0 | 0 | 0 |
negfinite | negfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
negfinite | negfinite | 0/1 | QNaN | 0 | 0 | 0 | 1 | 0 | 0 |
negfinite | negfinite | 0/1 | SNaN | 0 | 0 | 1 | 0 | 0 | 0 |
negfinite | negfinite | 0 | POSSNaN | 1 | 0 | 1 | 0 | 0 | 0 |
데이터 A | 데이터 B | 사인 비트 | 결과 | 과다 | 언더플로 | SNaN | QNaN | PINF | NINF |
QNaN/SNaN | x | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
x | QNaN/SNaN | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
영 | 영 | 0 | POSZERO | 0 | 0 | 0 | 0 | 0 | 0 |
영 | posfinite(y) | 1 | negfinite(y) | 0 | 0 | 0 | 0 | 0 | 0 |
영 | negfinite(y) | 0 | posfinite(y) | 0 | 0 | 0 | 0 | 0 | 0 |
영 | posinfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
영 | neginfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posfinite(y) | 영 | 0 | posfinite(y) | 0 | 0 | 0 | 0 | 0 | 0 |
posfinite | posinfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
posfinite | neginfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
negfinite(y) | 영 | 1 | negfinite(y) | 0 | 0 | 0 | 0 | 0 | 0 |
negfinite | posinfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
테이블 2-11. Truth Table for Subtraction (continued) | |||||||||
데이터 A | 데이터 B | 사인 비트 | 결과 | 과다 | 언더플로 | SNaN | QNaN | PINF | NINF |
negfinite | neginfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posinfinite | 영 | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posinfinite | posfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posinfinite | negfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posinfinite | posinfinite | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
posinfinite | neginfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
neginfinite | 영 | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
neginfinite | posfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
neginfinite | negfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
neginfinite | posinfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
neginfinite | neginfinite | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
posfinite | posfinite | 0 | posfinite | 0 | 0 | 0 | 0 | 0 | 0 |
posfinite | posfinite | 1 | negfinite | 0 | 0 | 0 | 0 | 0 | 0 |
posfinite | posfinite | 0 | POSSNaN | 0 | 1 | 1 | 0 | 0 | 0 |
posfinite | negfinite | 0 | posfinite | 0 | 0 | 0 | 0 | 0 | 0 |
posfinite | negfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posfinite | negfinite | 0/1 | QNaN | 0 | 0 | 0 | 1 | 0 | 0 |
posfinite | negfinite | 0/1 | SNaN | 0 | 0 | 1 | 0 | 0 | 0 |
posfinite | negfinite | 0 | POSSNaN | 1 | 0 | 1 | 0 | 0 | 0 |
negfinite | posfinite | 1 | negfinite | 0 | 0 | 0 | 0 | 0 | 0 |
negfinite | posfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
negfinite | posfinite | 0/1 | QNaN | 0 | 0 | 0 | 1 | 0 | 0 |
negfinite | posfinite | 0/1 | SNaN | 0 | 0 | 1 | 0 | 0 | 0 |
negfinite | posfinite | 0 | POSSNaN | 1 | 0 | 1 | 0 | 0 | 0 |
negfinite | negfinite | 0 | posfinite | 0 | 0 | 0 | 0 | 0 | 0 |
negfinite | negfinite | 1 | negfinite | 0 | 0 | 0 | 0 | 0 | 0 |
negfinite | negfinite | 0 | POSSNaN | 0 | 1 | 1 | 0 | 0 | 0 |
중요한:
- They in the preceding tables denotes any number.
- The in the preceding tables denotes a don’t care condition.
Truth Table for Multiplication
The following truth table lists the values for multiplication operation.
Table 2-12. Truth Table for Multiplication
데이터 A | 데이터 B | 사인 비트 | 결과 | 과다 | 언더플로 | SNaN | QNaN | PINF | NINF |
QNaN/SNaN | x | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
x | QNaN/SNaN | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
영 | 영 | 0 | POSZERO | 0 | 0 | 0 | 0 | 0 | 0 |
영 | posfinite | 0 | POSZERO | 0 | 0 | 0 | 0 | 0 | 0 |
영 | negfinite | 0 | POSZERO | 0 | 0 | 0 | 0 | 0 | 0 |
영 | posinfinite | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
영 | neginfinite | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
테이블 2-12. Truth Table for Multiplication (continued) | |||||||||
데이터 A | 데이터 B | 사인 비트 | 결과 | 과다 | 언더플로 | SNaN | QNaN | PINF | NINF |
posfinite | 영 | 0 | POSZERO | 0 | 0 | 0 | 0 | 0 | 0 |
posfinite | posinfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posfinite | neginfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
negfinite | 영 | 0 | POSZERO | 0 | 0 | 0 | 0 | 0 | 0 |
negfinite | posinfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
negfinite | neginfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posinfinite | 영 | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
posinfinite | posfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posinfinite | negfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
posinfinite | posinfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posinfinite | neginfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
neginfinite | 영 | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
neginfinite | posfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
neginfinite | negfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
neginfinite | posinfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
neginfinite | neginfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posfinite | posfinite | 0 | posfinite | 0 | 0 | 0 | 0 | 0 | 0 |
posfinite | posfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
posfinite | posfinite | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
posfinite | posfinite | 0 | POSSNaN | 0 | 0 | 1 | 0 | 0 | 0 |
posfinite | posfinite | 0 | POSSNaN | 1 | 0 | 1 | 0 | 0 | 0 |
posfinite | posfinite | 0 | POSSNaN | 0 | 1 | 1 | 0 | 0 | 0 |
posfinite | negfinite | 1 | negfinite | 0 | 0 | 0 | 0 | 0 | 0 |
posfinite | negfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
posfinite | negfinite | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
posfinite | negfinite | 0 | POSSNaN | 0 | 0 | 1 | 0 | 0 | 0 |
posfinite | negfinite | 0 | POSSNaN | 1 | 0 | 1 | 0 | 0 | 0 |
posfinite | negfinite | 0 | POSSNaN | 0 | 1 | 1 | 0 | 0 | 0 |
negfinite | posfinite | 1 | negfinite | 0 | 0 | 0 | 0 | 0 | 0 |
negfinite | posfinite | 1 | neginfinite | 0 | 0 | 0 | 0 | 0 | 1 |
negfinite | posfinite | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
negfinite | posfinite | 0 | POSSNaN | 0 | 0 | 1 | 0 | 0 | 0 |
negfinite | posfinite | 0 | POSSNaN | 1 | 0 | 1 | 0 | 0 | 0 |
negfinite | posfinite | 0 | POSSNaN | 0 | 1 | 1 | 0 | 0 | 0 |
negfinite | negfinite | 0 | posfinite | 0 | 0 | 0 | 0 | 0 | 0 |
negfinite | negfinite | 0 | posinfinite | 0 | 0 | 0 | 0 | 1 | 0 |
negfinite | negfinite | 0 | POSQNaN | 0 | 0 | 0 | 1 | 0 | 0 |
negfinite | negfinite | 0 | POSQNaN | 0 | 0 | 1 | 0 | 0 | 0 |
negfinite | negfinite | 0 | POSQNaN | 1 | 0 | 1 | 0 | 0 | 0 |
negfinite | negfinite | 0 | POSQNaN | 0 | 1 | 1 | 0 | 0 | 0 |
중요한:
Sign Bit ‘0’ defines positive output and ‘1’ defines negative output.
The x in the preceding table denotes don’t care condition.
CoreFPU Parameters and Interface Signals
This section discusses the parameters in the CoreFPU Configurator settings and I/O signals.
구성 GUI 매개변수
There are number of configurable options that apply to the FPU unit as shown in the following table. If a configuration other than default is required, configuration dialog box is used to select appropriate values for the configurable option.
Table 3-1. CoreFPU Configuration GUI Parameters
매개변수 이름 | 기본 | 설명 |
정도 | 하나의 | Select the operation as required:
Single Precision |
변환 유형 | Fixed-point to Floating-point conversion | Select the operation as required:
|
Input Fraction Width1 | 15 | Configures the fractional point in the Input ain and bin signals
Valid range is 31–1 |
Output Fraction Width2 | 15 | Configures the fractional point in the Output aout signals
Valid range is 51–1 |
중요한:
- This parameter is configurable only during fixed-point to floating-point conversion.
- This parameter is configurable only during floating-point to fixed-point conversion.
입력 및 출력 신호(질문하기)
The following table lists the input and output port signals of CoreFPU.
Table 3-2. Port Description
신호 이름 | 너비 | 유형 | 설명 |
클락 | 1 | 입력 | Main system clock |
rstn | 1 | 입력 | Active-low asynchronous reset |
di_valid | 1 | 입력 | Active-high input valid
This signal indicates that the data present on ain[31:0], ain[63:0] and bin[31:0], bin[63:0] is valid. |
아인 | 32/64 | 입력 | A Input Bus (It is used for all operations) |
큰 상자1 | 32/64 | 입력 | B Input Bus (It is used for arithmetic operations only) |
아웃2 | 32/64 | 산출 | Output value when fixed to floating-point or floating to fixed-point conversion operations are selected. |
pout1 | 32/64 | 산출 | Output value when addition, subtraction, or multiplication operations are selected. |
테이블 3-2. Port Description (continued) | |||
신호 이름 | 너비 | 유형 | 설명 |
do_valid | 1 | 산출 | Active-high signal
This signal indicates that the data present on pout/aout data bus is valid. |
ovfl_fg3 | 1 | 산출 | Active-high signal
This signal indicates the overflow during floating-point operations. |
unfl_fg | 1 | 산출 | Active-high signal
This Signal indicates the underflow during floating point operations. |
qnan_fg3 | 1 | 산출 | Active-high signal
This signal indicates the Quiet Not a Number (QNaN) during floating-point operations. |
snan_fg | 1 | 산출 | Active-high signal
This signal indicates the Signalling Not-a-Number (SNaN) during floating point operations. |
pinf_fg3 | 1 | 산출 | Active-high signal
This signal indicates the positive infinity during floating-point operations. |
ninf_fg | 1 | 산출 | Active-high signal
This signal indicates the negative infinity during floating-point operations. |
중요한:
- This port is available only for floating-point addition, subtraction, or multiplication operations.
- This port is available only for fixed-point to floating-point and floating-point to fixed-point conversion operations.
- This port is available for floating-point to fixed-point, floating-point addition, floating-point subtraction, and floating-point multiplication.
Implementation of CoreFPU in Libero Design Suite
This section describes the implementation of CoreFPU in the Libero Design Suite.
스마트디자인
CoreFPU is available for download in the Libero IP catalog through the web repository. Once it is listed in the catalog, the core is instantiated using the SmartDesign flow. For information on using SmartDesign to configure, connect, and generate cores, see Libero SoC online help.
After configuring and generating the core instance, the basic functionality is simulated using the testbench supplied with the CoreFPU. The testbench parameters automatically adjust to the CoreFPU configuration. The CoreFPU is instantiated as a component of a larger design.
Figure 4-1. SmartDesign CoreFPU Instance for Arithmetic Operations
Figure 4-2. SmartDesign CoreFPU Instance for Conversion Operation
Fixed-Point to Floating-Point Conversion
During fixed-point to floating-point conversion, the Input Fraction Width is configurable. The Output Width is set to 32-bit for single precision and 64-bit for double precision floating-point by default.
To convert from fixed-point to floating-point, select Fixed to floating point Conversion type, as shown in the following figure.
Floating-Point to Fixed-Point
During floating-point to fixed-point conversion, the Output Fractional Width is configurable, and the Input Width is set to 32-bit for single precision and 64-bit for double precision floating-point by default.
To convert from floating-point to fixed-point, select Floating point to fixed Conversion type, as shown in the following figure.
Figure 4-4. CoreFPU Configurator for Floating Point to Fixed Floating-Point Addition/Subtraction/Multiplication
During floating-point addition, subtraction, and multiplication operation, the Input Fraction Width and Output Fraction Width are not configurable as these are floating-point arithmetic operations, and the Input/Output Width is set to 32-bit single precision and 64-bit for double precision floating-point by default.
The following figure shows the CoreFPU configurator for floating point subtraction operation.
Figure 4-5. CoreFPU Configurator for Floating Point Subtraction시뮬레이션(질문하기)
To run simulations, in the core configuration window, select User Testbench. After generating the CoreFPU, the pre-synthesis testbench Hardware Description Language (HDL) files는 Libero에 설치됩니다.
Simulation Waveforms (Ask a Question)
This section discusses the simulation waveforms for CoreFPU.
The following figures show the waveform of fixed-point to floating-point conversion for both 32-bit and 64-bit.
시스템 통합
다음 그림은 예를 보여줍니다ample of using the core. In this example, the design UART is used as a communication channel between the design and the host PC. The signals ain and bin (each of 32-bit or 64-bit width) are the inputs to the design from UART. After the CoreFPU receives the di_valid signal, it computes the result. After computing the result, the do_valid signal goes high and stores the result (aout/pout data) in the output buffer. This same procedure is applicable for conversion and arithmetic operations. For conversion operations, only input ain is sufficient whereas for arithmetic operations, both ain and bin inputs are required. Output aout is enabled for conversion operations and pout port is enabled for arithmetic operations.
그림 4-16. 전ample of the CoreFPU System
- Synthesis (Ask a Question)
To run synthesis on the CoreFPU, set the design root to the IP component instance and from the Libero design flow pane, run the Synthesis tool.
Place and Route (Ask a Question)
After the design is synthesized, run the Place-and-Route tool. CoreFPU requires no special placeand- route settings. - 사용자 테스트벤치(질문하기)
A user testbench is provided with the CoreFPU IP release. Using this testbench, you can verify functional behavior of CoreFPU.
A simplified block diagram of the user testbench is shown in the following figure. The user testbench instantiates the Configured CoreFPU design (UUT), and includes behavioral test data generator, necessary clock, and reset signals.
Figure 4-17. CoreFPU User Testbench
Important: You have to monitor the output signals in ModelSim simulator, see Simulation section.
추가 참조 (질문하기)
This section provides a list for additional information.
소프트웨어, 장치 및 하드웨어에 대한 업데이트 및 추가 정보를 보려면 다음을 방문하십시오.
Microchip FPGA 및 PLD의 지적 재산 페이지 web대지.
- Known Issues and Workarounds (Ask a Question)
There are no known issues and workarounds for CoreFPU v3.0. - Discontinued Features and Devices (Ask a Question)
이 IP 릴리스에는 중단된 기능이나 장치가 없습니다.
어휘
The following are the list of terms and definitions used in the document.
표 6-1. 용어 및 정의
용어 | 정의 |
플루언서 | 부동 소수점 단위 |
FP ADD | Floating-Point Addition |
FP SUB | Floating-Point Subtraction |
FP MULT | Floating-Point Multiplication |
해결된 문제
The following table lists all the resolved issues for the various CoreFPU releases.
표 7-1. 해결된 문제
풀어 주다 | 설명 |
3.0 | The following is the list of all resolved issues in the v3.0 release:
Case Number: 01420387 and 01422128 Added the rounding scheme logic (round to the nearest even number). |
2.1 | The following is the list of all resolved issues in the v2.1 release: The design encounters issues due to the presence of duplicate modules when multiple cores are instantiated. Renaming the CoreFPU IP instance results in an “Undefined module” error. |
1.0 | 최초 릴리스 |
Device Resource Utilization and Performance
The CoreFPU macro is implemented in the families listed in the following table.
Table 8-1. FPU PolarFire Unit Device Utilization for 32-Bit
FPGA Resources | 이용 | |||||||
가족 | 4루트 | 디에프에프 | 총 | Math Block | 장치 | 퍼센tage | 성능 | 숨어 있음 |
Fixed-Point to Floating-Point | ||||||||
폴라파이어® | 260 | 104 | 364 | 0 | MPF300T | 0.12 | 310MHz | 3 |
Floating-Point to Fixed-Point | ||||||||
폴라파이어 | 591 | 102 | 693 | 0 | MPF300T | 0.23 | 160MHz | 3 |
Floating-Point Addition | ||||||||
폴라파이어 | 1575 | 1551 | 3126 | 0 | MPF300T | 1.06 | 340MHz | 16 |
Floating-Point Subtraction | ||||||||
폴라파이어 | 1561 | 1549 | 3110 | 0 | MPF300T | 1.04 | 345MHz | 16 |
Floating-Point Multiplication | ||||||||
폴라파이어 | 465 | 847 | 1312 | 4 | MPF300T | 0.44 | 385MHz | 14 |
FPGA Resources | 이용 | |||||||
가족 | 4루트 | 디에프에프 | 총 | Math Block | 장치 | 퍼센tage | 성능 | 숨어 있음 |
Fixed-Point to Floating-Point | ||||||||
RTG4™ | 264 | 104 | 368 | 0 | RT4G150 | 0.24 | 160MHz | 3 |
Floating-Point to Fixed-Point | ||||||||
RTG4 | 439 | 112 | 551 | 0 | RT4G150 | 0.36 | 105MHz | 3 |
Floating-Point Addition | ||||||||
RTG4 | 1733 | 1551 | 3284 | 0 | RT4G150 | 1.16 | 195MHz | 16 |
Floating-Point Subtraction | ||||||||
RTG4 | 1729 | 1549 | 3258 | 0 | RT4G150 | 1.16 | 190MHz | 16 |
Floating-Point Multiplication | ||||||||
RTG4 | 468 | 847 | 1315 | 4 | RT4G150 | 0.87 | 175MHz | 14 |
FPGA Resources | 이용 | |||||||
가족 | 4루트 | 디에프에프 | 총 | Math Block | 장치 | 퍼센tage | 성능 | 숨어 있음 |
Fixed-Point to Floating-Point | ||||||||
폴라파이어® | 638 | 201 | 849 | 0 | MPF300T | 0.28 | 305MHz | 3 |
Floating-Point to Fixed-Point | ||||||||
폴라파이어 | 2442 | 203 | 2645 | 0 | MPF300T | 0.89 | 110MHz | 3 |
Floating-Point Addition | ||||||||
폴라파이어 | 5144 | 4028 | 9172 | 0 | MPF300T | 3.06 | 240MHz | 16 |
Floating-Point Subtraction | ||||||||
폴라파이어 | 5153 | 4026 | 9179 | 0 | MPF300T | 3.06 | 250MHz | 16 |
Floating-Point Multiplication | ||||||||
폴라파이어 | 1161 | 3818 | 4979 | 16 | MPF300T | 1.66 | 340MHz | 27 |
FPGA Resources | 이용 | |||||||
가족 | 4루트 | 디에프에프 | 총 | Math Block | 장치 | 퍼센tage | 성능 | 숨어 있음 |
Fixed-Point to Floating-Point | ||||||||
RTG4™ | 621 | 201 | 822 | 0 | RT4G150 | 0.54 | 140MHz | 3 |
Floating-Point to Fixed-Point | ||||||||
RTG4 | 1114 | 203 | 1215 | 0 | RT4G150 | 0.86 | 75MHz | 3 |
Floating-Point Addition | ||||||||
RTG4 | 4941 | 4028 | 8969 | 0 | RT4G150 | 5.9 | 140MHz | 16 |
Floating-Point Subtraction | ||||||||
RTG4 | 5190 | 4026 | 9216 | 0 | RT4G150 | 6.07 | 130MHz | 16 |
Floating-Point Multiplication | ||||||||
RTG4 | 1165 | 3818 | 4983 | 16 | RT4G150 | 3.28 | 170MHz | 27 |
Important: To increase the frequency, select Enable retiming option in synthesis setting.
개정 내역
개정 내역은 문서에서 구현된 변경 사항을 설명합니다. 변경 사항은 최신 출판물부터 시작하여 개정별로 나열됩니다.
마이크로칩 FPGA 지원
Microchip FPGA 제품 그룹은 고객 서비스, 고객 기술 지원 센터, web사이트 및 전 세계 영업 사무소. 고객은 이미 질문에 대한 답변을 받았을 가능성이 높으므로 지원팀에 문의하기 전에 Microchip 온라인 리소스를 방문하는 것이 좋습니다.
를 통해 기술 지원 센터에 문의하십시오. web사이트에서 www.microchip.com/support. FPGA 디바이스 부품 번호를 언급하고 적절한 케이스 카테고리를 선택하고 디자인을 업로드하십시오. files 기술 지원 사례를 만드는 동안.
제품 가격, 제품 업그레이드, 업데이트 정보, 주문 상태 및 승인과 같은 비기술적 제품 지원에 대해서는 고객 서비스에 문의하십시오.
- 북미에서 전화하려면 800.262.1060으로 전화하세요.
- 전 세계에서 650.318.4460으로 전화하세요.
- 팩스: 전 세계 어디에서나 650.318.8044
마이크로칩 정보
상표
"Microchip" 이름과 로고, "M" 로고 및 기타 이름, 로고 및 브랜드는 미국 및/또는 기타 국가에서 Microchip Technology Incorporated 또는 그 계열사 및/또는 자회사의 등록 및 미등록 상표입니다("Microchip 상표"). Microchip 상표에 대한 정보는 다음에서 찾을 수 있습니다. https://www.microchip.com/en-us/about/legal-information/microchip-trademarks
ISBN: 979-8-3371-0947-3
법적 고지
이 간행물과 여기에 있는 정보는 Microchip 제품을 설계, 테스트 및 응용 프로그램과 통합하는 것을 포함하여 Microchip 제품에만 사용할 수 있습니다. 이 정보를 다른 방식으로 사용하는 것은 이 약관을 위반하는 것입니다. 장치 응용 프로그램에 관한 정보는 귀하의 편의를 위해서만 제공되며 업데이트로 대체될 수 있습니다. 애플리케이션이 사양을 충족하는지 확인하는 것은 귀하의 책임입니다. 추가 지원이 필요한 경우 지역 Microchip 영업 사무소에 문의하거나 다음에서 추가 지원을 받으십시오. www.microchip.com/en-us/support/design-help/client-support-services
이 정보는 MICROCHIP에서 "있는 그대로" 제공합니다. MICROCHIP은 비침해, 상품성 및 특정 목적에의 적합성에 대한 묵시적 보증을 포함하되 이에 국한되지 않는 정보와 관련하여 명시적이든 묵시적이든, 서면이든 구두이든, 법률적이든 기타이든 어떠한 종류의 진술이나 보증도 하지 않습니다. 또는 그 상태, 품질 또는 성능과 관련된 보증도 하지 않습니다.
어떠한 경우에도 MICROCHIP은 정보 또는 그 사용과 관련된 간접적, 특수적, 징벌적, 우발적 또는 결과적 손실, 피해, 비용 또는 경비에 대해 어떠한 원인으로 발생하든, MICROCHIP이 가능성을 통보받았거나 피해가 예측 가능한 경우에도 책임을 지지 않습니다. 법률에서 허용하는 최대 범위 내에서 정보 또는 그 사용과 관련된 모든 청구에 대한 MICROCHIP의 총 책임은 귀하가 정보에 대해 MICROCHIP에 직접 지불한 수수료 금액을 초과하지 않습니다(있는 경우).
생명 유지 및/또는 안전 애플리케이션에서 Microchip 장치를 사용하는 것은 전적으로 구매자의 위험이며, 구매자는 그러한 사용으로 인해 발생하는 모든 손해, 청구, 소송 또는 비용으로부터 Microchip을 방어, 보상하고 무해하게 보호하는 데 동의합니다. 달리 명시되지 않는 한, Microchip 지적 재산권에 따라 묵시적 또는 기타 방식으로 라이선스가 양도되지 않습니다.
Microchip Devices 코드 보호 기능
Microchip 제품의 코드 보호 기능에 대한 자세한 내용은 다음과 같습니다.
- 마이크로칩 제품은 해당 마이크로칩 데이터 시트에 포함된 사양을 충족합니다.
- Microchip은 자사 제품군이 의도된 방식으로, 작동 사양 내에서, 정상적인 조건에서 사용될 경우 안전하다고 믿습니다.
- Microchip은 지적 재산권을 소중히 여기고 적극적으로 보호합니다. Microchip 제품의 코드 보호 기능을 위반하려는 시도는 엄격히 금지되며 디지털 밀레니엄 저작권법을 위반할 수 있습니다.
- Microchip이나 다른 반도체 제조업체는 코드의 보안을 보장할 수 없습니다. 코드 보호는 제품이 "깨지지 않는다"는 것을 보장한다는 것을 의미하지 않습니다. 코드 보호는 끊임없이 진화하고 있습니다. Microchip은 제품의 코드 보호 기능을 지속적으로 개선하기 위해 최선을 다하고 있습니다.
문서 / 리소스
![]() |
MICROCHIP CoreFPU Core Floating Point Unit [PDF 파일] 사용자 가이드 v3.0, v2.1, v2.0, v1.0, CoreFPU Core Floating Point Unit, Core Floating Point Unit, Floating Point Unit, Point Unit |