Microsemi DG0618 Su'esu'ega ma Fa'asa'oga ile SmartFusion2 Devices e fa'aaoga ai le DDR Memory

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Su'esu'ega sese ma Fa'asa'oga ile SmartFusion2 Devices e fa'aaoga ai le DDR Memory

Folasaga
I se si'osi'omaga fa'aletonu e tasi (SEU), o le manatua avanoa fa'afuase'i (RAM) e faigofie ona fa'aletonu le tumau e mafua mai i ion mamafa.
O lenei pepa o loʻo faʻamatalaina ai le EDAC gafatia o le SoC FPGA, lea e faʻaaogaina i talosaga ma manatuaga e fesoʻotaʻi atu i le microcontroller subsystem (MSS) DDR (MDDR).
O le EDAC controllers o loʻo faʻatinoina i masini SmartFusion2 e lagolagoina le faʻasaʻoina o mea sese e tasi ma le faʻaluaina o mea sese (SECDED). O manatuaga uma—e fa'aleleia le manatua ole avanoa fa'afuase'i (eSRAM), DDR, DDR, maualalo le malosi (LPDDR)—i totonu o masini SmartFusion2 MSS e puipuia e le SECDED. O le DDR synchronous dynamic random access memory (SDRAM) e mafai ona avea ma DDR2, DDR3, poʻo LPDDR1, faʻalagolago i le MDDR configuration ma meafaigaluega ECC gafatia.
O le SmartFusion2 MDDR subsystem e lagolagoina densities manatua e oo atu i le 4 GB. I lenei demo, e mafai ona e filifilia soʻo se nofoaga e manatua ai le 1 GB i le avanoa tuatusi DDR (0xA0000000 i le 0xDFFFFFFF).
Pe a mafai SECDED:

• O se fa'agaioiga tusitusi e fa'atatau ma fa'aopoopo i ai le 8 bits o le SECDED code (i 64 bits uma o fa'amaumauga)
• O se fa'agaioiga faitau e faitau ma siaki fa'amaumauga fa'asaga i le code SECDED na teuina e lagolago ai le fa'asa'oga sese 1-bit ma le su'esu'eina o mea sese 2-bit.

O le faʻataʻitaʻiga o loʻo i lalo o loʻo faʻamatalaina ai le poloka poloka o SmartFusion2 EDAC ile DDR SDRAM.

Ata 1 • Fa'afanua Poloka Tulaga Maualuga

Ole vaega ole EDAC ole DDR e lagolagoina mea nei:

1.  SECDED masini
2. Tuuina atu faʻalavelave i le ARM Cortex-M3 processor ma le ie FPGA i luga o le mauaina o se mea sese 1-bit poʻo le 2-bit sese.
3. Teuina le numera o mea sese 1-bit ma 2-bit i tusi resitala faʻailoga sese
4. Teu le tuatusi o le mea sese 1-bit po'o le 2-bit mulimuli na aafia ai le nofoaga manatua
5. Teu le 1-bit po'o le 2-bit fa'amatalaga sese ile SECDED resitala
6. e maua ai faailo pasi sese i le ie FPGA

Mo nisi fa'amatalaga e uiga i le EDAC, va'ai UG0443: SmartFusion2 ma IGLOO2 FPGA Security and Reliability User Guide ma UG0446: SmartFusion2 ma IGLOO2 FPGA High-Speed ​​DDR Interfaces User Guide.

Fuafuaga Manaomia
O le laulau o lo'o i lalo o lo'o lisiina ai mea e mana'omia mo le mamanu.

Laulau 1 • Fuafuaga Manaomia

• Fuafuaga Manaomia Fa'amatalaga
• Meafaigaluega Manaomia
• SmartFusion2 Advanced Development Kit laupapa Rev B pe mulimuli ane
• FlashPro5 programmer pe mulimuli ane
• USB A i le mini-B uaea USB
• Fa'afeso'ota'i eletise 12 V
• DDR3 Afafine laupapa
• Faiga Fa'atino So'o se 64-bit po'o le 32-bit Windows XP SP2
• So'o se 64-bit po'o le 32-bit Windows 7
• Polokalama Manaoga
• Libero® System-on-Chip (SoC) v11.8
• SoftConsole v4.0
• FlashPro polokalame polokalame v11.8
• Talia PC Aveta'avale USB i UART aveta'avale
• Ta'iala e fa'atino fa'ata'ita'iga Microsoft .NET Framework 4 client

Fa'ata'ita'iga Fuafuaga
Le mamanu demo files o loʻo avanoa mo le siiina mai le ala o loʻo i lalo i le Microsemi webnofoaga: http://soc.microsemi.com/download/rsc/?f=m2s_dg0618_liberov11p8_df
Le mamanu demo filee aofia ai:

• DDR Configuration File
• DDR_EDAC
• Polokalama files
• GUI fa'atino
• Faitau a'u file

O le fa'ata'ita'iga o lo'o i lalo o lo'o fa'amatalaina ai le fausaga pito i luga ole mamanu files. Mo nisi fa'amatalaga, va'ai le readme.txt file.

Ata 2 • Fa'ata'ita'iga Fa'ata'ita'iga Fa'atulagaina Tulaga Maualuga

Fa'atino Fa'ata'ita'iga
O le MDDR subsystem o lo'o i ai se fa'atonu fa'atonu EDAC. E iloa e le EDAC se mea sese 1-bit po'o le 2-bit sese pe a faitau fa'amaumauga mai le manatua. Afai e iloa e le EDAC le sese 1-bit, e faʻasaʻo e le pule o le EDAC le mea sese. Afai e mafai e le EDAC mo mea sese uma 1-bit ma 2-bit, o lo'o fa'atupula'ia fa'asologa o mea sese i totonu o tusi resitala ma fa'atupuina fa'alavelave tutusa ma fa'ailoga pasi sese i le ie FPGA.
E tupu lenei mea i le taimi moni. Ina ia faʻaalia lenei mea SECDED, o se mea sese e faʻafeiloaʻi ma le lima ma mataʻituina le suʻesuʻeina ma le faasaʻoina.
O lenei faʻataʻitaʻiga mamanu e aofia ai le faʻatinoina o laasaga nei:

1. Fa'aola le EDAC
2. Tusi faʻamatalaga i le DDR
3. Faitau faʻamatalaga mai le DDR
4. Taofi le EDAC
5. Fa'aleaga 1 pe 2 bits
6. Tusi faʻamatalaga i le DDR
7. Fa'aola le EDAC
8. Faitau faʻamatalaga
9. I le tulaga o se mea sese 1-bit, e faʻasaʻo e le pule o le EDAC le mea sese, faʻafou le resitala tulaga tutusa, ma tuʻuina atu faʻamaumauga o loʻo tusia i le Laasaga 2 i le faʻagaioiga faitau na faia i le Laasaga 8.
10. I le tulaga o se 2-bit sese, o se faʻalavelave tutusa e faʻatupuina ma e tatau i le talosaga ona faʻasaʻo faʻamaumauga pe faia le gaioiga talafeagai i le faʻalavelave faʻalavelave. O nei metotia e lua o loʻo faʻaalia i lenei demo.

E lua suʻega o loʻo faʻatinoina i lenei faʻataʻitaʻiga: suʻega taʻavale ma suʻega tusi lesona ma e faʻatatau i mea sese uma e lua 1-bit ma 2-bit.

Su'ega Loop
E fa'atino le su'ega ta'amilo pe a maua e masini SmartFusion2 se fa'atonuga ole su'ega mai le GUI. I le taimi muamua, o lo'o tu'u uma fa'ailoga sese ma resitara fa'atatau i le EDAC i le tulaga RESET.
O laasaga o loʻo mulimuli mai o loʻo faʻatinoina mo suʻesuʻega taʻitasi.

1. Fa'aaga le pule EDAC
2. Tusi faʻamatalaga i le nofoaga patino DDR manatua
3. Ta'e le pule EDAC
4. Tusi le 1-bit po'o le 2-bit mea sese fa'aoso fa'amatalaga i le nofoaga e tasi e manatua ai le DDR
5. Fa'aaga le pule EDAC
6. Faitau faʻamatalaga mai le nofoaga e tasi e manatua ai le DDR
7. Auina atu le 1-bit poʻo le 2-bit faʻamatalaga sese ma le 1-bit faʻasaʻoina faʻamatalaga i le tulaga o le 1-bit sese i le GUI

Su'ega Tusia
O lenei metotia e mafai ai ona faʻatagaina le suʻega tusi o le 1-bit faʻamaonia mea sese ma le faʻasaʻoina ma le 2-bit faʻamatalaga sese mo le tuatusi manatua DDR (0xA0000000 i le 0xDFFFFFFF) faʻatasi ai ma le amataga. O se mea sese 1-bit/2-bit e fa'afeiloa'i ma le lima i se tuatusi manatua DDR filifilia. O faʻamatalaga tuʻuina atu o loʻo tusia i le nofoaga manatua DDR filifilia ma le EDAC ua mafai. O fa'amatalaga fa'aletonu 1-bit po'o le 2-bit sese e tusi i le nofoaga e tasi e manatua ai ma le EDAC ua le atoatoa. O faʻamatalaga i luga o le 1-bit poʻo le 2-bit mea sese ua iloa pe a faitau faʻamatalaga mai le nofoaga e tasi e manatua ai ma le EDAC ua mafai. Le fa'atonu DMA maualuga
(HPDMA) e faʻaaogaina e faitau ai faʻamatalaga mai le DDR memory. O le lua-bit error detection interrupt handler e faʻatinoina e fai le gaioiga talafeagai pe a iloa se mea sese 2-bit.
O le fa'ata'ita'iga o lo'o i lalo o lo'o fa'amatalaina ai le fa'atinoga o fa'ata'ita'iga a le EDAC.

Ata 3 • Fa'asologa o Fuafuaga

Fa'aaliga: Mo se mea sese 2-bit, pe a faitau e le Cortex-M3 processor le faʻamatalaga, o le code execution e alu i totonu o le faʻalavelave faʻaletonu, ona o le faʻalavelave na maua ua tuai ona tali atu le processor. I le taimi e tali atu ai i le faʻalavelave, atonu ua uma ona pasia faʻamaumauga ma faʻafuaseʻi ona faʻalauiloa se poloaiga. O le i'uga, ua taofia e le HRESP le faiga o fa'amatalaga sese. O le su'esu'eina o mea sese 2-bit e fa'aaoga ai le HPDMA e faitau ai fa'amatalaga mai le nofoaga o le tuatusi DDR, lea e fa'atonuina ai le fa'agaioiga e faitau fa'amatalaga o lo'o i ai se mea sese 2-bit ma e tatau i le faiga ona faia se gaioiga talafeagai e toe fa'aleleia ai (ECC interrupt Handler).

Fa'atulaga le Fa'ata'ita'iga Design
O lenei vaega o loʻo faʻamatalaina le seti o le SmartFusion2 Advanced Development Kit, le GUI filifiliga, ma le faʻaogaina o le faʻataʻitaʻiga mamanu.
O laasaga nei o loʻo faʻamatalaina pe faʻapefea ona seti le demo:

1. Fa'afeso'ota'i le tasi pito o le USB mini-B cable i le feso'ota'iga J33 o lo'o tu'uina atu i le SmartFusion2 Advanced Development Kit board. Faʻafesoʻotaʻi le isi pito o le USB cable i le PC talimalo. E tatau ona fa'amumu le moli fa'avevela (LED) DS27, e ta'u mai ai ua fa'amauina le so'oga UART. Ia mautinoa o le USB i UART alalaupapa avetaʻavale e otometi ona iloa (e mafai ona faʻamaonia i le Device Manager), e pei ona faʻaalia i le ata o loʻo i lalo.
   Ata 4 • USB i UART Bridge Aveta'avale
   
   Afai e le faʻapipiʻiina avetaavale alalaupapa USB i UART, download ma faʻapipiʻi avetaavale mai: www.microsemi.com/soc/documents/CDM_2.08.24_WHQL_Certified.zip.
2. Faʻafesoʻotaʻi faʻaulu i luga o le SmartFusion2 Advanced Development Kit laupapa, e pei ona faʻaalia i le Laulau 4, itulau 11. E tatau ona tape le ki o le eletise SW7, aʻo faia fesoʻotaʻiga osooso.

Ata 5 • Fa'atonuga a le SmartFusion2 Advanced Development Kit Board

 Fa'amatalaga fa'aoga fa'akalafi
O lenei vaega o loʻo faʻamatalaina le DDR - EDAC Demo GUI.

Ata 6 • DDR – EDAC Demo GUI

E lagolagoina e le GUI vaega nei:

1. Filifiliga o le COM port ma le Baud Rate
2. Filifiliga o le 1-bit fa'asa'o mea sese po'o le 2-bit fa'amatalaga sese
3. Fa'asinomaga fanua e tusi pe faitau ai fa'amatalaga i po'o mai le tuatusi DDR fa'apitoa
4. Fa'amatalaga fanua e tusi pe faitau fa'amatalaga i po'o mai le tuatusi DDR fa'apitoa
5. Vaega Serial Console e lolomi ai fa'amatalaga tulaga na maua mai le talosaga
6. Enable EDAC/Disable EDAC: Fa'aola pe tape le EDAC
7. Tusi: Fa'ataga le tusiaina o fa'amatalaga i le tuatusi fa'apitoa
8.  Faitau: Fa'ataga le faitau fa'amatalaga mai le tuatusi fa'apitoa
9. Su'ega ta'avale ON/OFF: Fa'ataga le su'ega o le masini EDAC i se auala fa'aoga
10.  Amataina: Fa'ataga e fa'amataina le nofoaga e manatua muamua (i lenei fa'ata'ita'iga A0000000-A000CFFF)

Fa'atino le Fa'ata'ita'iga Design
O laasaga nei o loʻo faʻamatalaina pe faʻafefea ona faʻatino le mamanu:

1. Su'e le ki o le sapalai, SW7.
2. Polokalama le masini SmarFusion2 ma le polokalame file saunia i le mamanu files.(\PolokalameFile\EDAC_DDR3.stp) e faʻaaoga ai le FlashPro design software, e pei ona faʻaalia i le ata o loʻo i lalo.
   Ata 7 • Fa'amalama Polokalama FlashPro
   
3. Oomi le ki SW6 e toe setiina le laupapa pe a uma polokalame manuia.
4. Tatala le EDAC_DDR Demo GUI e mafai ona fa'atinoina file avanoa i le mamanu files (\GUI Executable\ EDAC_DDR.exe). O loʻo faʻaalia le faamalama GUI, e pei ona faʻaalia i le Ata 8, itulau 9.
5. Kiliki Fesoʻotaʻi, e filifilia le COM port ma faʻavae le fesoʻotaʻiga. Feso'ota'i suiga o le filifiliga i le Disconnect.
6. Filifili le 1-bit Error Correction tab poʻo le 2-bit Error Detection.
7. E mafai ona faia su'ega Tusia ma Loop.
8. Kiliki Initialize e amata ai le DDR memory e fai ai su'ega Tusia ma Loop, o se fe'au fa'amae'aina o lo'o fa'aalia ile Serial Console, e pei ona fa'aalia i le Ata 8, itulau 9.

Ata 8 • Fa'amalama Fa'amae'aina o le amataga

Fa'atino Su'ega Loop
Kiliki Loop Test ON. O lo'o fa'agasolo i le fa'aoga fa'aoga e fa'aauau ai le fa'asa'oga ma le su'esu'eina o mea sese. O gaioiga uma e faia i le SmartFusion2 masini o loʻo faʻamauina i le vaega Serial Console o le GUI.

Laulau 2 • Fa'aoga DDR3 Fa'aoga ile Su'ega Loop

• Manatua DDR3
• Fa'asa'oga sese 1-bit 0xA0008000
• 2-bit iloa mea sese 0xA000C000

Fa'atino Su'ega Tusi Ta'iala
I lenei metotia, o mea sese e faʻafeiloaʻi ma le lima e faʻaaoga ai le GUI. Fa'aoga la'asaga nei e fa'atino ai le fa'asa'oga 1-bit po'o le su'esu'eina o mea sese 2-bit.

Laulau 3 • DDR3 Fa'amanatuga Fa'aaoga ile Su'ega Tusia

Tulaga Ulufale ma Fa'amaumauga (fa'aoga 32-bit Hexadecimal values).

• Manatua DDR3
• Fa'asa'oga sese 1-bit 0xA0000000-0xA0004000
• 2-bit su'esu'ega sese 0xA0004000-0xA0008000

1. Kiliki Enable EDAC.
2. Kiliki Tusi.
3. Kiliki Disable EDAC.
4. Suia se fasi mea se tasi (i le tulaga o le 1-bit fa'asa'oga sese) po'o le lua fasi mea (i le tulaga o le 2-bit mea sese e iloa ai) i le Fa'amatalaga Fa'amatalaga (fa'ailoa sese).
5. Kiliki Tusi.
6. Kiliki Enable EDAC.
7. Kiliki Faitau.
8. Mataʻituina Faʻaaliga Faʻamatalaga Faʻamatalaga ma Faʻamatalaga Faʻamatalaga ile GUI. O le numera o mea sese e faʻatuputeleina ile 1.

O le 1-bit error loop correction window o loʻo faʻaalia i le ata o loʻo i lalo.

Ata 9 • 1-bit Error Loop Detection Window

O le 2-bit error detection manual window o loʻo faʻaalia i le ata o loʻo i lalo.

Ata 10 • 2-bit Fa'amalama Fa'ailoga Fa'amatalaga Fa'amatalaga

Fa'ai'uga
O lenei fa'aaliga fa'aalia SmartFusion2 SECDED gafatia mo le MDDR subsystem.

Fa'aopoopoga: Fa'atonuga o le Jumper

O le laulau o loʻo i lalo o loʻo faʻaalia uma ai tagata osooso e manaʻomia e seti i luga o le SmartFusion2 Advanced Development Kit.

Fuafuaga 4 • SmartFusion2 Advanced Development Kit Jumper Settings

Tu'u : Pin (Mai) : Pin (I) : Fa'amatalaga

• J116, J353, J354, J54 1 2 O tulaga ia e le mafai ona osooso o le Advanced
• J123 2 3 laupapa Pusa Atina'e. Ia mautinoa o lo'o fa'atutu lelei nei mea osooso.
• J124, J121, J32 1 2 JTAG polokalame e ala ile FTDI

DG0618 Fa'ata'ita'iga Taiala Toe Iloiloga 4.0

Pepa / Punaoa

Microsemi DG0618 Su'esu'ega ma Fa'asa'oga ile SmartFusion2 Devices e fa'aaoga ai le DDR Memory [pdf] Taiala mo Tagata Fa'aoga DG0618 Su'esu'ega ma Fa'asa'oga i SmartFusion2 Devices e fa'aaoga ai le DDR Memory, DG0618, Fa'amatalaga Fa'aletonu ma Fa'asa'oga ile SmartFusion2 Devices e fa'aaoga ai le DDR Memory, SmartFusion2 Devices e fa'aaoga ai le DDR Memory, DDR Memory.

Fa'asinomaga

• Tusi Taiala