intel FPGA Integer Arithmetic IP Cores User Guide

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1 FPGA Integer Arithmetic IP Cores

2 Pepa / Punaoa

2.1 Fa'asinomaga

3 Fa'amatalaga Fa'atatau

FPGA Integer Arithmetic IP Cores

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Intel FPGA Integer Arithmetic IP Cores User Guide
Fa'afou mo le Intel® Quartus® Prime Design Suite: 20.3

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UG-01063

ID: 683490 Fa'aliliuga: 2020.10.05

Mataupu
Mataupu
1. Intel FPGA Integer Arithmetic IP Cores……………………………………………………………….. 5
2. LPM_COUNTER (Counter) IP Core………………………………………………………………………….. 7 2.1. Vaega ………………………………………………………………………………………7 2.2. Verilog HDL Prototype…………………………………………………………………………………….. 8 2.3. Ta'utinoga Vaega VHDL………………………………………………………………………….8 2.4. VHDL LIBRARY_USE Tautinoga………………………………………………………………………… 9 2.5. Taulaga………………………………………………………………………………………………..9 2.6. Parata ……………………………………………………………………………………… 10
3. LPM_DIVIDE (Vaevaeina) Intel FPGA IP Core……………………………………………………………….. 12 3.1. Fa'ailoga ………………………………………………………………………………………. 12 3.2. Verilog HDL Prototype………………………………………………………………………… 12 3.3. Ta'utinoga Vaega VHDL………………………………………………………………………….. 13 3.4. VHDL LIBRARY_USE Tautinoga…………………………………………………………………………. 13 3.5. Taulaga……………………………………………………………………………………………… 13 3.6. Parameter ……………………………………………………………………………………… 14
4. LPM_MULT (Faatele) IP Core…………………………………………………………………………. 16 4.1. Fa'ailoga ………………………………………………………………………………………. 16 4.2. Verilog HDL Prototype………………………………………………………………………… 17 4.3. Ta'utinoga Vaega VHDL………………………………………………………………………….. 17 4.4. VHDL LIBRARY_USE Tautinoga…………………………………………………………………………. 17 4.5. Faailoga……………………………………………………………………………………………… 18 4.6. Parameter mo Stratix V, Arria V, Afa V, ma Intel Cyclone 10 LP Meafaigaluega……………… 18 4.6.1. Laulau Lautele………………………………………………………………………………18 4.6.2. Laulau Lautele 2 …………………………………………………………………………… 19 4.6.3. Fa'apa paipa……………………………………………………………………………… 19 4.7. Parameter mo Intel Stratix 10, Intel Arria 10, ma Intel Cyclone 10 GX Devices........... 20 4.7.1. Laulau Lautele………………………………………………………………………………20 4.7.2. Laulau Lautele 2 …………………………………………………………………………… 20 4.7.3. Fa'apa paipa……………………………………………………………………………………21
5. LPM_ADD_SUB (Fa'aopoopo/Tu'u'ese)………………………………………………………………………… 22 5.1. Fa'ailoga ………………………………………………………………………………………. 22 5.2. Verilog HDL Prototype………………………………………………………………………… 23 5.3. Ta'utinoga Vaega VHDL………………………………………………………………………….. 23 5.4. VHDL LIBRARY_USE Tautinoga …………………………………………………………………. 23 5.5. Taulaga……………………………………………………………………………………………… 23 5.6. Parameter ……………………………………………………………………………………… 24
6. LPM_COMPARE (Fa'atusatusa)………………………………………………………………………… 26 6.1. Fa'ailoga ………………………………………………………………………………………. 26 6.2. Verilog HDL Prototype………………………………………………………………………… 27 6.3. Ta'utinoga Vaega VHDL………………………………………………………………………….. 27 6.4. VHDL LIBRARY_USE Tautinoga…………………………………………………………………………. 27 6.5. Taulaga……………………………………………………………………………………………… 27 6.6. Parameter…………………………………………………………………………………… 28

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7. ALTECC (Fa'ailoga Fa'asa'oga Sese: Encoder/Decoder) IP Autu………………………………………… 30
7.1. ALTECC Encoder Features…………………………………………………………………………..31 7.2. Verilog HDL Prototype (ALTECC_ENCODER)……………………………………………………. 32 7.3. Verilog HDL Prototype (ALTECC_DECODER)……………………………………………………. 32 7.4. Ta'utinoga Vaega VHDL (ALTECC_ENCODER)……………………………………………33 7.5. Ta'utinoga Vaega VHDL (ALTECC_DECODER)……………………………………………………33 7.6. VHDL LIBRARY_USE Tautinoga…………………………………………………………………………. 33 7.7. Encoder Taulaga……………………………………………………………………………………………… 33 7.8. Taulaga Decoder…………………………………………………………………………………………34 7.9. Fa'ailoga Fa'ailoga ……………………………………………………………………………………… 34 7.10. Fa'asologa o le Decoder …………………………………………………………………………………… 35
8. Intel FPGA Multiply Adder IP Core………………………………………………………………. 36
8.1. Fa'ailoga ………………………………………………………………………………………. 37 8.1.1. Fa'aopoopo muamua…………………………………………………………………………………… 38 8.1.2. Tusi Resitala Fa'atuai o le Systolic……………………………………………………………… 40 8.1.3. Mu'i uta Tumau………………………………………………………………………… 43 8.1.4. Fa'aputuga Faalua………………………………………………………………………… 43
8.2. Verilog HDL Prototype………………………………………………………………………… 44 8.3. Ta'utinoga Vaega VHDL………………………………………………………………………….. 44 8.4. VHDL LIBRARY_USE Tautinoga …………………………………………………………………. 44 8.5. Faailoga……………………………………………………………………………………………… 44 8.6. Parameter………………………………………………………………………………………… 47
8.6.1. Laulau Lautele………………………………………………………………………………47 8.6.2. Faiga Fa'aopoopo Faila………………………………………………………………………….. 47 8.6.3. Laupapa Faatele………………………………………………………………………….. 49 8.6.4. Lautusi Tusitala……………………………………………………………………………………. 51 8.6.5. Fa'aputuga Fa'aputu………………………………………………………………………….. 53 8.6.6. Systolic/Chainout Tab……………………………………………………………………. 55 8.6.7. Fa'apa paipa……………………………………………………………………………… 56
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core…………………… 57
9.1. Fa'ailoga ………………………………………………………………………………………. 57 9.2. Verilog HDL Prototype………………………………………………………………………… 58 9.3. Ta'utinoga Vaega VHDL………………………………………………………………………….. 58 9.4. Taulaga……………………………………………………………………………………………… 59 9.5. Parata ……………………………………………………………………………………… 59
10. ALTMULT_ACCUM (Faatele-Faaputu) IP Core…………………………………………………… 61
10.1. Vaega ………………………………………………………………………………………………… 62 10.2. Verilog HDL Prototype…………………………………………………………………………………….62 10.3. Ta'utinoga Vaega VHDL……………………………………………………………… 63 10.4. VHDL LIBRARY_USE Tautinoga …………………………………………………………………63 10.5. Taulaga………………………………………………………………………………………………. 63 10.6. Parameter ………………………………………………………………………………………. 64
11. ALTMULT_ADD (Faatele-Faaopoopo) IP Autu………………………………………………………………..69
11.1. Vaega ………………………………………………………………………………………………… 71 11.2. Verilog HDL Prototype…………………………………………………………………………..72 11.3. Ta'utinoga Vaega VHDL………………………………………………………………………… 72 11.4. VHDL LIBRARY_USE Tautinoga …………………………………………………………………72

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11.5. Taulaga………………………………………………………………………………………………. 72 11.6. Parameter ………………………………………………………………………………………. 73
12. ALTMULT_COMPLEX (Fa'atele Fa'atele) IP Autu…………………………………………………… 86 12.1. Fa'atelega Lavelave…………………………………………………………………………. 86 12.2. Fa'atusa Fa'akanoni ………………………………………………………………… 87 12.3. Fa'atusa Fa'aleaganu'u …………………………………………………………………. 87 12.4. Vaega ……………………………………………………………………………………… 88 12.5. Verilog HDL Prototype…………………………………………………………………………..88 12.6. Ta'utinoga Vaega VHDL……………………………………………………………… 89 12.7. VHDL LIBRARY_USE Tautinoga …………………………………………………………………89 12.8. Faailoga………………………………………………………………………………………………. 89 12.9. Parameter ………………………………………………………………………………………. 90
13. ALTSQRT (Integer Square Root) IP Autu………………………………………………………………92 13.1. Vaega ……………………………………………………………………………………… 92 13.2. Verilog HDL Prototype…………………………………………………………………………..92 13.3. Ta'utinoga Vaega VHDL……………………………………………………………… 93 13.4. VHDL LIBRARY_USE Tautinoga …………………………………………………………………93 13.5. Taulaga………………………………………………………………………………………………. 93 13.6. Parameter ………………………………………………………………………………………. 94
14. PARALLEL_ADD (Fa'aopoopo Fa'atasi) IP Core……………………………………………………………….. 95 14.1. Vaega ……………………………………………………………………………………….95 14.2. Verilog HDL Prototype…………………………………………………………………………..95 14.3. Ta'utinoga Vaega VHDL………………………………………………………………………… 96 14.4. VHDL LIBRARY_USE Tautinoga …………………………………………………………………96 14.5. Taulaga………………………………………………………………………………………………. 96 14.6. Parameter ………………………………………………………………………………………. 97
15. Integer Arithmetic IP Cores User Guide Document Archives ………………………………… 98
16. Tala Fa'asolopito o Fa'amaumauga mo le Intel FPGA Integer Arithmetic IP Cores Taiala mo Tagata Fa'aoga…. 99

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1. Intel FPGA Integer Arithmetic IP Cores

E mafai ona e fa'aogaina le Intel® FPGA integer IP cores e fa'atino ai galuega fa'a-matematika i lau mamanu.

O nei galuega e ofoina atu le sili atu ona lelei le faʻaogaina o le faʻaogaina ma le faʻatinoina o masini nai lo le faʻavasegaina o au lava galuega. E mafai ona e faʻavasegaina le IP cores e faʻaoga ai au mamanu manaʻomia.

Intel integer arithmetic IP cores ua vaevaeina i vaega nei e lua: · Faletusi o modules parameterized (LPM) IP cores · Intel-specific (ALT) IP cores

Ole laulau o lo'o i lalo o lo'o lisiina ai fa'asologa ole numera IP cores.

Laulau 1.

Lisi o IP Cores

IP Cores

LPM IP cores

LPM_COUNTER

LPM_DIVIDE

LPM_MULT

LPM_ADD_SUB
LPM_COMPARE
Intel-specific (ALT) IP core ALTECC

Galueview Counter Divider Multiplier
Fa'aopoopo po'o to'ese le Fa'atusa
ECC Encoder/Decoder

Masini Lagolago
Arria® II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone® IV E, Afa IV GX, Afa V, Intel Afa 10 LP,
Intel Cyclone 10 GX, MAX® II, MAX V, MAX 10, Stratix® IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Afa IV E, Afa IV GX,
Afa V, Intel Afa 10 LP, Intel Afa 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Afa IV E, Afa IV GX,
Afa V, Intel Afa 10 LP, Intel Afa 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Afa IV E, Afa IV GX, Afa V, Intel Afa 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Afa IV E, Afa IV GX, Afa V, Intel Afa 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Afa IV E, Afa IV GX,
Afa V, Intel Afa 10 LP, Intel Afa 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V faaauau...

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

ISO 9001:2015 Resitala

1. Intel FPGA Integer Arithmetic IP Cores 683490 | 2020.10.05

IP Cores Intel FPGA Multiply Adder po'o ALTERA_MULT_ADD ALTMEMMULT
ALTMULT_ACCUM ALTMULT_ADD ALTMULT_COMPLEX
ALTSQRT
PARALLEL_ADD

Galueview Fa'atele-Adder
Fa'atele Fa'atele Tuma'u Fa'atatau ile manatua
Fa'atele-Accumulator Fa'atele-Adder
Fa'atele Lavelave
Integer Square-Root
Fa'aopoopo Fa'atasi

Masini Lagolago
Arria V, Stratix V, Afa V, Intel Stratix 10, Intel Arria 10, Intel Afa
10 GX
Arria II GX, Arria II GZ, Arria V, Intel Arria 10 (Intel Quartus® Prime Standard Edition), Afa IV E, Afa IV GX, Afa V, Intel
Afa 10 LP, MAX II, MAX V, MAX 10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Afa IV E, Afa IV GX, Intel Afa 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Afa IV E, Afa IV GX, Intel Afa 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Intel Arria 10, Arria V, Arria V GZ, Afa IV E, Afa IV GX, Afa V, Intel
Afa 10 GX, Intel Afa 10 LP, MAX 10, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Afa IV E, Afa IV GX,
Afa V, Intel Afa 10 LP, Intel Afa 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Afa IV E, Afa IV GX,
Afa V, Intel Afa 10 LP, Intel Afa 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V

Fa'amatalaga Fa'atatau
· Intel FPGAs ma Polokalama Masini Fa'asa'oloto Fa'amatalaga
· Folasaga i Intel FPGA IP Cores Tuuina atu nisi fa'amatalaga e uiga i Intel FPGA IP Cores.
· Fa'a'a'e-Point IP Cores Taiala Fa'aaogā Fa'amatalaga e uiga i Intel FPGA Floating-Point IP cores.
· Folasaga i Intel FPGA IP Cores Tuuina atu faʻamatalaga lautele e uiga i Intel FPGA IP cores, e aofia ai le faʻavasegaina, gaosia, faʻaleleia, ma le faʻataʻitaʻiina o pusa IP.
· Fausia Version-Tutoatasi IP ma Qsys Simulation Scripts Fausia tusitusiga faʻataʻitaʻiga e le manaʻomia ni faʻafouga tusi lesona mo polokalama poʻo le faʻaleleia o le IP.
· Puleaina o Poloketi Fa'ata'ita'iga sili ona lelei mo le fa'afoega lelei ma le feavea'iina o lau poloketi ma le IP files.
· Integer Arithmetic IP Cores User Guide Document Archives i le itulau 98 Tuuina atu se lisi o taiala faʻaoga mo lomiga muamua o le Integer Arithmetic IP cores.

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2. LPM_COUNTER (Counter) IP Core

Ata 1.

O le LPM_COUNTER IP core ose fa'amau fa'atau e fau i luga fa'atau, fa'amau i lalo ma fa'amau i luga po'o lalo fa'atasi ma fa'atinoga e o'o atu i le 256 bits lautele.

O le ata o lo'o i lalo o lo'o fa'aalia ai ports mo le LPM_COUNTER IP core.

LPM_COUNTER Taulaga

LPM_COUNTER

ssclr sload sset data[]

q[]

i luga i lalo

cout

aclr aload aseta

clk_en cnt_en cin
inst

2.1. Vaega
O le LPM_COUNTER IP autu o lo'o ofoina atu vaega nei: · Fa'atupu fa'atau i luga, lalo, ma luga/lalo · Fa'atupu ituaiga fa'atau nei:
— Binary Plain– o le fa'atupu fa'aopoopo e amata mai le zero po'o fa'aitiitiga e amata mai i le 255
- Modulus-o le faʻatusatusaga faʻaopoopo i poʻo faʻaititia mai le tau modulus faʻamaonia e le tagata faʻaoga ma toe fai
· Lagolago i le filifiliga fa'amaopoopo manino, uta, ma seti uafu fa'aoga · Lagolago le filifiliga asynchronous manino, uta, ma seti uafu fa'aoga · Lagolago le fa'atonuina o le faitau ma fa'aagavaa le uati i totonu o ports · Lagolago avanoa e ave i totonu ma fa'atau i fafo

ISO 9001:2015 Resitala

2. LPM_COUNTER (Counter) IP Core
683490 | 2020.10.05
2.2. Verilog HDL Prototype
Ole Verilog HDL prototype o lo'o iai ile Verilog Design File (.v) lpm.v i le edasynthesis directory.
module lpm_counter (q, data, uati, cin, cout, clk_en, cnt_en, updown, aseta, aclr, aload, sset, sclr, sload, eq ); parameter lpm_type = “lpm_counter”; parameter lpm_width = 1; parameter lpm_modulus = 0; parameter lpm_direction = “LE UA FAI”; parameter lpm_value = “LE UA FAI”; parameter lpm_svalue = “LE UA FAI”; parameter lpm_pvalue = “LE UA FAI”; parameter lpm_port_updown = “PORT_CONNECTIVITY”; parakalafa lpm_hint = “LE FA’USIA”; galuega faatino [lpm_width-1:0] q; galuega faatino; galuega faatino [15:0] tutusa; cin in; fa'aoga [lpm_width-1:0] fa'amatalaga; uati ulufale, clk_en, cnt_en, luga i lalo; fa'aoga aseta, aclr, uta; fa'aoga sset, sclr, sload; endmodule
2.3. VHDL Fa'aaliga Vaega
O le ta'utinoga vaega VHDL o lo'o maua ile VHDL Design File (.vhd) LPM_PACK.vhd i le faletusivhdllpm directory.
vaega LPM_COUNTER generic ( LPM_WIDTH : natura; LPM_MODULUS : natura := 0; LPM_DIRECTION : manoa := “LE’I FA’USIA”; LPM_AVALUE : manoa := “LE FA’USIA”; LPM_SVALUE : manoa := “LE’I FA’USIA”; LPM_PORT_UPDOWN : manoa := “PORT_CONNED ; LPM_PVALUE : manoa := “LE FA’USIA”; uafu (FA'amatalaga: i std_logic_vector(LPM_WIDTH-1 i lalo i le 0):= (ISI =>
'0'); Uati : i std_logic ; CLK_EN : i std_logic := '1'; CNT_EN : i std_logic := '1'; UPDOWN : i std_logic : = '1'; SLOAD : i std_logic := '0'; SSET : i std_logic := '0'; SCLR : i std_logic : = '0'; ALOAD : i std_logic := '0'; ASET : i std_logic := '0'; ACLR : i std_logic : = '0'; CIN : i std_logic : = '1'; COUT : out std_logic := '0'; Q : i fafo std_logic_vector(LPM_WIDTH-1 i lalo i le 0); EQ : i fafo std_logic_vector(15 i lalo i le 0));
vaega pito;

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2.4. VHDL LIBRARY_USE Tautinoga
Ole VHDL LIBRARY-USE ta'utinoga e le mana'omia pe a e fa'aogaina le VHDL Component Declaration.
LOLOTOGA lpm; FAAAOGA lpm.lpm_components.all;

2.5. Taulaga

O siata o lo'o i lalo o lo'o lisiina ai ports o lo'o i totonu ma fa'aulufale mo le LPM_COUNTER IP autu.

Laulau 2.

LPM_COUNTER Taulaga Ulufale

Igoa o le Taulaga

Manaomia

Fa'amatalaga

fa'amatalaga[]

Leai

Fa'asoa fa'amatalaga fa'atasi i le fata. Ole tele ole uafu fa'aoga e fa'alagolago ile LPM_WIDTH tau fa'ailoga.

uati

Ioe

Tulaga lelei-fa'aoso uati fa'aoga.

clk_en

Leai

O le uati e mafai ai ona fa'aoga mea e fa'agaoioi ai gaioiga uma. Afai e ave'esea, o le tau fa'aletonu ole 1.

cnt_en

Leai

Faitau e mafai ona fa'aoga e fa'amalo le faitau pe a fa'amaualalo e aunoa ma le afaina o le sload, sset, po'o le sclr. Afai e ave'esea, o le tau fa'aletonu ole 1.

i luga i lalo

Leai

Puleaina le itu o le faitau. A fa'ailoa maualuga (1), o lo'o i luga le fa'atonuga o le faitau, ae a fa'amaualalo (0), o lo'o i lalo le itu o le faitau. Afai e fa'aogaina le LPM_DIRECTION parameter, e le mafai ona feso'ota'i le pito i luga. Afai e le'o fa'aogaina le LPM_DIRECTION, o le uafu i luga e filifili. Afai e ave'esea, o le tau fa'aletonu e maualuga (1).

cin

Leai

Ave-i totonu i le vaega maualalo. Mo fata i luga, o le amio a le cin input o le

e tutusa ma le amio a le cnt_en input. Afai e ave'esea, o le tau fa'aletonu ole 1

(VCC).

aclr

Leai

Fa'aoga manino asynchronous. Afai e fa'aoga uma le aseta ma le aclr ma fa'amaonia, e fa'asili e le aclr le aseta. Afai e ave'esea, o le tau fa'aletonu o le 0 (fa'aletonu).

aseta

Leai

Fa'aoga seti le sa'o. Fa'ama'oti le q[] galuega fa'atino e pei o 1s uma, po'o le tau o lo'o fa'ailoa mai e le fa'ailoga LPM_AVALUE. Afai e fa'aoga uma le aseta ma le aclr ports ma fa'amaonia, o le tau o le aclr ports e fa'asili le tau o le aseta uafu. Afai e ave'esea, o le tau fa'aletonu o le 0, fa'aletonu.

uta

Leai

Asynchronous load input that asynchronous load the counter with the value on the data input. A fa'aoga le uafu aload, e tatau ona feso'ota'i le data[] port. Afai e ave'esea, o le tau fa'aletonu o le 0, fa'aletonu.

sclr

Leai

Fa'aoga manino fa'atasi e fa'amama le fata i le isi pito o le uati o lo'o galue. Afai o le sset ma le sclr ports o loʻo faʻaogaina ma faʻamaonia, o le tau o le sclr port e sili atu le tau o le sset port. Afai e ave'esea, o le tau fa'aletonu o le 0, fa'aletonu.

sset

Leai

Fa'aoga seti fa'atasi e tu'u ai le fata i le isi pito o le uati o lo'o galue. Fa'ama'oti le tau o galuega q e pei o 1s uma, po'o le tau o lo'o fa'ailoa mai e le LPM_SVALUE parameter. Afai o le sset ma le sclr ports e faʻaaogaina ma faʻamaonia,
o le tau o le sclr port e faʻafefe ai le tau o le sset port. Afai e ave'esea, o le tau fa'aletonu o le 0 (fa'aletonu).

uta

Leai

Fa'aoga uta fa'atasi e utaina ai le fata ma fa'amaumauga[] i le isi pito o le uati galue. A fa'aoga le uafu sload, e tatau ona feso'ota'i le data[] port. Afai e ave'esea, o le tau fa'aletonu o le 0 (fa'aletonu).

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Laulau 3.

LPM_COUNTER Taulaga Fa'atino

Igoa o le Taulaga

Manaomia

Fa'amatalaga

q[]

Leai

Fa'amatalaga maua mai le fata. Ole tele ole uafu fa'aola e fa'alagolago ile

LPM_WIDTH tau fa'ailoga. Po'o le q[] po'o le tasi o le eq[15..0] ports

e tatau ona fesootai.

eq[15..0]

Leai

Counter decode galuega faatino. O le eq[15..0] uafu e le mafai ona maua i le fa'atonu fa'ata'ita'i ona e na'o le AHDL e lagolagoina e le parakalafa.
Po'o le q[] uafu po'o le eq[] uafu e tatau ona feso'ota'i. E o'o atu i ports c eq e mafai ona fa'aoga (0 <= c <= 15). E na'o le 16 tau maualalo pito i lalo e fa'aliliu. A o'o le tau aofa'i o le c, o le fa'atusa e fa'apea e maualuga (1). Mo example, pe a 0 le faitau, eq0 = 1, pe a 1 le faitau, eq1 = 1, ma a o le faitau e 15, eq 15 = 1. Decoded galuega faatino mo le tau aofaʻi o le 16 pe sili atu e manaʻomia le decoding fafo. O le eq [15..0] gaioiga e le tutusa ma le q [] galuega.

cout

Leai

Lave-out port of the counter's MSB bit. E mafai ona fa'aoga e fa'afeso'ota'i i se isi fata e fai ai se fata tele.

2.6. Parakalafa

Ole laulau o lo'o i lalo o lo'o lisiina ai fa'amaufa'ailoga mo le LPM_COUNTER IP core.

Laulau 4.

LPM_COUNTER Parata

Igoa Parameter

Ituaiga

LPM_WIDTH

Integer

LPM_DIRECTION

manoa

LPM_MODULUS LPM_AVALUE

Integer
Integer/ String

LPM_SVALUE LPM_HINT

Integer/ String
manoa

LPM_TYPE

manoa

Manaomia Ioe Leai Leai
Leai Leai
Leai

Fa'amatalaga
Fa'ailoa mai le lautele o fa'amaumauga [] ma q[] ports, pe a fa'aaogaina.
O fa'atauga e LU, LALO, ma LE LE FA'aogaina. Afai e fa'aogaina le LPM_DIRECTION parameter, e le mafai ona feso'ota'i le pito i luga. A le feso'ota'i le uafu i luga, o le LPM_DIRECTION fa'amaufa'ailoga le aoga o le UP.
Ole numera maualuga, fa'atasi ma le tasi. Numera o setete tulaga ese i le taamilosaga a le fata. Afai e sili atu le tau o le uta nai lo le LPM_MODULUS parameter, e le o faʻamaonia le amio a le fata.
Taua faifai pea e utaina pe a fa'ailoa maualuga le aseta. Afai o le tau o loʻo faʻamaonia e sili atu pe tutusa ma , o le amio a le fata o se tulaga le fa'amalamalamaina (X), lea o le LPM_MODULUS, pe a iai, po'o le 2 ^ LPM_WIDTH. Ua fautuaina e Intel e te fa'amaoti lenei tau o se numera tesimale mo mamanu AHDL.
Tau faifaipea o loʻo faʻapipiʻiina i luga o le pito i luga o le uati uati pe a faʻamaonia le maualuga o le sset port. Ua fautuaina e Intel e te fa'amaoti lenei tau o se numera tesimale mo mamanu AHDL.
Pe a e fa'atonuina se faletusi o fa'asologa fa'atulagaina (LPM) galuega i se VHDL Design File (.vhd), e tatau ona e faʻaogaina le LPM_HINT parakalafa e faʻamaonia ai se Intel-faʻapitoa parakalafa. Mo example: LPM_HINT = “FAUFAI_FAIALA = 8, ONE_INPUT_IS_CONSTANT = IOE”
Ole tau fa'aletonu ole UNUSED.
Fa'ailoa le faletusi o le fa'avasegaina o modules (LPM) igoa fa'alapotopotoga ile VHDL design files.
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Intel FPGA Integer Arithmetic IP Cores User Guide 10

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Igoa Parameter INTENDED_DEVICE_FAMILY CARRY_CNT_EN
LAWIDE_SCLR
LPM_PORT_UPDOWN

Fa'aigoa manoa
manoa
manoa

Manaomia Leai Nu
Leai
Leai

Fa'amatalaga
O lenei fa'ata'ita'iga e fa'aaogaina mo fa'ata'ita'iga ma fa'amoemoega fa'ata'ita'iga. O lenei fa'ata'ita'iga e fa'aaogaina mo fa'ata'ita'iga ma fa'amoemoega fa'ata'ita'iga. E fa'atatau e le fa'atonu fa'ailoga le tau mo lea fa'ailoga.
Intel-fa'apitoa parakalafa. E tatau ona e fa'aogaina le LPM_HINT parakalafa e fa'amaoti ai le CARRY_CNT_EN parakalafa ile VHDL design files. O tau e SMART, ON, OFF, ma le UNUSED. Fa'aagaaga le galuega LPM_COUNTER e fa'asalalau ai le faailo cnt_en e ala i le filifili ave. I nisi tulaga, o le seti CARRY_CNT_EN e ono iai sina aafiaga i le saoasaoa, atonu e te mana'o e tape. Ole tau fa'aletonu ole SMART, lea e maua ai le fefa'ataua'iga sili i le va o le tele ma le saoasaoa.
Intel-fa'apitoa parakalafa. E tatau ona e fa'aogaina le LPM_HINT parakalafa e fa'amaoti ai le LAWIDE_SCLR parakalafa ile VHDL design files. O fa'atauga o lo'o ON, OFF, po'o le LE'A'OA'OGA. Ole tau fa'aletonu ole ON. Fa'ataga oe e fa'agata le fa'aogaina o le LABwide sclr feature o lo'o maua i aiga masini ua le toe aoga. O le tapeina o lenei filifiliga e fa'atuputeleina ai le avanoa e fa'aoga atoatoa ai le LAB ua fa'atumuina, ma fa'apea e fa'ataga ai le maualuga o le fa'atatau pe a le fa'aoga le SCLR i se LAB atoa. O lo'o avanoa lenei ta'otoga mo feso'ota'iga i tua, ma ua fautuaina oe e Intel e aua le fa'aogaina lenei parakalafa.
Fa'ailoa mai le fa'aogaina o le uafu fa'aoga i luga. Afai e ave'esea le tau fa'aletonu ole PORT_CONNECTIVITY. Pe a seti le tau o le taulaga i le PORT_USED, o le taulaga e faʻaogaina e pei ona faʻaaogaina. Pe a seti le tau o le taulaga i le PORT_UNUSED, o le taulaga e faʻaogaina e le faʻaaogaina. Pe a seti le tau o le taulaga i le PORT_CONNECTIVITY, o le faʻaogaina o le uafu e fuafua e ala i le siakiina o le fesoʻotaʻiga uafu.

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3. LPM_DIVIDE (Vaevaeina) Intel FPGA IP Core

Ata 2.

O le LPM_DIVIDE Intel FPGA IP core e fa'atino se vaeluaga e vaevae ai se tau fa'aoga numera i se tau fa'aoga fa'aui e maua ai se quotient ma se toega.

O le ata o lo'o i lalo o lo'o fa'aalia ai ports mo le LPM_DIVIDE IP core.

LPM_DIVIDE Taulaga

LPM_DIVIDE

numera[] denom[] uati

quotient [] tumau[]

clken aclr

inst

3.1. Vaega
O le LPM_DIVIDE IP core o lo'o ofoina atu vaega nei: · Fa'atupuina se vaeluaga e vaevae ai le tau fa'aoga numera i se fa'aulu fa'atatau.
tau e maua ai se quotient ma se toega. · Lagolagoina le lautele o faʻamatalaga o 1 bits. · Lagolagoina le fa'atusaina o fa'amaumauga ua sainia ma le saini mo le numera
ma fa'atatau fa'atatau. · Lagolagoina le vaega poʻo le saoasaoa faʻaleleia. · Tuuina atu se filifiliga e faʻamaonia ai se mea e totoe lelei. · Lagolago pipelining configurable output latency. · Lagolago avanoa asynchronous manino ma uati mafai ports.

3.2. Verilog HDL Prototype
Ole Verilog HDL prototype o lo'o iai ile Verilog Design File (.v) lpm.v i le edasynthesis directory.
module lpm_divide ( quotient, tumau, numera, denom, uati, clken, aclr); parameter lpm_type = “lpm_divide”; parameter lpm_widthn = 1; parameter lpm_widthd = 1; parameter lpm_nrepresentation = “LE SAIAINA”; parameter lpm_drepresentation = “LE SAIAINA”; parameter lpm_remainderpositive = “MONI”; parameter lpm_paipa = 0;

ISO 9001:2015 Resitala

3. LPM_DIVIDE (Vaevaeina) Intel FPGA IP Core 683490 | 2020.10.05

parameter lpm_hint = “LE UA FAI”; uati ulufale; clken i totonu; fa'aoga aclr; fa'aofi [lpm_widthn-1:0] numera; fa'aofi [lpm_widthd-1:0] denom; fua [lpm_widthn-1:0] quotient; galuega [lpm_widthd-1:0] tumau; endmodule

3.3. VHDL Fa'aaliga Vaega
O le ta'utinoga vaega VHDL o lo'o maua ile VHDL Design File (.vhd) LPM_PACK.vhd i le faletusivhdllpm directory.
vaega LPM_DIVIDE generic (LPM_WIDTHN : natura; LPM_WIDTHD : natura;
LPM_NREPRESENTATION : manoa := “LE SAIAINA”; LPM_DREPRESENTATION : manoa := “LE SAIAINA”; LPM_PIPELINE : natura := 0; LPM_TYPE : manoa := L_DIVIDE; LPM_HINT : manoa := “LE FA’USIA”); taulaga (NUMER: i le std_logic_vector(LPM_WIDTHN-1 i lalo i le 0); DENOM: i le std_logic_vector(LPM_WIDTHD-1 lalo i le 0); ACLR: i le std_logic: = '0'; CLOCK: i le std_logic: = '0'; CLKEN: i le std_logic : = '1'; QUOTIENT : fafo std_logic_vector(LPM_WIDTHN-1 i lalo 0)); vaega pito;

3.4. VHDL LIBRARY_USE Tautinoga
Ole VHDL LIBRARY-USE ta'utinoga e le mana'omia pe a e fa'aogaina le VHDL Component Declaration.
LOLOTOGA lpm; FAAAOGA lpm.lpm_components.all;

3.5. Taulaga

O siata o lo'o i lalo o lo'o lisiina ai ports o lo'o i totonu ma fa'aulufale mo le LPM_DIVIDE IP core.

Laulau 5.

LPM_DIVIDE Taulaga Ulufale

Igoa o le Taulaga

Manaomia

numera[]

Ioe

lotu []

Ioe

Fa'amatalaga
Ulufale fa'amatalaga numera. Ole tele ole uafu fa'aoga e fa'alagolago ile LPM_WIDTHN tau fa'ailoga.
Fa'asoa fa'amatalaga fa'atatau. Ole tele ole uafu fa'aoga e fa'alagolago ile LPM_WIDTHD tau fa'ailoga.
faaauau…

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Uati Igoa Taulaga clken
aclr

Manaomia Leai Nu
Leai

Fa'amatalaga
Fa'aoga uati mo le fa'aogaina o paipa. Mo LPM_PIPELINE tau e ese mai i le 0 (fa'aletonu), e tatau ona fa'agaoioi le uati.
Uati mafai ona fa'aoga paipa. A fa'apea e maualuga le uafu o le clken, e fai le fa'agaioiga vaevaega. A maualalo le faailo, e leai se gaioiga e tupu. Afai e ave'esea, o le tau fa'aletonu ole 1.
Asynchronous uafu manino fa'aoga i so'o se taimi e toe fa'afo'i ai le paipa i '0 uma i le fa'aogaina o le uati.

Laulau 6.

LPM_DIVIDE Taulaga Fa'atino

Igoa o le Taulaga

Manaomia

Fa'amatalaga

quotient []

Ioe

Fa'amatalaga fa'amatalaga. Ole tele ole uafu e fa'atatau ile LPM_WIDTHN

tau fa'ailoga.

tumau []

Ioe

Fa'amatalaga fa'amatalaga. Ole tele ole uafu fa'aola e fa'alagolago ile LPM_WIDTHD

tau fa'ailoga.

3.6. Parakalafa

O le laulau o loʻo i lalo o loʻo lisiina ai faʻamaufaʻailoga mo le LPM_DIVIDE Intel FPGA IP core.

Igoa Parameter

Ituaiga

Manaomia

Fa'amatalaga

LPM_WIDTHN

Integer

Ioe

Fa'ailoa mai le lautele o le numera[] ma

quotient[] ports. O tau e 1 i le 64.

LPM_WIDTHD

Integer

Ioe

Fa'ailoa mai le lautele o le denom[] ma

tumau [] taulaga. O tau e 1 i le 64.

LPM_NREPRESENTATION LPM_DREPRESENTATION

manoa manoa

Leai

Saini fa'atusa o le fa'ailoga numera.

O tau e saini ma le le saini. A o lenei

ua setiina le parakalafa i SAINI, le vaeluaga

fa'amatala le numera [] fa'aoga e pei o le lua saini

fa'atasi.

Leai

Saini fa'atusa o le fa'auiga fa'atatau.

O tau e saini ma le le saini. A o lenei

ua setiina le parakalafa i SAINI, le vaeluaga

fa'amatala le igoa [] fa'aulu e pei ona saini lua

fa'atasi.

LPM_TYPE

manoa

Leai

Fa'ailoaina le faletusi o fa'avasegaina

modules (LPM) igoa fa'alapotopotoga ile VHDL mamanu

files (.vhd).

LPM_HINT

manoa

Leai

A e fa'afuafuaina se faletusi o

fa'atonuina modules (LPM) galuega i se

VHDL Design File (.vhd), e tatau ona e faʻaogaina le

LPM_HINT parakalafa e fa'amaoti ai se Intel-

fa'ailoga fa'apitoa. Mo example: LPM_HINT

= “FILIU_SIZE = 8,

ONE_INPUT_IS_CONSTANT = IOE” O le

o le tau fa'aletonu e LE'I FA'USIA.

LPM_REMAINDERPOSITIVE

manoa

Leai

Intel-fa'apitoa parakalafa. E tatau ona e faʻaaogaina le

LPM_HINT parakalafa e faʻamaonia ai le

LPM_REMAINDERPOSITIVE parakalafa i

VHDL mamanu files. Tulaga e MONI pe SE.

Afai e setiina lenei parakalafa i le TRUE, o le

e tatau ona sili atu le tau o le toega [] uafu

faaauau…

Intel FPGA Integer Arithmetic IP Cores User Guide 14

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3. LPM_DIVIDE (Vaevaeina) Intel FPGA IP Core 683490 | 2020.10.05

Igoa Parameter

Ituaiga

MAXIMIZE_SPEED

Integer

LPM_PIPELINE

Integer

INTENDED_DEVICE_FAMILY SKIP_BITS

Manu'a Nu'u

Manaomia Nu
Leai Leai Leai

Fa'amatalaga
nai lo pe tutusa ma le leai. Afai e setiina lenei parakalafa i le TRUE, o le tau o le tumau[] uafu o le zero, pe o le tau o le faailoga tutusa, pe lelei pe leaga, e pei o le tau o le tau numera. Ina ia faʻaitiitia le eria ma faʻaleleia le saoasaoa, e fautuaina e Intel le setiina o lenei parakalafa i le TRUE i gaioiga e tatau ona lelei le vaega o totoe pe o le mea o totoe e le taua.
Intel-fa'apitoa parakalafa. E tatau ona e faʻaogaina le LPM_HINT parakalafa e faʻamaonia ai le MAXIMIZE_SPEED parakalafa i le VHDL mamanu files. O tau e [0..9]. Afai e fa'aaogaina, e taumafai le Intel Quartus Prime software e fa'amanino se fa'ata'ita'iga fa'apitoa o le galuega LPM_DIVIDE mo le saosaoa nai lo le ta'avale, ma fa'ato'a le fa'atulagaina o le filifiliga fa'atatau o le Optimization Technique. Afai e le'o fa'aaogaina MAXIMIZE_SPEED, e fa'aoga le tau o le filifiliga Fa'atonu Fa'atonu. Afai o le tau o le MAXIMIZE_SPEED e 6 pe sili atu, o le Compiler optimizes le LPM_DIVIDE IP autu mo le saoasaoa maualuga e ala i le faaaogaina o filifili tauaveina; afai o le tau e 5 pe itiiti ifo, e faʻatino e le tagata faʻapipiʻi le mamanu e aunoa ma ni filifili amo.
Fa'amaoti le aofa'i o ta'amilosaga o le uati o lo'o feso'ota'i ma le quotient[] ma tumau[] galuega faatino. Ole tau ole zero (0) e ta'u mai ai e leai se fa'aletonu o lo'o iai, ma o se galuega tu'ufa'atasia e fa'atupu vave. Afai e ave'esea, o le tau fa'aletonu o le 0 (le paipa). E le mafai ona e fa'ailoaina se tau mo le fa'ailoga LPM_PIPELINE e maualuga atu i le LPM_WIDTHN.
O lenei fa'ata'ita'iga e fa'aaogaina mo fa'ata'ita'iga ma fa'amoemoega fa'ata'ita'iga. E fa'atatau e le fa'atonu fa'ailoga le tau mo lea fa'ailoga.
Fa'ataga mo le vaevaega vaevaega fa'apitoa e sili atu ona lelei e fa'amanino ai le fa'atatau i pito ta'imua e ala i le tu'uina atu o le numera o le ta'ita'i GND i le LPM_DIVIDE IP autu. Fa'amaoti le numera o le GND ta'ita'ia i luga o le fa'aupuga fa'atatau i lenei ta'otoga.

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4. LPM_MULT (Fa'atele) IP Core

Ata 3.

O le LPM_MULT IP autu e fa'atinoina se fa'atele e fa'atele ai fa'amaumauga fa'amaumauga e lua e maua mai ai se oloa e fai ma galuega.

O le ata o loʻo i lalo o loʻo faʻaalia ai ports mo le LPM_MULT IP core.

LPM_Fa'atele Uafu

LPM_MULT uati dataa[] taunuuga[] datab[] aclr/sclr clken
inst

Fa'amatalaga Fa'atatau ile itulau 71

4.1. Vaega
O le LPM_MULT IP autu o loʻo ofoina atu uiga nei: · Faʻatupuina se faʻateleina e faʻateleina ai faʻamatalaga faʻamatalaga e lua · Lagolago le lautele o faʻamatalaga o le 1 bits · Lagolagoina le faʻailogaina ma le le faʻamaoniaina o faʻamatalaga faʻatusa · Lagolagoina le vaega poʻo le saoasaoa optimization · Lagolago pipelining ma configurable output latency · Tuuina atu se filifiliga mo le faʻatinoina i le faʻatulagaina o faʻailoga numera (DSP)
poloka circuitry po'o elemene logic (LEs) Fa'aaliga: A fau mea fa'atele e lapo'a atu nai lo le lapo'a e lagolagoina e le atunu'u e ono/
o le a avea ma aafiaga fa'atinoga e mafua mai i le fa'aoso o poloka DSP. · Lagolagoina le manino asynchronous ma le uati e mafai ai ona fa'aoga uafu · Lagolagoina le fa'aogaina manino mo Intel Stratix 10, Intel Arria 10 ma Intel Cyclone 10 GX masini

ISO 9001:2015 Resitala

4. LPM_MULT (Faatele) IP Core 683490 | 2020.10.05
4.2. Verilog HDL Prototype
Ole Verilog HDL prototype o lo'o iai ile Verilog Design File (.v) lpm.v i le edasynthesis directory.
module lpm_mult (i'uga, dataa, datab, sum, uati, clken, aclr ) parameter lpm_type = “lpm_mult”; parameter lpm_widtha = 1; parameter lpm_widthb = 1; parameter lpm_widths = 1; parameter lpm_widthp = 1; parameter lpm_representation = “LE SAIAINA”; parameter lpm_paipa = 0; parameter lpm_hint = “LE UA FAI”; uati ulufale; clken i totonu; fa'aoga aclr; fa'aofi [lpm_widtha-1:0] dataa; fa'aofi [lpm_widthb-1:0] datab; tuu i totonu [lpm_widths-1:0] aofaiga; fa'ai'uga [lpm_widthp-1:0]; endmodule
4.3. VHDL Fa'aaliga Vaega
O le ta'utinoga vaega VHDL o lo'o maua ile VHDL Design File (.vhd) LPM_PACK.vhd i le faletusivhdllpm directory.
vaega LPM_MULT generic ( LPM_WIDTHA : natura; LPM_WIDTHB : natura; LPM_WIDTHS : natura : = 1; LPM_WIDTHP : natura;
LPM_REPRESENTATION : manoa := “LE SAIAINA”; LPM_PIPELINE : natura := 0; LPM_TYPE: manoa := L_MULT; LPM_HINT : manoa := “LE FA’USIA”); taulaga (DATAA: i le std_logic_vector(LPM_WIDTHA-1 i lalo i le 0); DATAB: i le std_logic_vector(LPM_WIDTHB-1 i lalo i le 0); ACLR: i le std_logic: = '0'; CLOCK: i le std_logic: = '0'; CLKEN: in std_logic : = '1'; SUM : i le std_logic_vector(LPM_WIDTHS-1 i lalo i le 0) := (ISI => '0' RESULT: out std_logic_vector(LPM_WIDTHP-1 i lalo i le 0)); vaega pito;
4.4. VHDL LIBRARY_USE Tautinoga
Ole VHDL LIBRARY-USE ta'utinoga e le mana'omia pe a e fa'aogaina le VHDL Component Declaration.
LOLOTOGA lpm; FAAAOGA lpm.lpm_components.all;

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Intel FPGA Integer Arithmetic IP Cores User Guide 17

4. LPM_MULT (Faatele) IP Core 683490 | 2020.10.05

4.5. Fa'ailoga

Laulau 7.

LPM_MULT Fa'ailoga Fa'aofi

Igoa Faailoga

Manaomia

Fa'amatalaga

fa'amatalaga[]

Ioe

Tuuina atu o faamatalaga.

Mo Intel Stratix 10, Intel Arria 10, ma le Intel Cyclone 10 GX masini, o le tele o le faʻailoga faʻapipiʻi e faʻalagolago i le tau o le lautele o Dataa.

Mo masini tuai ma le Intel Cyclone 10 LP, o le tele o le fa'ailoga fa'aoga e fa'alagolago i le tau o le LPM_WIDTHA.

datab[]

Ioe

Tuuina atu o faamatalaga.

Mo le Intel Stratix 10, Intel Arria 10, ma le Intel Cyclone 10 GX masini, o le tele o le faʻailoga faʻapipiʻi e faʻalagolago i le tau o le lautele o le Datab.

Mo masini tuai ma Intel Cyclone 10 LP, e fa'alagolago le tele o le fa'ailo fa'aoga

i le LPM_WIDTHB tau fa'ailoga.

uati

Leai

Fa'aoga uati mo le fa'aogaina o paipa.

Mo masini tuai ma Intel Cyclone 10 LP, e tatau ona fa'agaoioi le faailo o le uati mo LPM_PIPELINE tau e ese mai le 0 (fa'aletonu).

Mo Intel Stratix 10, Intel Arria 10, ma le Intel Cyclone 10 GX masini, e tatau ona fa'agaoioi le faailo o le uati pe a fai e ese le tau Latency nai lo le 1 (fa'aletonu).

clken

Leai

E mafai ona fa'aogaina le uati mo le fa'aogaina o paipa. A maualuga le faailo clken, o le

fa'atino galuega fa'aopoopo/to'ese. A maualalo le faailo, leai se gaioiga

tupu. Afai e ave'esea, o le tau fa'aletonu ole 1.

aclr sclr

Leai

Fa'ailoga manino asynchronous fa'aaoga i so'o se taimi e toe seti ai le paipa i 0s uma,

asynchronously i le faailo o le uati. O le paipa e amata ile le fa'amalamalamaina (X)

tulaga fa'atatau. O fa'atinoga e fa'atutusa, ae le-zero tau.

Leai

Fa'ailoga manino fa'aoga fa'aoga i so'o se taimi e toe seti ai le paipa i 0s uma,

fa'atasi i le faailo o le uati. O le paipa e amata ile le fa'amalamalamaina (X)

tulaga fa'atatau. O fa'atinoga e fa'atutusa, ae le-zero tau.

Laulau 8.

LPM_MULT Fa'ailoga fa'aulu

faailo Igoa

Manaomia

Fa'amatalaga

i'uga[]

Ioe

Fa'amatalaga fa'amatalaga.

Mo masini tuai ma le Intel Cyclone 10 LP, o le tele o le fa'ailo o le gaosiga e fa'alagolago i le LPM_WIDTHP tau fa'amaufa'ailoga. Afai LPM_WIDTHP < max (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) po'o (LPM_WIDTHA + LPM_WIDTHS), na'o LPM_WIDTHP MSB o lo'o iai.

Mo le Intel Stratix 10, Intel Arria 10 ma le Intel Cyclone 10 GX, o le tele o faʻailoga e faʻatatau i le faʻamaufaʻailoga lautele.

4.6. Parameter mo Stratix V, Arria V, Afa V, ma Intel Cyclone 10 LP Devices

4.6.1. General Tab

Laulau 9.

General Tab

Parameter

Taua

Fa'aopoopo Fa'aopoopo

Fa'atele 'dataa' fa'aoga ile 'datab' fa'aoga

Tau Fa'atonu

Fa'amatalaga

Fa'atele 'dataa' fa'aoga ile 'datab' fa'aoga

Filifili le fa'atulagaga mana'omia mo le fa'atele.
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Intel FPGA Integer Arithmetic IP Cores User Guide 18

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4. LPM_MULT (Faatele) IP Core 683490 | 2020.10.05

Parameter
O le a le lautele e tatau ona iai le 'dataa'? O le a le lautele e tatau ona iai le 'datab'? E fa'apefea ona fa'amauina le lautele o le 'i'uga' galuega? Taofi le lautele

Taua
Fa'atele 'dataa' fa'aoga na'o ia (faiga fa'atafafa)
1 - 256 bits

Tau Fa'atonu

Fa'amatalaga

8 pito

Fa'ailoa le lautele o le dataa[] port.

1 - 256 bits

8 pito

Fa'ailoa le lautele o le datab[] port.

Fuafua otometi le lautele Taofi le lautele
1 - 512 bits

Otometi y fuafua le lautele

Filifili le auala e mana'omia e iloa ai le lautele o le taunu'uga[] uafu.

16 pito

Fa'ailoa le lautele o le taunu'uga[] uafu.
O lenei tau e na'o le aoga pe afai e te filifilia Fa'agata le lautele i le Ituaiga parameter.

4.6.2. Laulau 2 Tab

Laulau 10. Aoao 2 Tab

Parameter

Taua

Fa'amatalaga Fa'amatalaga

E iai pea le tau o le pasi 'datab'?

Leai Ioe

Ituaiga Faatele

O le fea ituaiga o

Le saini

fa'atele e te mana'o ai? Saini

Fa'atinoga

O le fea fa'atinoga fa'atele e tatau ona fa'aoga?

Fa'aaoga le fa'atinoga fa'aletonu
Fa'aaogā le fa'asologa fa'atele (E le'o avanoa mo aiga uma)
Fa'aoga elemene fa'atatau

Tau Fa'atonu

Fa'amatalaga

Leai

Filifili le Ioe e faʻamaonia ai le tau tumau o le

'datab' fa'aoga pasi, pe a iai.

Le saini

Fa'ama'oti le fa'atusa fa'atusa mo mea uma e lua dataa[] ma datab[].

Fa'aaoga le fa'aoga le fa'aoga ion

Filifili le auala e mana'omia e iloa ai le lautele o le taunu'uga[] uafu.

4.6.3. Pipeli Tab

Laulau 11. Pipelining Tab

Parameter

E te manaʻo e faʻapipiʻi le Nu

galue?

Ioe

Taua

Fausia se 'aclr'

—

uafu manino asynchronous

Tau Fa'atonu

Fa'amatalaga

Leai

Filifili ioe e mafai ai ona resitala paipa ile

fa'atupu fa'atele ma fa'amaoti le mana'omia

ta'amilosaga o le uati. Fa'atagaina le

resitara paipa e fa'aopoopoina le fa'agata i le

galuega faatino.

Le fa'ailogaina

Filifili le filifiliga lea ina ia mafai ai e le aclr port ona fa'aoga asynchronous clear mo le resitala o paipa.
faaauau…

Lauina Manatu

Intel FPGA Integer Arithmetic IP Cores User Guide 19

4. LPM_MULT (Faatele) IP Core 683490 | 2020.10.05

Parameter
Fausia se 'clken' uati mafai ai
Fa'atonuga
O le a le ituaiga fa'ata'ita'iga e te mana'o ai?

Taua -
Vaega Saosaoa masani

Tau Fa'atonu

Fa'amatalaga

Le fa'ailogaina

Fa'ailoa mai le uati maualuga malosi e mafai ai mo le uati o le resitara paipa

Fa'atonu

Fa'ailoa mai le fa'atonuga mana'omia mo le IP core.
Filifili le Default e fa'ataga ai le Intel Quartus Prime software e fuafua le fa'atonuga sili mo le IP core.

4.7. Parameter mo Intel Stratix 10, Intel Arria 10, ma Intel Cyclone 10 GX Devices

4.7.1. General Tab

Laulau 12. Laulau Lautele

Parameter

Taua

Tau Fa'atonu

Fa'amatalaga

Ituaiga Fa'aopoopo Fa'atele
Lautele o Taulaga Fa'amatalaga

Fa'atele 'dataa' fa'aoga ile 'datab' fa'aoga
Fa'atele 'dataa' fa'aoga na'o ia (faiga fa'atafafa)

Fa'atele 'dataa' fa'aoga ile 'datab' fa'aoga

Filifili le fa'atulagaga mana'omia mo le fa'atele.

Fa'amatalaga lautele

1 - 256 bits

8 pito

Fa'ailoa le lautele o le dataa[] port.

Fa'amatalaga lautele

1 - 256 bits

8 pito

Fa'ailoa le lautele o le datab[] port.

E fa'apefea ona fa'amauina le lautele o le 'i'uga' galuega?

Ituaiga

Fa'atatau otometi le lautele
Taofi le lautele

Otometi y fuafua le lautele

Filifili le auala e mana'omia e iloa ai le lautele o le taunu'uga[] uafu.

Taua

1 - 512 bits

16 pito

Fa'ailoa le lautele o le taunu'uga[] uafu.
O lenei tau e na'o le aoga pe afai e te filifilia Fa'agata le lautele i le Ituaiga parameter.

I'uga lautele

1 - 512 bits

—

Fa'aali le lautele lelei o le taunu'uga[] uafu.

4.7.2. Laulau 2 Tab

Laulau 13. Aoao 2 Tab

Parameter

Fa'amatalaga Fa'amatalaga

E iai pea le tau o le pasi 'datab'?

Leai Ioe

Taua

Tau Fa'atonu

Fa'amatalaga

Leai

Filifili le Ioe e faʻamaonia ai le tau tumau o le

'datab' fa'aoga pasi, pe a iai.

faaauau…

Intel FPGA Integer Arithmetic IP Cores User Guide 20

Lauina Manatu

4. LPM_MULT (Faatele) IP Core 683490 | 2020.10.05

Parameter

Taua

So'o se tau e sili atu nai lo le 0

Ituaiga Faatele

O le fea ituaiga o

Le saini

fa'atele e te mana'o ai? Saini

Sitaili Fa'atinoga

O le fea fa'atinoga fa'atele e tatau ona fa'aoga?

Fa'aaoga le fa'atinoga fa'aletonu
Fa'aaogā le fa'asologa fa'atele fa'apitoa
Fa'aoga elemene fa'atatau

Tau Fa'atonu

Fa'amatalaga

Fa'ailoa le tau tumau o le datab[] port.

Le saini

Fa'ama'oti le fa'atusa fa'atusa mo mea uma e lua dataa[] ma datab[].

Fa'aaoga le fa'aoga le fa'aoga ion

Filifili le auala e mana'omia e iloa ai le lautele o le taunu'uga[] uafu.

4.7.3. Paipa

Laulau 14. Pipelining Tab

Parameter

Taua

E te mana'o e fa'auigaina le galuega?

Paipa

Leai Ioe

Latency Clear Ituaiga Faailoga

So'o se tau e sili atu nai lo le 0.
LEAI ACLR SCLR

Fausia se uati 'clken'

—

mafai le uati

O le a le ituaiga fa'ata'ita'iga e te mana'o ai?

Ituaiga

Vaega Saosaoa masani

Tau Fa'atonu

Fa'amatalaga

Leai 1 LEAI
—

Filifili le Ioe ina ia mafai ai ona resitara paipa i le fa'ateleina o galuega. O le fa'aogaina o le resitara o paipa e fa'aopoopoina ai le fa'aletonu i le gaosiga.
Fa'ailoa le fa'aletonu o lo'o mana'omia ile ta'amilosaga o le uati.
Fa'ailoa le ituaiga toe setiina mo le resitala o paipa. Filifili le LEAI pe afai e te le fa'aogaina so'o se resitara paipa. Filifili le ACLR e fa'aoga ai le asynchronous clear mo le resitala o paipa. Ole mea lea ole a maua ai le ACLR port. Filifili le SCLR e fa'aoga le synchronous clear mo le resitala o paipa. Ole mea lea ole a maua ai le port SCLR.
Fa'ailoa mai le uati maualuga malosi e mafai ai mo le uati o le resitara paipa

Fa'atonu

Fa'ailoa mai le fa'atonuga mana'omia mo le IP core.
Filifili le Default e fa'ataga ai le Intel Quartus Prime software e fuafua ai le fa'atonuga sili mo le IP core.

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Intel FPGA Integer Arithmetic IP Cores User Guide 21

683490 | 2020.10.05 Auina Manatu

5. LPM_ADD_SUB (Fa'aopoopo/Tu'u'ese)

Ata 4.

O le LPM_ADD_SUB IP autu e mafai ai ona e fa'atinoina se fa'aopoopo po'o se to'ese e fa'aopoopo pe to'ese seti o fa'amaumauga e maua ai se galuega fa'atino o lo'o iai le aofa'iga po'o le eseesega o tau fa'aoga.

O le ata o loʻo i lalo o loʻo faʻaalia ai ports mo le LPM_ADD_SUB IP core.

LPM_ADD_SUB Taulaga

LPM_ADD_SUB add_sub cin

fa'amatalaga[]

uati clken datab[] aclr

i'uga[] taumasuasua cout

inst

5.1. Vaega
O le LPM_ADD_SUB IP autu o loʻo ofoina atu uiga nei: · Faʻatupuina faʻaopoopoga, faʻaitiitiga, ma faʻapipiʻi faʻapipiʻi / faʻaitiitiga malosi.
galuega tauave. · Lagolagoina le lautele o faʻamatalaga o le 1 bits. · Lagolagoina le fa'atusaina o fa'amaumauga e pei o le sainia ma le le sainia. · Lagolagoina e filifili ai e ave i totonu (nono i fafo), manino e le fetaui, ma ua mafai ai
taulaga fa'aoga. · Lagolagoina e filifili ai e ave i fafo (noi i totonu) ma taumasuasua uafu o galuega. · Fa'atonu se tasi o pasi fa'amatalaga fa'aoga i se fa'aauau. · Lagolagoina le paipa fa'atasi ai ma le fa'agaoioiga o galuega fa'atino.

ISO 9001:2015 Resitala

5. LPM_ADD_SUB (Fa'aopoopo/Tu'u'ese) 683490 | 2020.10.05
5.2. Verilog HDL Prototype
Ole Verilog HDL prototype o lo'o iai ile Verilog Design File (.v) lpm.v i le edasynthesis directory.
module lpm_add_sub (i'uga, cout, lofia, add_sub, cin, dataa, datab, uati, clken, aclr ); parameter lpm_type = “lpm_add_sub”; parameter lpm_width = 1; parameter lpm_direction = “LE UA FAI”; parameter lpm_representation = “SAIGINA”; parameter lpm_paipa = 0; parakalafa lpm_hint = “LE FA’USIA”; fa'aofi [lpm_width-1:0] dataa, datab; fa'aoga add_sub, cin; uati ulufale; clken i totonu; fa'aoga aclr; fa'ai'uga [lpm_width-1:0]; Output cout, taumasuasua; endmodule
5.3. VHDL Fa'aaliga Vaega
O le ta'utinoga vaega VHDL o lo'o maua ile VHDL Design File (.vhd) LPM_PACK.vhd i le faletusivhdllpm directory.
vaega LPM_ADD_SUB lautele (LPM_WIDTH : natura;
LPM_DIRECTION : manoa := “LE UA FAI”; LPM_REPRESENTATION: manoa := “SAIGINA”; LPM_PIPELINE : natura := 0; LPM_TYPE : manoa := L_ADD_SUB; LPM_HINT : manoa := “LE FA’USIA”); taulaga (DATAA: i le std_logic_vector(LPM_WIDTH-1 i lalo i le 0); DATAB: i le std_logic_vector(LPM_WIDTH-1 lalo i le 0); ACLR: i le std_logic: = '0'; CLOCK: i le std_logic: = '0'; CLKEN: i totonu std_logic : = '1'; CIN : i le std_logic : = 'Z' ; vaega pito;
5.4. VHDL LIBRARY_USE Tautinoga
Ole VHDL LIBRARY-USE ta'utinoga e le mana'omia pe a e fa'aogaina le VHDL Component Declaration.
LOLOTOGA lpm; FAAAOGA lpm.lpm_components.all;
5.5. Taulaga
O siata o lo'o i lalo o lo'o lisiina ai ports o lo'o i totonu ma fa'aulufale mo le LPM_ADD_SUB IP autu.

Lauina Manatu

Intel FPGA Integer Arithmetic IP Cores User Guide 23

5. LPM_ADD_SUB (Fa'aopoopo/Tu'u'ese) 683490 | 2020.10.05

Fuafuaga 15. LPM_ADD_SUB Taulaga Ulufale IP

Igoa o le Taulaga

Manaomia

Fa'amatalaga

cin

Leai

Ave-i totonu i le vaega maualalo. Mo galuega fa'aopoopo, o le tau fa'aletonu ole 0. Mo

fa'agaioiga toese, ole tau fa'aletonu ole 1.

fa'amatalaga[]

Ioe

Tuuina atu o faamatalaga. Ole tele ole uafu fa'aoga e fa'alagolago ile LPM_WIDTH tau fa'ailoga.

datab[]

Ioe

Tuuina atu o faamatalaga. Ole tele ole uafu fa'aoga e fa'alagolago ile LPM_WIDTH tau fa'ailoga.

add_sub

Leai

O le uafu fa'aoga e filifili ai e mafai ai ona fesuia'i malosi i le va o le fa'aopoopo ma le to'ese

galuega tauave. Afai e fa'aogaina le LPM_DIRECTION parameter, e le mafai ona fa'aogaina le add_sub. Afai

ave'esea, ole tau fa'aletonu ole ADD. Ua fautuaina e Intel e te fa'aogaina le

LPM_DIRECTION parameter e faʻamaonia ai le faʻaogaina o le galuega LPM_ADD_SUB,

nai lo le tuʻuina atu o se faʻaauau i le add_sub port.

uati

Leai

Fa'aoga mo le fa'aogaina o paipa. O le uati uafu e maua ai le fa'aoga uati mo se paipa

fa'agaioiga. Mo LPM_PIPELINE tau e ese mai i le 0 (fa'aletonu), e tatau ona i ai le uati

mafai.

clken

Leai

E mafai ona fa'aogaina le uati mo le fa'aogaina o paipa. A maualuga le uafu clken, o le adder/

fa'atino galuega to'ese. A maualalo le faailo, e leai se gaioiga e tupu. Afai

ave'esea, o le tau fa'aletonu ole 1.

aclr

Leai

Asynchronous manino mo le fa'aogaina o paipa. O le paipa e amata ile le fa'amalamalamaina (X)

tulaga fa'atatau. O le aclr port e mafai ona faʻaoga i soʻo se taimi e toe setiina ai le paipa i 0s uma,

asynchronously i le faailo o le uati.

Fuafuaga 16. LPM_ADD_SUB Taulaga Fa'aulufale Autu IP

Igoa o le Taulaga

Manaomia

Fa'amatalaga

i'uga[]

Ioe

Fa'amatalaga fa'amatalaga. Ole tele ole uafu fa'aola e fa'alagolago ile LPM_WIDTH parameter

taua.

cout

Leai

Tu'u i fafo (noi-i totonu) o le pito sili ona taua (MSB). O le uafu cout ei ai lona tino

fa'aliliuga o le fa'atinoina (noi-i totonu) ole MSB. E iloa e le uafu cout

taumasuasua i galuega UNSIGNED. O lo'o fa'agaoioi le uafu cout i le faiga lava e tasi mo

Saini ma le le saini galuega.

taumasuasua

Leai

Fa'atonuga fa'agata fa'amama fa'asolo. O lo'o i ai le fa'auigaga fa'aletino o le taulaga o lo'o i ai

le XOR o le ave i totonu i le MSB faatasi ai ma le aveina i fafo o le MSB. O le uafu ova

fa'amaonia pe a sili atu fa'ai'uga i le sa'o o lo'o maua, ma e fa'aaogaina pe a

LPM_REPRESENTATION tau fa'ailoga ua SAIAINA.

5.6. Parakalafa

O le laulau o lo'o i lalo o lo'o lisiina ai le LPM_ADD_SUB IP autu autu.

Laulau 17. LPM_ADD_SUB IP Core Parameters

Suafa Igoa LPM_WIDTH

Ituaiga Integer

Manaomia Ioe

Fa'amatalaga
Fa'amaoti le lautele o le dataa[], datab[], ma taunuuga[] ports.

LPM_DIRECTION

manoa

Leai

O tau o le ADD, SUB, ma le UNUSED. Afai e ave'esea, o le tau fa'aletonu ole DEFAULT, lea e fa'atonu ai le parakalafa e ave lona tau mai le add_sub port. E le mafai ona fa'aoga le add_sub port pe a fa'aoga LPM_DIRECTION. Ua fautuaina e Intel e te faʻaogaina le LPM_DIRECTION parameter e faʻamaonia ai le faʻaogaina o le galuega LPM_ADD_SUB, nai lo le tuʻuina atu o se faʻaauau i le add_sub port.
faaauau…

Intel FPGA Integer Arithmetic IP Cores User Guide 24

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5. LPM_ADD_SUB (Fa'aopoopo/Tu'u'ese) 683490 | 2020.10.05

Igoa Parameter LPM_REPRESENTATION LPM_PIPELINE LPM_HINT LPM_TYPE ONE_INPUT_IS_CONSTANT MAXIMIZE_SPEED
INTENDED_DEVICE_FAMILY

Fa'aigoa Fa'aigoa Integer manoa manoa fa'atasi
manoa

Manaomia Leai Leai Leai Leai Leai
Leai

Fa'amatalaga
Fa'ailoa mai le ituaiga o fa'aopoopoga na faia. O tau e saini ma le le saini. Afai e ave'esea, o le tau fa'aletonu o le SAINI. A fa'atūina le fa'ailoga i le SAINI, e fa'amatala e le fa'aopoopo/to'ese le fa'auluina o fa'amaumauga e pei o le saini e lua.
Fa'amaoti mai le aofa'i o ta'amilosaga o le uati o lo'o feso'ota'i ma le taunu'uga[] galuega. Ole tau ole zero (0) o lo'o fa'aalia ai e leai se fa'aletonu o iai, ma o le a fa'atinoina se galuega fa'atasi. Afai e ave'esea, o le tau fa'aletonu o le 0 (le paipa).
Fa'ataga oe e fa'ailoa fa'amaufa'ailoga fa'apitoa a Intel ile mamanu VHDL files (.vhd). Ole tau fa'aletonu ole UNUSED.
Fa'ailoa le faletusi o le fa'avasegaina o modules (LPM) igoa fa'alapotopotoga ile VHDL design files.
Intel-fa'apitoa parakalafa. E tatau ona e fa'aogaina le LPM_HINT parakalafa e fa'amaoti ai le ONE_INPUT_IS_CONSTANT parakalafa ile VHDL design files. O fa'atauga o le IOE, LEAI, ma LE LE FA'A'OGA. E maua ai le fa'alelei sili atu pe a fai e tasi le fa'aoga e tumau. Afai e ave'esea, ole tau fa'aletonu ole NO.
Intel-fa'apitoa parakalafa. E tatau ona e faʻaogaina le LPM_HINT parakalafa e faʻamaonia ai le MAXIMIZE_SPEED parakalafa i le VHDL mamanu files. E mafai ona e faʻamaonia se tau i le va o le 0 ma le 10. Afai e faʻaaogaina, e taumafai le Intel Quartus Prime software e faʻamalieina se faʻataʻitaʻiga faʻapitoa o le galuega LPM_ADD_SUB mo le saoasaoa nai lo le faʻaogaina, ma faʻamalo le faʻatulagaina o le filifiliga o le Optimization Technique logic. Afai e le'o fa'aaogaina MAXIMIZE_SPEED, e fa'aoga le tau o le filifiliga Fa'atonu Fa'atonu. Afai o le faʻatulagaina mo MAXIMIZE_SPEED e 6 poʻo le maualuga, o le Compiler e faʻamalosia le LPM_ADD_SUB IP autu mo le saoasaoa maualuga e faʻaaoga ai filifili ave; afai o le seti e 5 pe itiiti ifo, e faʻatino e le Compiler le mamanu e aunoa ma ni filifili amo. E tatau ona fa'amaoti lenei ta'oto mo masini Afa, Stratix, ma Stratix GX pe a le fa'aogaina le add_sub port.
O lenei fa'ata'ita'iga e fa'aaogaina mo fa'ata'ita'iga ma fa'amoemoega fa'ata'ita'iga. E fa'atatau e le fa'atonu fa'ailoga le tau mo lea fa'ailoga.

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Intel FPGA Integer Arithmetic IP Cores User Guide 25

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6. LPM_COMPARE (Fa'atusa)

Ata 5.

O le LPM_COMPARE IP autu e faʻatusatusa le tau o seti e lua o faʻamaumauga e fuafua ai le va o latou. I lona faiga sili ona faigofie, e mafai ona e fa'aogaina se faitoto'a fa'apitoa-OR e iloa ai pe tutusa fa'amaumauga e lua.

O le ata o lo'o i lalo o lo'o fa'aalia ai ports mo le LPM_COMPARE IP core.

LPM_COMPARE Taulaga

LPM_COMPARE

clken

alb

aeb

fa'amatalaga[]

agb

datab[]

tausagab

uati

aneb

aclr

aleb

inst

6.1. Vaega
O le LPM_COMPARE IP autu o loʻo ofoina atu uiga nei: · Fausia se galuega faʻatusatusa e faʻatusatusa ai seti o faʻamaumauga e lua · Lagolagoina le lautele o faʻamatalaga o le 1 bits · Lagolagoina faʻamatalaga faʻamatalaga e pei o le sainia ma le le sainia · Faia ituaiga o galuega nei:
— alb (o mea e fai A e itiiti ifo nai lo mea fa'aoga B) — aeb (ulufale A e tutusa ma mea fa'aoga B) — agb (ulufale A e sili atu nai lo mea fa'aoga B) — ageb (ulufale A e sili atu pe tutusa ma fa'aoga B) — aneb ( fa'aoga A e le tutusa ma fa'aoga B) — aleb (fa'aulu A e la'ititi pe tutusa ma fa'aoga B) · Lagolagoina le fa'aogaina manino ma le uati e mafai ai ona fa'aoga ports · Fa'asoa le datab [] fa'aoga i se taimi tumau · Lagolago le paipa fa'atasi ma le fa'aogaina o mea e mafai ona fai.

ISO 9001:2015 Resitala

6. LPM_COMPARE (Fa'atusatusa) 683490 | 2020.10.05
6.2. Verilog HDL Prototype
Ole Verilog HDL prototype o lo'o iai ile Verilog Design File (.v) lpm.v i le edasynthesis directory.
module lpm_compare ( alb, aeb, agb, aleb, aneb, ageb, dataa, datab, uati, clken, aclr ); parameter lpm_type = “lpm_faatusatusa”; parameter lpm_width = 1; parameter lpm_representation = “LE SAIAINA”; parameter lpm_paipa = 0; parakalafa lpm_hint = “LE FA’USIA”; fa'aofi [lpm_width-1:0] dataa, datab; uati ulufale; clken i totonu; fa'aoga aclr; galuega faatino alb, aeb, agb, aleb, aneb, ageb; endmodule
6.3. VHDL Fa'aaliga Vaega
O le ta'utinoga vaega VHDL o lo'o maua ile VHDL Design File (.vhd) LPM_PACK.vhd i le faletusivhdllpm directory.
vaega LPM_COMPARE lautele (LPM_WIDTH : natura;
LPM_REPRESENTATION : manoa := “LE SAIAINA”; LPM_PIPELINE : natura := 0; LPM_TYPE: manoa := L_COMPARE; LPM_HINT : manoa := “LE FA’USIA”); taulaga (DATAA: i le std_logic_vector(LPM_WIDTH-1 i lalo i le 0); DATAB: i le std_logic_vector(LPM_WIDTH-1 lalo i le 0); ACLR: i le std_logic: = '0'; CLOCK: i le std_logic: = '0'; CLKEN: i totonu std_logic : = '1' ; vaega pito;
6.4. VHDL LIBRARY_USE Tautinoga
Ole VHDL LIBRARY-USE ta'utinoga e le mana'omia pe a e fa'aogaina le VHDL Component Declaration.
LOLOTOGA lpm; FAAAOGA lpm.lpm_components.all;
6.5. Taulaga
O siata o lo'o i lalo o lo'o lisiina ai ports o lo'o i totonu ma fa'aulufale mo le LMP_COMPARE IP autu.

Lauina Manatu

Intel FPGA Integer Arithmetic IP Cores User Guide 27

6. LPM_COMPARE (Fa'atusatusa) 683490 | 2020.10.05

Fuafuaga 18. LPM_COMPARE IP matua'i Taulaga Ulufale

Igoa o le Taulaga

Manaomia

Fa'amatalaga

fa'amatalaga[]

Ioe

Tuuina atu o faamatalaga. Ole tele ole uafu fa'aoga e fa'alagolago ile LPM_WIDTH tau fa'ailoga.

datab[]

Ioe

Tuuina atu o faamatalaga. Ole tele ole uafu fa'aoga e fa'alagolago ile LPM_WIDTH tau fa'ailoga.

uati

Leai

Fa'aoga uati mo le fa'aogaina o paipa. O le uati uafu e maua ai le fa'aoga uati mo se paipa

fa'agaioiga. Mo LPM_PIPELINE tau e ese mai i le 0 (fa'aletonu), e tatau ona i ai le uati

mafai.

clken

Leai

E mafai ona fa'aogaina le uati mo le fa'aogaina o paipa. A fa'amaualuga le uafu clken, o le

fa'atusatusaga fa'atinoga e faia. A maualalo le faailo, e leai se gaioiga e tupu. Afai

ave'esea, o le tau fa'aletonu ole 1.

aclr

Leai

Asynchronous manino mo le fa'aogaina o paipa. O le paipa e amata i se manatu e le'i fa'amalamalamaina (X).

tulaga. O le aclr port e mafai ona faʻaoga i soʻo se taimi e toe setiina ai le paipa i 0s uma,

asynchronously i le faailo o le uati.

Fuafuaga 19. LPM_COMPARE IP autu o Taulaga Fa'aulufale

Igoa o le Taulaga

Manaomia

Fa'amatalaga

alb

Leai

Uafu fa'aoso mo le fa'atusa. Fa'amaonia pe a la'ititi le fa'aoga A nai lo le fa'aoga B.

aeb

Leai

Uafu fa'aoso mo le fa'atusa. Fa'amaonia pe afai e tutusa le fa'aoga A ma le fa'aoga B.

agb

Leai

Uafu fa'aoso mo le fa'atusa. Fa'amaonia pe afai e sili atu le fa'aoga A nai lo le fa'aoga B.

tausagab

Leai

Uafu fa'aoso mo le fa'atusa. Fa'amaonia pe afai e sili atu pe tutusa le fa'aoga A i le fa'aoga

aneb

Leai

Uafu fa'aoso mo le fa'atusa. Fa'amaonia pe afai e le tutusa le fa'aoga A ma le fa'aoga B.

aleb

Leai

Uafu fa'aoso mo le fa'atusa. Fa'ailoa pe a la'ititi ifo pe tutusa le fa'aoga A i le fa'aoga B.

6.6. Parakalafa

O le laulau o loʻo i lalo o loʻo lisiina ai faʻamau mo le LPM_COMPARE IP autu.

Fuafuaga 20. LPM_COMPARE IP autu Parameter

Igoa Parameter

Ituaiga

Manaomia

LPM_WIDTH

Integer Ioe

LPM_REPRESENTATION

manoa

Leai

LPM_PIPELINE

Numera Nu

LPM_HINT

manoa

Leai

Fa'amatalaga
Fa'ailoa mai le lautele o ports dataa[] ma datab[].
Fa'ailoa mai le ituaiga fa'atusatusaga na faia. O tau e saini ma le le saini. Afai e ave'esea, ole tau fa'aletonu ole UNSIGNED. A fa'atulaga le tau fa'amaufa'ailoga i le SIGNED, e fa'amatalaina e le tagata fa'atusatusa le fa'auluina o fa'amaumauga e pei o le saini e lua.
Fa'amaoti le aofa'i o ta'amilosaga o le uati o le taofi e feso'ota'i ma le alb, aeb, agb, ageb, aleb, po'o le aneb gaioiga. Ole tau ole zero (0) o lo'o fa'aalia ai e leai se fa'aletonu o iai, ma o le a fa'atinoina se galuega fa'atasi. Afai e ave'esea, o le tau fa'aletonu o le 0 (le paipa).
Fa'ataga oe e fa'ailoa fa'amaufa'ailoga fa'apitoa a Intel ile mamanu VHDL files (.vhd). Ole tau fa'aletonu ole UNUSED.
faaauau…

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6. LPM_COMPARE (Fa'atusatusa) 683490 | 2020.10.05
Igoa Parameter LPM_TYPE INTENDED_DEVICE_FAMILY
ONE_INPUT_IS_CONSTANT

Fa'aigoa manoa
manoa

Manaomia Leai Nu
Leai

Fa'amatalaga
Fa'ailoa le faletusi o le fa'avasegaina o modules (LPM) igoa fa'alapotopotoga ile VHDL design files.
O lenei fa'ata'ita'iga e fa'aaogaina mo fa'ata'ita'iga ma fa'amoemoega fa'ata'ita'iga. E fa'atatau e le fa'atonu fa'ailoga le tau mo lea fa'ailoga.
Intel-fa'apitoa parakalafa. E tatau ona e fa'aogaina le LPM_HINT parakalafa e fa'amaoti ai le ONE_INPUT_IS_CONSTANT parakalafa ile VHDL design files. O fa'atatau o le IOE, LEAI, po'o le LE'I FA'A'OA'INA. E maua ai le fa'alelei sili atu pe afai e tumau pea le fa'aoga. Afai e ave'esea, ole tau fa'aletonu ole NO.

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7. ALTECC (Fa'atonu Fa'asa'o Fa'ailoga: Encoder/Decoder) IP Core

Ata 6.

Intel tu'uina atu le ALTECC IP autu e fa'atino ai galuega fa'atino a le ECC. E su'e e le ECC fa'amatalaga leaga o lo'o tupu i le itu e talia a'o fa'asalalauina fa'amatalaga. O lenei auala e fa'asa'o ai mea sese e sili ona fetaui mo tulaga e tutupu fa'afuase'i ai fa'aletonu nai lo le pa.

E iloa e le ECC mea sese e ala i le faʻagasologa o faʻamaumauga ma faʻavasegaina. Mo example, pe a faʻaaogaina le ECC i se faʻasalalauga talosaga, o faʻamatalaga faitau mai le puna e faʻailogaina aʻo leʻi auina atu i le tagata e taliaina. O le galuega faatino (code word) mai le encoder o lo'o i ai fa'amatalaga mata'utia ua fa'aopoopoina ma le aofa'i o pa'u tutusa. Ole numera sa'o ole pa'u fa'apipi'i e fa'atatau ile numera o pa'u ile fa'amatalaga fa'aulu. O le upu faakomepiuta ua gaosia e fa'asalalau atu lea i le mea e alu i ai.

E maua e le tagata e taliaina le upu fa'ailoga ma fa'aliliu ai. O fa'amatalaga e maua e le decoder e iloa ai pe maua se mea sese. O le decoder e iloa ai mea sese tasi-bit ma lua-bit, ae na'o le tasi-bit mea sese e mafai ona toe faaleleia i faʻamatalaga leaga. Ole ituaiga ECC ole fa'asa'oga fa'alua fa'alua (SECDED).

E mafai ona e fa'atulagaina galuega encoder ma decoder o le ALTECC IP core. O faʻamatalaga faʻapipiʻi i le encoder o loʻo faʻapipiʻiina e faʻatupu ai se upu faʻailoga o se tuʻufaʻatasiga o faʻamatalaga faʻamatalaga ma mea faʻapipiʻi tutusa. O le upu fa'ailoga ua fa'atupuina o lo'o tu'uina atu i le module decoder mo le fa'avasegaina a'o le'i o'o i lona poloka taunu'u. O le decoder e fa'atupuina ai se ma'i fa'ama'i e iloa ai pe i ai se mea sese i le upu code na maua. E fa'asa'o e le decoder fa'amaumauga pe a fai o le mea sese e tasi e sau mai fa'amaumauga. E leai se fa'ailoga e fa'ailogaina pe a fai o le mea sese e tasi e mai le pa'u pa'u. E iai fo'i fa'ailoga fu'a a le decoder e fa'aalia ai le tulaga o fa'amaumauga na maua ma le gaioiga na faia e le decoder, pe a iai.

O fa'atusa nei o lo'o fa'aalia ai ports mo le ALTECC IP core.

ALTECC Encoder Taulaga

ALTECC_ENCODER

fa'amatalaga[]

q[]

uati

aclr

inst

ISO 9001:2015 Resitala

7. ALTECC (Fa'atonu Fa'asa'o Fa'ailoga: Encoder/Decoder) IP Core 683490 | 2020.10.05

Ata 7. ALTECC Decoder Ports

ALTECC_DECODER

fa'amaumauga [] uati

q [] err_detected err_corrected
err_fatal

aclr

inst

7.1. ALTECC Encoder Features

O le ALTECC encoder IP core o loʻo ofoina atu uiga nei: · Faʻatino faʻasologa o faʻamatalaga e faʻaaoga ai le Hamming Coding scheme · Lagolagoina le lautele o faʻamatalaga o 2 bits · Lagolagoina le sainia ma le le sainia o faʻamatalaga faʻamatalaga · Lagolago pipelining faʻatasi ai ma le taofiofia o gaioiga o le tasi pe lua taamilosaga uati · Lagolago le faitalia asynchronous manino ma uati mafai ports

O le ALTECC encoder IP core e ave i totonu ma fa'ailoga fa'amaumauga e fa'aaoga ai le Hamming Coding scheme. O le Hamming Coding scheme e maua mai ai vaega tutusa ma fa'apipi'i i fa'amaumauga muamua e maua ai le upu fa'ailoga. Ole numera ole pa'u fa'aopoopo e fa'atatau ile lautele ole fa'amaumauga.

O le siata o lo'o i lalo o lo'o lisiina ai le aofa'i o pa'u tutusa ua fa'apipi'i mo vaega eseese o le lautele o fa'amaumauga. O le koluma Aofa'i Bits o lo'o fa'atusalia ai le aofa'i o fa'amaumauga o fa'amatalaga ma fa'aopoopo fa'atasi.

Laulau 21.

Numera o Parity Bits ma Code Word E tusa ai ma le lautele o faʻamatalaga

Fa'amatalaga Lautele

Numera o Piti Fa'atasi

Aofa'i Bits (Code Word)

2-4

3+1

6-8

5-11

4+1

10-16

12-26

5+1

18-32

27-57

6+1

34-64

58-64

7+1

66-72

O le fa'asologa o le pa'u e fa'aaogaina le siaki tutusa. O le 1 bit faaopoopo (fa'aali i le laulau e pei o le +1) o lo'o fa'apipi'iina i pa'u tutusa e pei o le MSB o le upu fa'ailoga. O le mea lea e fa'amautinoa ai o le upu fa'ailoga o lo'o i ai se numera tutusa o le 1's. Mo example, afai o le lautele o faamatalaga e 4 bits, 4 parity bits e faaopoopo i le faamatalaga e avea ma upu code ma le aofaiga o 8 bits. Afai 7 bits mai le LSB o le 8-bit code word ei ai se numera ese o le 1's, o le 8th bit (MSB) o le code word o le 1 ma le numera atoa o le 1's i le code word even.
O le ata o loʻo i lalo o loʻo faʻaalia ai le upu code faʻatupuina ma le faʻatulagaina o paʻu paʻu ma faʻamatalaga faʻamaumauga i totonu o le 8-bit faʻamatalaga faʻamatalaga.

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7. ALTECC (Fa'atonu Fa'asa'o Fa'ailoga: Encoder/Decoder) IP Core 683490 | 2020.10.05

Ata 8.

Fa'asologa Fa'atasi ma Fa'amatalaga Fa'amatalaga i totonu o le 8-Bit Generated Code Word

MSB

LSB

4 vaega tutusa

4 fa'amaumauga fa'amaumauga

Ole ALTECC encoder IP core e talia na'o le lautele ole ulufale ole 2 i le 64 bits ile taimi e tasi. Ole lautele ole ulufale ole 12 bits, 29 bits, ma le 64 bits, lea e fetaui lelei i masini Intel, e maua ai mea e maua mai i le 18 bits, 36 bits, ma le 72 bits. E mafai ona e pulea le fa'atapula'aina o le filifiliga i le fa'atonu fa'atonu.

7.2. Verilog HDL Prototype (ALTECC_ENCODER)
Ole Verilog HDL prototype o lo'o iai ile Verilog Design File (.v) lpm.v i le edasynthesis directory.
module altecc_encoder #( parameter intended_device_family = "le faʻaaogaina", parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = "altecc_encoder", parameter lpm_hint = "le faʻaaogaina") ( faʻaoga uaea aclr, faʻaoga uaea uaea, ulufale uaea uaea uaea uaea, uaea ulufale [width_dataword-1:0] fa'amaumauga, uaea mea e gaosia [width_codeword-1:0] q); endmodule

7.3. Verilog HDL Prototype (ALTECC_DECODER)
Ole Verilog HDL prototype o lo'o iai ile Verilog Design File (.v) lpm.v i le edasynthesis directory.
module altecc_decoder #( parameter intended_device_family = "le faʻaaogaina", parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = "altecc_decoder", parameter lpm_hint = "le faʻaaogaina") ( faʻaoga uaea aclr, faʻaoga uaea uaea, ulufale uaea uaea uaea uaea, uaea ulufale [width_codeword-1:0] fa'amatalaga, uaea fa'akomepiuta err_corrected, uaea uaea fa'aletonu ua iloa, uaea outut err_fatal, uaea uaea [width_dataword-1:0] q); endmodule

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7.4. Ta'utinoga Vaega VHDL (ALTECC_ENCODER)
O le ta'utinoga vaega VHDL o lo'o maua ile VHDL Design File (.vhd) altera_mf_components.vhd i le librariesvhdlaltera_mf directory.
vaega altecc_encoder generic ( intended_device_family: manoa : = "le faʻaaogaina"; lpm_pipeline: natura: = 0; width_codeword: natura: = 8; width_dataword: natura: = 8; lpm_hint: manoa : = "LE UA FAʻaogaina"; lpm_type: manoa: = "altecc_encoder ”); taulaga (aclr:i std_logic:= '0'; uati:i std_logic:= '0'; uati: i std_logic:= '1'; fa'amaumauga: i le std_logic_vector(width_dataword-1 i lalo i le 0); q: out std_logic_vector(width_codeword -1 i lalo i le 0)); vaega pito;
7.5. Ta'utinoga Vaega VHDL (ALTECC_DECODER)
O le ta'utinoga vaega VHDL o lo'o maua ile VHDL Design File (.vhd) altera_mf_components.vhd i le librariesvhdlaltera_mf directory.
vaega altecc_decoder generic ( intended_device_family: manoa : = "le faʻaaogaina"; lpm_pipeline: natura: = 0; width_codeword: natura: = 8; width_dataword: natura: = 8; lpm_hint: manoa : = "E LE'I FA'aogaina"; lpm_type: manoa: = "altecc_decoder ”); taulaga (aclr: i std_logic : = '0'; uati: i std_logic : = '0'; uati: i std_logic : = '1'; faʻamatalaga: i std_logic_vector(lautele_codeword-1 i lalo i le 0); err_corrected: fafo std_logic; err_detected : fafo std_logic q: fafo std_logic_vector(width_dataword-1 lalo i le 0); vaega pito;
7.6. VHDL LIBRARY_USE Tautinoga
Ole VHDL LIBRARY-USE ta'utinoga e le mana'omia pe a e fa'aogaina le VHDL Component Declaration.
LIBRARY altera_mf; USE altera_mf.altera_mf_components.all;
7.7. Encoder Taulaga
O siata o lo'o i lalo o lo'o lisiina ai ports o lo'o i totonu ma fa'aulufalega mo le ALTECC encoder IP core.

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7. ALTECC (Fa'atonu Fa'asa'o Fa'ailoga: Encoder/Decoder) IP Core 683490 | 2020.10.05

Laulau 22. ALTECC Encoder Input Ports

Igoa o le Taulaga

Manaomia

Fa'amatalaga

fa'amatalaga[]

Ioe

Taulaga e tu'u ai fa'amatalaga. Ole tele ole uafu fa'aoga e fa'alagolago ile WIDTH_DATAWORD

tau fa'ailoga. O le data[] uafu o lo'o i ai fa'amaumauga mata'utia e fa'ailoga.

uati

Ioe

Uati fa'aoga uafu e maua ai le fa'ailo o le uati e fa'afetaui ai le fa'agaioiga o le encoding.

E mana'omia le uati pe a sili atu le tau o le LPM_PIPELINE nai lo le 0.

uati

Leai

Uati mafai. Afai e ave'esea, o le tau fa'aletonu ole 1.

aclr

Leai

Fa'aoga manino asynchronous. Ole fa'ailoga aclr maualuga malosi e mafai ona fa'aoga i so'o se taimi e

fa'amama asynchronously tusi resitala.

Laulau 23. ALTECC Encoder Output Ports

Igoa o le Taulaga q[]

Manaomia Ioe

Fa'amatalaga
Fa'ailoga uafu fa'amaumauga. Ole tele ole uafu fa'aola e fa'alagolago ile WIDTH_CODEWORD parameter value.

7.8. Decoder Taulaga

O siata o lo'o i lalo o lo'o lisiina ai ports o lo'o i totonu ma fa'aulufalega mo le ALTECC decoder IP core.

Laulau 24. ALTECC Decoder Input Ports

Igoa o le Taulaga

Manaomia

Fa'amatalaga

fa'amatalaga[]

Ioe

Taulaga e tu'u ai fa'amatalaga. Ole tele ole uafu fa'aoga e fa'alagolago ile WIDTH_CODEWORD tau fa'ailoga.

uati

Ioe

Uati fa'aoga uafu e maua ai le fa'ailo o le uati e fa'afetaui ai le fa'agaioiga o le encoding. E mana'omia le uati pe a sili atu le tau o le LPM_PIPELINE nai lo le 0.

uati

Leai

Uati mafai. Afai e ave'esea, o le tau fa'aletonu ole 1.

aclr

Leai

Fa'aoga manino asynchronous. E mafai ona fa'aoga le fa'ailo maualuga aclr i so'o se taimi e fa'amama fa'atasi ai tusi resitala.

Siata 25. ALTECC Decoder Output Ports

Igoa o le Taulaga q[]

Manaomia Ioe

Fa'amatalaga
Decoded fa'amatalaga fa'amatalaga uafu. Ole tele ole uafu fa'aola e fa'alagolago ile WIDTH_DATAWORD parameter value.

err_detected Ioe

Fa'ailoga o le fu'a e atagia ai le tulaga o fa'amaumauga na maua ma fa'amaoti so'o se mea sese na maua.

err_fa'asa'o Ioe o

Fa'ailoga o le fu'a e atagia ai le tulaga o fa'amaumauga na maua. Fa'ailoa mai se mea sese e tasi na maua ma fa'asa'o. E mafai ona e fa'aogaina fa'amaumauga aua ua uma ona fa'asa'o.

err_fatal

Ioe

Fa'ailoga o le fu'a e atagia ai le tulaga o fa'amaumauga na maua. E fa'ailoa ai mea sese na maua, ae le'i fa'asa'oina. E le tatau ona e fa'aogaina fa'amaumauga pe a fa'ailoa mai lenei fa'ailoga.

syn_e

Leai

O se fa'ailoga o le a alu maualuga i so'o se taimi e iloa ai se mea sese e tasi i le parity

fasi.

7.9. Encoder Parameter
O le laulau o lo'o i lalo o lo'o lisiina ai fa'amaufa'ailoga mo le ALTECC encoder IP core.

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Laulau 26. ALTECC Encoder Parameter

Igoa Parameter

Ituaiga

Manaomia

Fa'amatalaga

WIDTH_DATAWORD

Integer Ioe

Fa'ailoa mai le lautele o fa'amatalaga mata'utia. O tau e mai le 2 i le 64. Afai e ave'esea, o le tau fa'aletonu o le 8.

WIDTH_CODEWORD

Integer Ioe

Fa'ailoa mai le lautele o le upu fa'ailoga tutusa. O tau aoga e mai le 6 i le 72, e le aofia ai le 9, 17, 33, ma le 65. Afai e ave'esea, o le tau fa'aletonu o le 13.

LPM_PIPELINE

Numera Nu

Fa'ailoa mai le paipa mo le ta'amilosaga. O tau e mai le 0 i le 2. Afai o le tau o le 0, o ports e le o resitalaina. Afai o le tau o le 1, ua resitalaina ports o galuega. Afai o le tau o le 2, o le ulufale ma le gaosiga o ports ua resitalaina. Afai e ave'esea, o le tau fa'aletonu ole 0.

7.10. Parameter Decoder

Ole laulau o lo'o i lalo ole lisi ole ALTECC decoder IP core parameters.

Laulau 27. ALTECC Decoder Parameters

Igoa Parameter WIDTH_DATAWORD

Ituaiga Integer

Manaomia

Fa'amatalaga

Ioe

Fa'ailoa mai le lautele o fa'amatalaga mata'utia. O tau e 2 i le 64. O le

le tau fa'aletonu ole 8.

WIDTH_CODEWORD

Integer

Ioe

Fa'ailoa mai le lautele o le upu fa'ailoga tutusa. O tau e 6

i le 72, e le aofia ai le 9, 17, 33, ma le 65. Afai e ave'esea, o le tau fa'aletonu

e 13.

LPM_PIPELINE

Integer

Leai

Fa'ailoa mai le resitala o le matagaluega. O tau e mai le 0 i le 2. Afai o le

tau e 0, e leai se resitala e fa'atinoina. Afai o le tau o le 1, o le

ua resitalaina galuega faatino. Afai o le tau o le 2, o le faʻaoga ma le

ua resitalaina galuega faatino. Afai e sili atu le tau nai lo le 2, faaopoopo

resitara o lo'o fa'atinoina ile galuega faatino mo le fa'aopoopoga

taofiga. Afai e ave'esea, o le tau fa'aletonu ole 0.

Fausia se taulaga 'syn_e'

Integer

Leai

Fa'aola le parakalafa e fai ai se taulaga syn_e.

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8. Intel FPGA Fa'aopoopo Fa'aopoopo IP Core

Ata 9.

O le Intel FPGA Multiply Adder (Intel Stratix 10, Intel Arria 10, ma le Intel Cyclone 10 GX masini) poʻo ALTERA_MULT_ADD (Arria V, Stratix V, ma le Afafā V masini) IP autu e mafai ai ona e faʻatinoina se faʻaopoopoga faʻateleina.

O le ata o loʻo i lalo o loʻo faʻaalia ai ports mo le Intel FPGA Multiply Adder poʻo le ALTERA_MULT_ADD IP core.

Intel FPGA Multiply Adder po'o ALTERA_MULT_ADD Taulaga

Intel FPGA Multiply Adder po'o ALTERA_MULT_ADD

dataa[] signa datab[] signb datac[] coefsel0[] coefsel1[] coefsel2[] coefsel3[] addnsub1 addnsub3 aclr/sclr[] scanina[] clock0 clock1 clock2 ena0 ena1 ena2 sload_accum
accum_sload chainin[]

scanouta[] taunuuga[]

aclr0 aclr1

inst
O le fa'aopoopo fa'atele e talia ta'ilua o mea fa'aoga, fa'atele fa'atasi fa'atatau ona fa'aopoopo lea pe to'ese mai oloa a isi paga uma.
Afai o le lautele o faʻamatalaga faʻapipiʻi uma e 9-bits lautele pe laʻititi, o le galuega e faʻaogaina le 9 x 9 bit input multiplier configuration i le DSP poloka mo masini e lagolagoina le 9 x 9 configuration. Afai e leai, o le poloka DSP e faʻaogaina le 18 × 18-bit faʻapipiʻi faʻapipiʻi e faʻagasolo ai faʻamatalaga ma le lautele i le va o le 10 bits ma le 18 bits. Afai e tele Intel FPGA Multiply Adder poʻo ALTERA_MULT_ADD IP cores e tupu i se mamanu, o galuega e tufatufa atu i le

ISO 9001:2015 Resitala

8. Intel FPGA Fa'aopoopo Fa'aopoopo IP Core 683490 | 2020.10.05
tele poloka DSP eseese e mafai ina ia sili atu ona fetuutuunai le auala i nei poloka. E itiiti fa'atele i poloka DSP e fa'ataga ai le tele o filifiliga fa'ata'ita'iina i totonu o le poloka e ala i le fa'aitiitia o ala ile isi vaega ole masini.
O tusi resitala ma isi resitara paipa mo faailoilo nei o loʻo tuʻuina foi i totonu o le poloka DSP: · Faʻamatalaga faʻamatalaga · Filifili saini pe leʻi sainia · Faʻaopoopo pe toese le filifilia · Oloa o faʻateleina
I le tulaga o le taunuuga o galuega, o le resitala muamua e tuʻuina i le poloka DSP. Ae ui i lea, o tusi resitala faaopoopo o loʻo tuʻuina i elemene talafeagai i fafo atu o le poloka. Peripheral i le poloka DSP, e aofia ai faʻamatalaga faʻapipiʻi i le faʻateleina, faʻaogaina o faailoilo faʻatonutonu, ma gaioiga a le faʻapipiʻi, faʻaoga faʻaoga masani e fesoʻotaʻi ma isi vaega o le masini. O feso'ota'iga uma i totonu o le galuega e fa'aogaina le ta'avale fa'apitoa i totonu ole poloka DSP. O lenei auala fa'apitoa e aofia ai filifili resitara sifi pe a e filifilia le filifiliga e fa'asolo ai fa'amatalaga fa'aulu a le fa'atele mai le fa'atele i le fa'atele lata ane.
Mo nisi fa'amatalaga e uiga i poloka DSP i so'o se fa'asologa o masini Stratix V, ma Arria V, va'ai i le DSP Blocks mataupu o tusitaulima ta'itasi i luga o le Literature and Technical Documentation page.
Fa'amatalaga Fa'afeso'ota'i AN 306: Fa'atinoina o Fa'atele i FPGA Devices
Tuuina atu nisi faʻamatalaga e uiga i le faʻatinoina o faʻaopoopoga e faʻaaoga ai DSP ma poloka manatua i masini Intel FPGA.
8.1. Vaega
O le Intel FPGA Multiply Adder po'o le ALTERA_MULT_ADD IP core e ofoina atu vaega nei: · Fa'atupuina se fa'atele e fa'atino ai fa'agaioiga fa'atele o fa'alavelave lavelave se lua.
numera Fa'amatalaga: A fau fa'atupu fa'atele e lapo'a atu nai lo le lapo'a e lagolagoina e le atunu'u e mafai ona/
o le a avea ma aafiaga fa'atinoga e mafua mai i le fa'aoso o poloka DSP. · Lagolago le lautele o faʻamatalaga o le 1 256 bits · Lagolagoina le sainia ma le le faʻamaonia le faʻatusaina o faʻamatalaga · Lagolago pipelining ma configurable input latency · Tuuina atu se filifiliga e fesuiai dynamically i le va o saini ma le saini lagolago faamatalaga · Tuuina atu se filifiliga e dynamically fesuiai i le va o le faaopoopo ma le toese galuega · Lagolago filifiliga asynchronous ma synchronous manino ma uati mafai ai ports ulufale · Lagolago systolic tuai faiga resitala · Lagolago muamua-adder ma 8 muamua uta coefficients mo faatele · Lagolago muamua uta i taimi uma e faaatoatoa ai tali accumulator

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8.1.1. Mu'ai fa'aopoopo
Faatasi ai ma le mua'i fa'aopoopo, fa'aopoopo po'o toese e fai a'o le'i fafaga le fa'atele.
E lima auala e le'i fa'apipi'i: · Fa'afaigofie le faiga · Fa'asagaga fa'aopoopo · Faiga fa'aaofia · Fa'ailoga sikuea · Fa'asolo pea.

Fa'aaliga:

A fa'aogaina le fa'auluina o le fa'aopoopo (fa'aopoopo muamua/fa'aulu/faiga sikuea), o fa'amatalaga uma e tu'uina atu i le fa'atele e tatau ona tutusa le seti o le uati.

8.1.1.1. Fa'apena Fa'aopoopo Faiga Faigofie

I lenei faiga, e lua operand e maua mai i totonu o ports ma e le'o fa'aogaina pe fa'aluma le fa'aulu. O le tulaga masani lea.

Ata 10. Fa'apena Fa'aopoopo Faiga Fa'afaigofie
a0 b0

Fa'atele0

taunuuga

8.1.1.2. Faiga Fa'aopoopo muamua
I lenei faiga, o le tasi operand multiplier e maua mai le pre-adder, ae o le isi operand e maua mai i totonu o le coefficient storage. O le coefficient teuina e mafai ai e oʻo atu i le 8 faʻatulagaina tumau. O fa'ailoga filifilia fa'atasi o le coefsel[0..3].
O lenei faiga o lo'o fa'aalia i le fa'atusa lea.

O lo'o fa'aalia i lalo le faiga fa'aopoopo muamua o le fa'atele.

Fa'ata 11. Fa'aaopoga Fa'aopoopo Fa'atasi

Faife'au

Fa'atele0

+/-

taunuuga

coefsel0 coef

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8.1.1.3. Faiga Fa'auluina Fa'aulu I totonu o lenei faiga, e maua mai le operand fa'atele e tasi mai le fa'aulu, ae o le isi operand e maua mai i le datac[] uafu ulufale. O lenei faiga o lo'o fa'aalia i le fa'atusa lea.

O lo'o fa'aalia i lalo le faiga fa'aulu o le fa'aopoopo fa'atele.

Ata 12. Faiga Fa'auluina Fa'aopoopo
a0 b0

Fa'atele0

+/-

taunuuga

8.1.1.4. Faiga Fa'aigoa Fa'amuamua O lenei faiga o lo'o fa'aalia i le fa'atusa o lo'o mulimuli mai.

O lo'o fa'aalia i lalo le fa'ailoga sikuea muamua o fa'atele e lua.

Ata 13. Fa'ailoga Fa'ailoga Fa'ato'aga
a0 b0

Fa'atele0

+/-

taunuuga

8.1.1.5. A'o le'i fa'aopoopo Faiga Tumau
I lenei faiga, o le tasi operand multiplier e maua mai i totonu o le uafu, ae o le isi operand e maua mai i totonu o le teuina o le coefficient. O le coefficient teuina e mafai ai e oʻo atu i le 8 faʻatulagaina tumau. O fa'ailo filifiliga fa'ai'uga o fa'ailoga o le coefsel[0..3].
O lenei faiga o lo'o fa'aalia i le fa'atusa lea.

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O le ata o lo'o i lalo o lo'o fa'aalia ai le faiga faifai pea a'o le'i fa'aopoopoina le fa'atele.

Ata 14. Fa'apena Fa'aopoopo Faiga Tumau
a0

Fa'atele0

taunuuga

fa'atasi0
kofe
8.1.2. Tusitala Fa'atuai Systolic
I totonu o se fausaga faʻapitoa, o faʻamatalaga o loʻo tuʻuina atu e fafaga i totonu o se cascade o tusi resitala o loʻo galue o se faʻamaumauga faʻamaumauga. E tu'uina atu e tusi resitala ta'itasi se fa'aoga sample i se faatele e faatele ai i le coefficient taitasi. O le mea fa'aopoopo filifili e teuina fa'atasi fa'asolosolo fa'ai'uga mai le fa'atele ma le fa'ai'uga na resitalaina muamua mai le chainin[] uafu fa'aulu e fai ai le i'uga mulimuli. O elemene ta'itasi fa'atele-fa'aopoopo e tatau ona tuai i se ta'amilosaga e tasi ina ia fetaui lelei fa'ai'uga pe a fa'aopoopo fa'atasi. O fa'atuai fa'asolosolo ta'itasi e fa'aoga e fa'afeso'ota'i uma le coefficient memory ma le fa'amaumauga o fa'amaumauga a latou elemene fa'atele-faaopoopo. Mo example, e tasi le tuai mo le elemene lona lua faʻaopoopo faʻaopoopo, lua faʻatuai mo le lona tolu faʻateleina-faaopoopo elemene, ma isi.
Ata 15. Tusi Resitala Systolic
Tusi resitala systolic

x(t) c(0)

S -1

c(1)

S -1

c(2)

S -1

c(N-1)

S -1

S -1 y(t)

x(t) o lo'o fa'atusalia ai taunu'uga mai le fa'aauau pea o fa'aulufalega samples ma y(t)
o lo'o fa'atusalia le aofa'iga o se seti o fa'aoga samples, ma i le taimi, faateleina i latou
coefficient taitasi. O fa'ai'uga fa'aoga ma fa'ai'uga e tafe mai le agavale i le taumatau. O le c(0) i le c(N-1) o lo'o fa'aalia ai le coefficient. O tusi resitala tuai o le systolic o loʻo faʻaalia e le S-1, ae o le 1 o loʻo faʻatusalia ai le tuai o le uati e tasi. Fa'aopoopo tusi resitala fa'atuai i
o mea fa'aoga ma mea e fa'atino mo le paipa i se auala e fa'amautinoa ai taunu'uga mai le
fa'atele operand ma le aofa'i fa'aputuga tumau i le fa'atasi. Lenei elemene galue
o lo'o fa'atusaina e fai ai se ta'amilosaga e fa'atatau le galuega fa'amama. O lenei galuega e
fa'aalia i le fa'atusa o lo'o mulimuli mai.

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N o lo'o fa'atusalia ai le aofa'i o ta'amilosaga o fa'amaumauga na tu'u i totonu o le fa'aputuga, y(t) o lo'o fa'atusalia ai le gaosiga i le taimi t, A(t) o lo'o fa'atusalia le fa'aoga i le taimi t, ma le B(i) o fa'atasi. O le t ma le i i le fa'atusatusaga e fetaui ma se taimi fa'apitoa i le taimi, ina ia fa'atatau le sample y(t) i le taimi t, o se vaega o mea e fai samples i N taimi eseese i le taimi, poʻo A(n), A(n-1), A(n-2), … A(n-N+1) e manaʻomia. O le vaega o N fa'aoga sampe fa'ateleina le N fa'atasi ma fa'aputu fa'atasi e maua ai le i'uga mulimuli y.
O le fa'ailoga tusi resitala e na'o le sum-of-2 ma le sum-of-4 e avanoa. Mo fa'asologa fa'atusitala fa'apitoa e lua, o le fa'ailoga muamua o le chainin e mana'omia ona nonoa i le 0.
O le ata o lo'o i lalo o lo'o fa'aalia ai le fa'atinoina o le resitara fa'atuai o le systolic o fa'atele e 2.
Ata 16. Systolic Delay Register Fa'atinoga o Fa'atele Fa'atele
chainin

Fa'atele0

+/-

Fa'atele1

+/-

taunuuga
O le aofa'iga o fa'atele e lua o lo'o fa'aalia i le fa'atusa lea.
O le ata o lo'o i lalo o lo'o fa'aalia ai le fa'atinoina o le resitara fa'atuai o le systolic o fa'atele e 4.

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Ata 17. Systolic Delay Register Fa'atinoga o Fa'atele Fa'atele
chainin

Fa'atele0

+/-

Fa'atele1

+/-

Fa'atele2

+/-

Fa'atele3

+/-

taunuuga
O le aofa'i o fa'atele e fa o lo'o fa'aalia i le fa'atusa o lo'o i lalo. Ata 18. Fa'ato'a 4 Fa'atele
Ole lisi lea ole advantago le fa'atinoga o le resitalaina fa'ale-aganu'u: · Fa'aiti'itia le fa'aogaina o puna'oa DSP · Fa'aagaaga lelei fa'afanua ile poloka DSP e fa'aoga ai le fausaga fa'apipi'i filifili.

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8.1.3. Mu'i uta Constant
O le fa'auma muamua e fa'atonutonu ai le operand accumulator ma fa'atutusa ai le fa'aputuga tali mai. O LOADCONST_VALUE aoga e amata mai i le 0. O le tau faifaipea e tutusa ma le 64N, lea N = LOADCONST_VALUE. Pe a seti le LOADCONST_VALUE i le 2, o le tau faifaipea e tutusa ma le 64. O lenei galuega e mafai ona faʻaaogaina e pei o le faʻaituau faʻataʻamilosaga.
O le ata o loʻo i lalo o loʻo faʻaalia ai le faʻatinoina faifai pea muamua.
Fa'ata 19. Mu'i uta Constant

Fa'amatalaga a le accumulator

tumau

Fa'atele0

+/-

Fa'atele1

+/b1

taunuuga

accum_sload sload_accum

Va'ai i le IP cores mo isi fa'atinoga fa'atele: · ALTMULT_ACCUM · ALTMEMMULT · LPM_MULT
8.1.4. Fa'aputu Fa'alua
O le vaega fa'aopoopo fa'aopoopo fa'aopoopo e fa'aopoopoina ai se resitara fa'aopoopo i le ala o fa'amatalaga fa'aputu. O le resitara fa'aputu fa'alua e mulimulita'i i le tusi resitala o galuega, lea e aofia ai le uati, uati mafai, ma le aclr. O le tusi resitala fa'aopoopo fa'aopoopo e toe fa'afo'i le i'uga i le tuai o le ta'amilosaga e tasi. O lenei fa'ailoga e mafai ai ona e maua ni alavai fa'aputu se lua e tutusa le aofa'i o puna'oa.
O le ata o loʻo i lalo o loʻo faʻaalia ai le faʻatinoina o le accumulator faalua.

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Ata 20. Fa'aopoopo Fa'alua

Fa'alua Accu mulator Resitala

Accu mulator feedback ck

Fa'atele0

+/-

Fa'atele1

+/b1

Fa'ai'uga taunu'u Tusi Resitala

8.2. Verilog HDL Prototype
E mafai ona e mauaina le Intel FPGA Multiply Adder poʻo ALTERA_MULT_ADD Verilog HDL prototype file (altera_mult_add_rtl.v) i le librariesmegafunctions directory.
8.3. VHDL Fa'aaliga Vaega
O le ta'utinoga vaega VHDL o lo'o maua ile altera_lnsim_components.vhd ile faletusivhdl altera_lnsim directory.
8.4. VHDL LIBRARY_USE Tautinoga
Ole VHDL LIBRARY-USE ta'utinoga e le mana'omia pe a e fa'aogaina le VHDL Component Declaration.
LIBRARY altera_mf; USE altera_mf.altera_mf_components.all;

8.5. Fa'ailoga

O laulau o lo'o i lalo o lo'o lisiina ai fa'ailoga fa'aoga ma fa'ailoga o le Multiply Adder Intel FPGA IPor ALTERA_MULT_ADD IP core.

Laulau 28. Fa'atele le Fa'aopoopo Intel FPGA IP po'o ALTERA_MULT_ADD Fa'ailoga Fa'aofi.

Fa'ailoga

Manaomia

Fa'amatalaga

dataa_0[]/dataa_1[]/

Ioe

dataa_2[]/dataa_3[]

Tuuina atu o faamatalaga i le faatele. Fa'aoga uafu [NUMBER_OF_MULTIPLIERS * WIDTH_A – 1 … 0] lautele
faaauau…

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Signal datab_0[]/datab_1[]/ datab_2[]/datab_3[] datac_0[] /datac_1[]/ datac_2[]/datac_3[] uati[1:0] aclr[1:0] sclr[1:0] ena [1:0] faailoga
fa'ailogab
scanina[] accum_sload

Manaomia Ioe Leai
Leai Leai Leai Leai
Leai
Leai Leai

Fa'amatalaga
O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i nei faailo. A e tuʻuina atu le tau X i nei faʻailoga, o le tau X e faʻasalalau i luga o faʻailoga o galuega.
Tuuina atu o faamatalaga i le faatele. Fa'ailoga fa'aulu [NUMBER_OF_MULTIPLIERS * WIDTH_B – 1 … 0] lautele O le fa'ata'ita'iga fa'ata'ita'iga mo lenei IP e lagolagoina le tau fa'aofi e le'i fuafuaina (X) i nei fa'ailoga. A e tuʻuina atu le tau X i nei faʻailoga, o le tau X o loʻo faʻasalalau i luga o faailo o galuega.
Tuuina atu o faamatalaga i le faatele. Fa'ailoga fa'aulu [NUMBER_OF_MULTIPLIERS * WIDTH_C – 1, … 0] lautele Filifili INPUT mo Filifili le fa'asologa o le fa'asologa o talatala e mafai ai nei faailo. O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i nei faailo. A e tuʻuina atu le tau X i nei faʻailoga, o le tau X o loʻo faʻasalalau i luga o faailo o galuega.
Uati fa'aoga uafu i le tusi resitala talafeagai. O lenei faailo e mafai ona faʻaogaina e soʻo se resitala i totonu ole IP. O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i nei faailo. A e tuʻuina atu le tau X i nei faʻailoga, o le tau X o loʻo faʻasalalau i luga o faailo o galuega.
Asynchronous fa'aoga manino i le tusi resitala talafeagai. O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i nei faailo. A e tuʻuina atu le tau X i nei faʻailoga, o le tau X o loʻo faʻasalalau i luga o faailo o galuega.
Fa'asoa manino fa'aoga i le tusi resitala talafeagai. O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaoga X i nei faailoilo. A e tuʻuina atu le tau X i nei faʻailoga, o le tau X o loʻo faʻasalalau i luga o faailo o galuega
Fa'afeso'ota'i le fa'aoga o fa'ailo i le tusi resitala talafeagai. O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i nei faailo. A e tuʻuina atu le tau X i nei faʻailoga, o le tau X o loʻo faʻasalalau i luga o faailo o galuega.
Fa'ama'oti le fa'atusa fa'anumera o le fa'aopoopo fa'aulu A. Afai e maualuga le fa'ailoga, e fa'aogaina e le fa'atele le fa'ailoga fa'aopoopo A o se numera saini. Afai e maualalo le fa'ailoga, o le fa'atele e fa'aogaina le fa'ailoga fa'aopoopo A o se numera e le'i sainia. Filifili VARIABLE mo O le a le fa'atusa fa'atusa mo Fa'atele A mea fa'aoga parakalafa e mafai ai lenei fa'ailoga. O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i lenei faailo. A e tu'uina atu le tau X i lenei fa'aoga, o le tau X o lo'o fa'asalalauina i luga o fa'ailoga o galuega.
Fa'amaoti le fa'atusa fa'anumera o le fa'ailoga fa'aopoopo B fa'aoga. Afai e maualuga le fa'ailoga saini, e fa'aogaina e le tagata fa'atele le fa'ailoga B fa'aopoopo e fai ma numera fa'aopoopo a le lua ua sainia. Afai e la'ititi le fa'ailoga fa'ailoga, e fa'aogaina e le fa'atele le fa'ailoga B fa'atuputeleina o se numera e le'i sainia. O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i lenei faailo. A e tu'uina atu le tau X i lenei fa'aoga, o le tau X o lo'o fa'asalalauina i luga o fa'ailoga o galuega.
Ulufale mo filifili filifili A. Fa'ailoga fa'aofi [WIDTH_A – 1, … 0] lautele. Afai ole INPUT_SOURCE_A e iai se aoga ole SCANA, e mana'omia le faailo scanina[].
Fa'ailoa fa'amalosi pe tumau pea le tau fa'aputu. Afai e maualalo le faailo o le accum_sload, ona utaina lea o le gaosiga faʻateleina i totonu o le accumulator. Aua le fa'aogaina le accum_sload ma le sload_accum i le taimi e tasi.
faaauau…

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Fa'ailoga sload_accum
chainin[] addnsub1
addnsub3
coefsel0[] coefsel1[] coefsel2[] coefsel3[]

Manaomia Nu
Leai Leai
Leai
Leai Leai Leai

Fa'amatalaga
O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i lenei faailo. A e tu'uina atu le tau X i lenei fa'aoga, o le tau X o lo'o fa'asalalauina i luga o fa'ailoga o galuega.
Fa'ailoa fa'amalosi pe tumau pea le tau fa'aputu. Afai e maualuga le faailo o le sload_accum, ona utaina lea o le gaosiga faʻateleina i totonu o le accumulator. Aua le fa'aogaina le accum_sload ma le sload_accum i le taimi e tasi. O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i lenei faailo. A e tu'uina atu le tau X i lenei fa'aoga, o le tau X o lo'o fa'asalalauina i luga o fa'ailoga o galuega.
Fa'aopoopo i'uga fa'aoga pasi mai le s muamuatagu. Fa'ailoga fa'aofi [WIDTH_CHAININ – 1, … 0] lautele.
Fai fa'aopoopo po'o to'ese i mea e maua mai le paga muamua o fa'atele. Ulufale 1 i le addnsub1 fa'ailoga e fa'aopoopo ai mea e maua mai le paga muamua o fa'atele. Fa'aulu 0 i le fa'aopoopoina fa'ailoga e to'ese ai mea na maua mai le pa'aga muamua o fa'atele. O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i lenei faailo. A e tu'uina atu le tau X i lenei fa'aoga, o le tau X o lo'o fa'asalalauina i luga o fa'ailoga o galuega.
Fai fa'aopoopo po'o to'ese i mea e maua mai le paga muamua o fa'atele. Ulufale 1 i le addnsub3 fa'ailoga e fa'aopoopo ai mea e maua mai i le paga lona lua o fa'atele. Fa'aulu 0 i le fa'ailoga addnsub3 e to'ese ai mea na maua mai le pa'aga muamua o fa'atele. O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i lenei faailo. A e tu'uina atu le tau X i lenei fa'aoga, o le tau X o lo'o fa'asalalauina i luga o fa'ailoga o galuega.
Fa'ailo fa'aulu fa'atasi [0:3] i le fa'atele muamua. O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i lenei faailo. A e tu'uina atu le tau X i lenei fa'aoga, o le tau X o lo'o fa'asalalauina i luga o fa'ailoga o galuega.
Fa'ailo fa'aulu fa'atasi[0:3]i le fa'atele lona lua. O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i lenei faailo. A e tu'uina atu le tau X i lenei fa'aoga, o le tau X o lo'o fa'asalalauina i luga o fa'ailoga o galuega.
Fa'ailoga fa'akomepiuta fa'aoga[0:3]i le fa'atele lona tolu. O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i lenei faailo. A e tu'uina atu le tau X i lenei fa'aoga, o le tau X o lo'o fa'asalalauina i luga o fa'ailoga o galuega.
Fa'ailo fa'aulu fa'atasi [0:3] i le fa'atele lona fa. O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP e lagolagoina le tau faʻaogaina (X) e leʻi fuafuaina i lenei faailo. A e tu'uina atu le tau X i lenei fa'aoga, o le tau X o lo'o fa'asalalauina i luga o fa'ailoga o galuega.

Laulau 29. Fa'atele le Adder Intel FPGA IP Output Signals

Fa'ailoga

Manaomia

Fa'amatalaga

i'uga []

Ioe

Fa'ailoga fa'atupu fa'atele. Fa'ailoga fa'aalia [WIDTH_RESULT – 1 … 0] lautele

O le faʻataʻitaʻiga faʻataʻitaʻiga mo lenei IP o loʻo lagolagoina le tau o galuega e leʻi fuafuaina (X). A e tuʻuina atu le tau X e fai ma faʻaoga, o le tau X e faʻasalalau i luga o lenei faailo.

scanouta []

Leai

Fa'ailoga o le filifili fa'ata'ita'i A. Fa'ailoga fa'ailoga [WIDTH_A – 1..0] lautele.

Filifili sili atu nai lo le 2 mo numera o fa'atele ma filifili Su'e filifili filifili mo O le a le fa'aoga A o le fa'atele e feso'ota'i i le parakalafa e mafai ai lenei fa'ailoga.

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8.6. Parakalafa

8.6.1. General Tab

Laulau 30. Laulau Lautele

Parameter

IP Fausia Parameter

Taua

O le a le numera o fa'atele?

numera_o_m 1 – 4 ultipliers

O le a le lautele e tatau ona i ai pasi ulufale A width_a?

1 – 256

O le a le lautele e tatau ona iai i totonu o pasi B width_b?

1 – 256

O le a le lautele e tatau ona i ai le 'fua'aga o le pasi?

width_reult

1 – 256

Fausia se uati feso'ota'i e mafai ai mo uati ta'itasi

gui_associate I luga d_clock_enabl Tape u

8.6.2. Faiga Fa'aopoopo Tab

Laulau 31. Faiga Fa'aopoopo Tab

Parameter

IP Fausia Parameter

Taua

Fa'atonuga o mea e fai

Resitala galuega faatino a le iunite faaopoopo

gui_output_re On

tui

Tape

O le a le fa'apogai mo le fa'aogaina o le uati?

gui_output_re gister_clock

Uati0 Uati1 Uati2

O le a le fa'apogai mo fa'aoga manino e le'i tutusa?

gui_output_re gister_aclr

LEAI ACLR0 ACLR1

O le a le fa'apogai mo fa'aoga manino fa'atasi?

gui_output_re gister_sclr

LEAI SCLR0 SCLR1

Fa'atonuga Fa'aopoopo

O le a le gaioiga e tatau ona faia i mea e maua mai i le paga muamua o fa'atele?

gui_multiplier 1_direction

ADD, SUB, FUAFUAGA

Taua Fa'aleaogaina 1
16

Fa'amatalaga
Numera o fa'atele e fa'aopoopo fa'atasi. O tau e 1 e oo i le 4. Fa'ailoa le lautele o le dataa[] port.

Fa'ailoa le lautele o le datab[] port.

Fa'ailoa le lautele o le taunu'uga[] uafu.

Tape

Filifili le filifiliga lea e fai ai le uati e mafai ai

mo uati taitasi.

Tau Fa'atonu

Fa'amatalaga

Tape le Uati0
LEAI LEAI

Filifili le filifiliga lea e mafai ai ona resitala galuega o le module adder.
Filifili le Uati0, Uati1 po'o le Uati2 e mafai ai ma fa'amaonia le puna o le uati mo tusi resitala o galuega. E tatau ona e filifilia le Resitala o mea e fai o le adder unit ina ia mafai ai lenei parakalafa.
Fa'amaoti mai le puna manino e le fa'aogaina mo le tusi resitala o mea fa'aopoopo. E tatau ona e filifilia le Resitala galuega o le iunite fa'aopoopo ina ia mafai ai lenei parakalafa.
Fa'amaoti le puna manino fa'atasi mo le tusi resitala o mea fa'aopoopo. E tatau ona e filifilia le Resitala galuega o le iunite fa'aopoopo ina ia mafai ai lenei parakalafa.

FA'AFI

Filifili le fa'aopoopoga po'o le to'esega e fa'atino mo galuega fa'atino i le va o fa'atele muamua ma lona lua.
· Filifili le ADD e fai ai le faʻaopoopoga o gaioiga.
· Filifili le SUB e faatino ai le galuega toese.
· Filifili VARIABLE e faʻaoga ai le addnsub1 port mo le faʻamalosia o le faʻaopoopoga/toʻesega pulea.
faaauau…

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Parameter

IP Fausia Parameter

Taua

Resitala 'addnsub1' fa'aoga

gui_addnsub_ On multiplier_reg Off ister1

O le a le fa'apogai mo le fa'aogaina o le uati?

gui_addnsub_ multiplier_reg ister1_clock

Uati0 Uati1 Uati2

O le a le fa'apogai mo fa'aoga manino e le'i tutusa?

gui_addnsub_ multiplier_aclr 1

LEAI ACLR0 ACLR1

O le a le fa'apogai mo fa'aoga manino fa'atasi?

gui_addnsub_ multiplier_sclr 1

LEAI SCLR0 SCLR1

O le a le gaioiga e tatau ona faia i mea e maua mai i le paga lona lua o fa'atele?

gui_multiplier 3_direction

ADD, SUB, FUAFUAGA

Resitala 'addnsub3' fa'aoga

gui_addnsub_ On multiplier_reg Off ister3

O le a le fa'apogai mo le fa'aogaina o le uati?

gui_addnsub_ multiplier_reg ister3_clock

Uati0 Uati1 Uati2

Tau Fa'atonu
Pepe le Uati0 LEAI LEAI LEAI FAAFULU
Tape le Uati0

Fa'amatalaga
A filifilia le tau VARIABLE: · Ave le faailo addnsub1 i le maualuga mo
galuega fa'aopoopo. · Ave le faailo addnsub1 i lalo mo
galuega toesea. E tatau ona e filifilia le sili atu ma le lua fa'atele e fa'aagaaga ai lenei fa'ailoga.
Filifili le filifiliga lea e mafai ai ona fa'aoga tusi resitala mo addnsub1 port. E tatau ona e filifili VARIABLE mo O le a le gaioiga e tatau ona faia i luga o galuega faatino o le lua muamua o faʻatele e mafai ai lenei parakalafa.
Filifili le Uati0, Uati1 po'o le Uati2 e fa'ailoa ai le fa'ailoga uati ulufale mo le resitara addnsub1. E tatau ona e filifili Resitala 'addnsub1' fa'aoga ina ia mafai ai lenei parakalafa.
Fa'amaoti le puna manino asynchronous mo le resitara addnsub1. E tatau ona e filifili Resitala 'addnsub1' fa'aoga ina ia mafai ai lenei parakalafa.
Fa'ailoa mai le puna manino fa'atasi mo le resitara addnsub1. E tatau ona e filifili Resitala 'addnsub1' fa'aoga ina ia mafai ai lenei parakalafa.
Filifili le fa'aopoopoga po'o le to'esega gaioiga e fa'atino mo galuega fa'atino i le va o fa'atele lona tolu ma le fa. · Filifili ADD e fai fa'aopoopo
fa'agaioiga. · Filifili le SUB e fai toesea
fa'agaioiga. · Filifili VARIABLE e fa'aoga addnsub1
uafu mo le malosi fa'aopoopo/to'ese pulea. Pe a filifilia le tau VARIABLE: · Ave le faailo addnsub1 i le maualuga mo le faʻaogaina o mea. · Ave le fa'ailoga addnsub1 i lalo mo le fa'agaioiga toese. E tatau ona e filifilia le tau 4 mo le O le a le numera o faʻateleina? e mafai ai lenei parakalafa.
Filifili le filifiliga lea e mafai ai ona fa'aoga le resitala mo fa'ailoga addnsub3. E tatau ona e filifilia le VARIABLE mo O le a le gaioiga e tatau ona faia i luga o galuega faatino a le lua lona lua o faʻatele e mafai ai lenei parakalafa.
Filifili le Uati0, Uati1 po'o le Uati2 e fa'ailoa mai ai le fa'ailoga uati ulufale mo le resitala addnsub3. E tatau ona e filifili le Resitala 'addnsub3' fa'aoga ina ia mafai ai lenei parakalafa.
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Parameter
O le a le fa'apogai mo fa'aoga manino e le'i tutusa?

IP Fausia Parameter

Taua

gui_addnsub_ multiplier_aclr 3

LEAI ACLR0 ACLR1

O le a le fa'apogai mo fa'aoga manino fa'atasi?

gui_addnsub_ multiplier_sclr 3

LEAI SCLR0 SCLR1

Polarity Enable `use_subadd'

gui_use_subn On

fa'aopoopo

Tape

8.6.3. Faatele Tab

Laulau 32. Fa'atele Fa'atele

Parameter

IP Fausia Parameter

Taua

O le a le

gui_represent

fa'atusa fa'atusa ation_a

mo mea fa'aopoopo A?

SAINI, LE'I SA'I, FUAFUAGA

Resitala 'signa' fa'aoga

gui_register_s On

igna

Tape

O le a le fa'apogai mo le fa'aogaina o le uati?

gui_register_s igna_clock

Uati0 Uati1 Uati2

O le a le fa'apogai mo fa'aoga manino e le'i tutusa?

gui_register_s igna_aclr

LEAI ACLR0 ACLR1

O le a le fa'apogai mo fa'aoga manino fa'atasi?

gui_register_s igna_sclr

LEAI SCLR0 SCLR1

O le a le

gui_represent

fa'atusa fa'atusa ation_b

mo mea fa'aopoopo B?

SAINI, LE'I SA'I, FUAFUAGA

Resitala 'signb' mea e fai

gui_register_s On

igb

Tape

Fa'atatau Taua E LEAI
E LEAI

Fa'amatalaga
Fa'amaoti le puna manino asynchronous mo le resitara addnsub3. E tatau ona e filifili Resitala 'addnsub3' fa'aoga ina ia mafai ai lenei parakalafa.
Fa'amaoti le puna manino fa'atasi mo le resitara addnsub3. E tatau ona e filifili le Resitala 'addnsub3' fa'aoga ina ia mafai ai lenei parakalafa.

Tape

Filifili le filifiliga lea e toe fa'afo'i le galuega

o addnsub uafu ulufale.

Avea le addnsub i le maualuga mo le fa'agaioiga toese.

Ave le addnsub i lalo mo le faʻaopoopoga o gaioiga.

Tau Fa'atonu

Fa'amatalaga

UNSIGNED Fa'ailoa mai le fa'atusa mo le fa'aulu A fa'aulu.

Tape

Filifili lenei filifiliga e mafai ai le faʻailoga

resitala.

E tatau ona e filifilia le tau VARIABLE mo O le a le fa'atusa fa'atusa mo mea fa'aopoopo A? parakalafa e mafai ai lenei filifiliga.

Uati0

Filifili le Uati0, Uati1 po'o le Uati2 e fa'aaga ma fa'amaoti ai le fa'ailo o le uati ulufale mo le resitala fa'ailoga.
E tatau ona e filifili le Resitala 'signa' input e mafai ai lenei parakalafa.

E LEAI

Fa'amaoti mai le puna manino asynchronous mo le resitala saini.
E tatau ona e filifili le Resitala 'signa' input e mafai ai lenei parakalafa.

E LEAI

Fa'ailoa mai le puna manino fa'atasi mo le resitala fa'ailoga.
E tatau ona e filifili le Resitala 'signa' input e mafai ai lenei parakalafa.

UNSIGNED Fa'ailoa mai le fa'atusa mo le fa'aopoopo B fa'aoga.

Tape

Filifili le filifiliga lea e mafai ai le sainib

resitala.

faaauau…

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Parameter

IP Fausia Parameter

Taua

Tau Fa'atonu

O le a le fa'apogai mo le fa'aogaina o le uati?

gui_register_s ignb_clock

Uati0 Uati1 Uati2

Uati0

O le a le fa'apogai mo fa'aoga manino e le'i tutusa?

gui_register_s ignb_aclr

LEAI ACLR0 ACLR1

O le a le fa'apogai mo fa'aoga manino fa'atasi?

gui_register_s ignb_sclr

LEAI SCLR0 SCLR1

Faiga Fa'aofi
Resitala fa'aoga A o le fa'atele
O le a le fa'apogai mo le fa'aogaina o le uati?

gui_input_reg I luga

ister_a

Tape

gui_input_reg ister_a_clock

Uati0 Uati1 Uati2

LEAI LEAI
Tape le Uati0

O le a le fa'apogai mo fa'aoga manino e le'i tutusa?

gui_input_reg ister_a_aclr

LEAI ACLR0 ACLR1

O le a le fa'apogai mo fa'aoga manino fa'atasi?

gui_input_reg ister_a_sclr

LEAI SCLR0 SCLR1

Resitala mea fa'aoga B o le fa'atele
O le a le fa'apogai mo le fa'aogaina o le uati?

gui_input_reg I luga

ister_b

Tape

gui_input_reg ister_b_clock

Uati0 Uati1 Uati2

E LEAI LEAI Sese Uati0

O le a le fa'apogai mo fa'aoga manino e le'i tutusa?

gui_input_reg ister_b_aclr

LEAI ACLR0 ACLR1

E LEAI

O le a le fa'apogai mo fa'aoga manino fa'atasi?

gui_input_reg ister_b_sclr

LEAI SCLR0 SCLR1

E LEAI

O le a le fa'aoga A o le fa'atele e feso'ota'i i ai?

gui_multiplier Fa'atele mea fa'aoga Fa'atele

_a_tulaga

Su'e fa'aoga filifili filifili

Fa'amatalaga
E tatau ona e filifilia le tau VARIABLE mo le O le a le fa'atusa fa'atusa mo mea fa'aopoopo B? parakalafa e mafai ai lenei filifiliga.
Filifili le Uati0, Uati1 po'o le Uati2 e fa'aaga ma fa'amaoti ai le fa'ailo o le uati ulufale mo le resitala fa'ailoga. E tatau ona e filifili le Resitala 'signb' input e mafai ai lenei parakalafa.
Fa'amaoti mai le puna manino asynchronous mo le resitala saini. E tatau ona e filifili le Resitala 'signb' input e mafai ai lenei parakalafa.
Fa'amaoti le puna manino fa'atasi mo le resitala saini. E tatau ona e filifili le Resitala 'signb' input e mafai ai lenei parakalafa.
Filifili le filifiliga lea e fa'aagaaga ai le resitara fa'aulu mo pasi fa'amatalaga.
Filifili le Uati0, Uati1 po'o le Uati2 e fa'aaga ma fa'amaoti ai le fa'ailoga o le uati ulufale mo fa'amaumauga o pasi fa'aulu. E tatau ona e filifili Resitala fa'aoga A o le fa'atele e fa'aagaaga ai lenei fa'ailoga.
Fa'amaoti mai le resitara fa'apogai manino asynchronous mo le pasi fa'aoga dataa. E tatau ona e filifili Resitala fa'aoga A o le fa'atele e fa'aagaaga ai lenei fa'ailoga.
Fa'amaoti mai le resitara fa'apogai manino fa'atasi mo le pasi fa'aoga fa'amaumauga. E tatau ona e filifili Resitala fa'aoga A o le fa'atele e fa'aagaaga ai lenei fa'ailoga.
Filifili le filifiliga lea e fa'aagaaga ai le resitara fa'aoga mo pasi fa'aoga datab.
Filifili le Uati0, Uati1 po'o le Uati2 e fa'aaga ma fa'amaoti ai le fa'ailoga uati fa'aulu mo le pasi fa'aoga datab. E tatau ona e filifili Resitala fa'aoga B o le fa'atele ina ia mafai ai lenei fa'ailoga.
Fa'amaoti mai le resitara fa'apogai manino le sa'o mo le pasi fa'aoga datab. E tatau ona e filifili Resitala fa'aoga B o le fa'atele ina ia mafai ai lenei fa'ailoga.
Fa'amaoti mai le resitara fa'apogai manino fa'atasi mo le pasi fa'aoga fa'amaumauga. E tatau ona e filifili Resitala fa'aoga B o le fa'atele ina ia mafai ai lenei fa'ailoga.
Filifili le puna fa'aoga mo fa'aoga A o le fa'atele.
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Parameter

IP Fausia Parameter

Taua

Scanout A Resitala Fa'atonuga

Resitala mea e maua mai le filifili su'esu'e

gui_scanouta luga

_resitala

Tape

O le a le fa'apogai mo le fa'aogaina o le uati?

gui_scanouta _register_clock k

Uati0 Uati1 Uati2

O le a le fa'apogai mo fa'aoga manino e le'i tutusa?

gui_scanouta _register_aclr

LEAI ACLR0 ACLR1

O le a le fa'apogai mo fa'aoga manino fa'atasi?

gui_scanouta _register_sclr

LEAI SCLR0 SCLR1

8.6.4. Preadder Tab

Laulau 33. Preadder Tab

Parameter

IP Fausia Parameter

Taua

Filifili le faiga preadder

preadder_mo de

FA'AFIO, COEF, INPUT, SQUARE, STATUS

Tau Fa'atonu

Fa'amatalaga
Filifili mea fa'aopoopo fa'atele e fa'aoga ai le pasi fa'amatalaga e fai ma puna i le fa'atele. Filifili Su'e filifili fa'aoga e fa'aoga ai le pasi fa'akomupiuta e fai ma fa'apogai i le fa'atele ma mafai ai le pasi fa'ata'ita'i. E avanoa lenei parakalafa pe a e filifilia le 2, 3 poʻo le 4 mo le O le a le numera o faʻateleina? fa'ata'oto.

Pepe le Uati0 LEAI LEAI

Filifili le filifiliga lea e mafai ai ona resitala galuega mo le scanouta output bus.
E tatau ona e filifilia Fa'ailoga filifili filifili mo O le a le fa'aoga A o le fa'atele e feso'ota'i i ai? parakalafa e mafai ai lenei filifiliga.
Filifili le Uati0, Uati1 po'o le Uati2 e fa'aaga ma fa'amaoti ai le fa'ailoga uati fa'aulu mo su'esu'ega pasi.
E tatau ona e fa'aolaina le Resitala o le fa'asologa o filifili filifili e mafai ai lenei filifiliga.
Fa'amaoti mai le resitara fa'apogai manino le sa'o mo le pasi fa'asolo.
E tatau ona e fa'aolaina le Resitala o le fa'asologa o filifili filifili e mafai ai lenei filifiliga.
Fa'amaoti mai le resitara fa'apogai manino fa'atasi mo le pasi fa'ato'aga scanouta.
E tatau ona e filifilia le Resitala mea e fai o le fa'ailoga filifili filifili e mafai ai lenei filifiliga.

Tau Fa'atonu
FA'AVAE

Fa'amatalaga
Fa'amaoti le faiga fa'agaioiga mo le fa'asologa o fa'asalalauga. FA'AFIAGA: Ole auala lea e pasi ai le preadder. O le tulaga masani lea. COEF: O lenei faiga e fa'aogaina ai le fa'aulufalega o le preadder ma le coefsel input pasi e fai ma fa'aoga i le fa'atele. INPUT: O lenei faiga e fa'aogaina ai le fa'aulufalega o le preadder ma le datac input pasi e fai ma fa'aoga i le fa'atele. SQUARE: O lenei faiga e fa'aogaina ai le mea e fai a le preadder e fai ma mea e lua i le fa'atele.
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Parameter

IP Fausia Parameter

Taua

Filifili le fa'atonuga a le faitalatala

gui_preadder ADD,

_ faasinoga

SUB

O le a le lautele e tatau ona iai i totonu o pasi C width_c?

1 – 256

Fa'amatalaga C Fa'atonu Tusi Resitala

Resitala fa'amatalaga fa'amatalaga

gui_datac_inp I luga

ut_resitala

Tape

O le a le fa'apogai mo le fa'aogaina o le uati?

gui_datac_inp ut_register_cl ock

Uati0 Uati1 Uati2

O le a le fa'apogai mo fa'aoga manino e le'i tutusa?

gui_datac_inp ut_register_a clr

LEAI ACLR0 ACLR1

O le a le fa'apogai mo fa'aoga manino fa'atasi?

gui_datac_inp ut_register_sc lr

LEAI SCLR0 SCLR1

Coefficients
O le a le lautele e tatau ona i ai le lautele o le coef?

width_coef

1 – 27

Coef Register Configuration

Resitala le fa'aoga coefsel

gui_coef_regi I luga

ster

Tape

O le a le fa'apogai mo le fa'aogaina o le uati?

gui_coef_regi ster_clock

Uati0 Uati1 Uati2

Tau Fa'atonu
FA'AFI
16

Fa'amatalaga
TATAU: O lenei faiga e fa'aogaina ai le pasi fa'aoga fa'atasi ma le pasi fa'aulu e pasi ma fa'aulu fa'atasi le pasi e fa'aoga i le fa'atele.
Fa'ama'oti le fa'agaioiga a le fa'asalalauga. Ina ia mafai ona fa'aogaina lenei parakalafa, filifili mea o lo'o i lalo mo Filifili le fa'asologa o talatala: · COEF · INPUT · SQUARE po'o le · FA'ATAU
Fa'ailoa mai le aofa'i o pusi mo le pasi ulufale C. E tatau ona e filifilia le INPUT mo le Filifili le fa'asologa o le fa'asalalauga e fa'aagaaga ai lenei parakalafa.

I le Uati0 LEAI LEAI

Filifili le filifiliga lea e fa'aagaaga ai le resitara fa'aulu mo pasi fa'aoga datac. E tatau ona e setiina le INPUT i le Filifili le fa'asologa o le fa'ata'ita'iga e mafai ai lenei filifiliga.
Filifili le Uati0, Uati1 po'o le Uati2 e fa'ailoa mai ai le fa'ailoga uati fa'aulu mo le resitara fa'amatalaga. E tatau ona e filifili Resitala datac input e mafai ai lenei parakalafa.
Fa'amaoti mai le puna manino asynchronous mo le resitara fa'amatalaga fa'amatalaga. E tatau ona e filifili Resitala datac input e mafai ai lenei parakalafa.
Fa'amaoti mai le puna manino fa'atasi mo le resitara fa'amatalaga fa'amatalaga. E tatau ona e filifili Resitala datac input e mafai ai lenei parakalafa.

Fa'ailoa mai le numera o bits mo

coefsel fa'aoga pasi.

E tatau ona e filifilia le COEF po'o le CONSTANT mo le fa'ata'ita'iga ala e mafai ai lenei parakalafa.

I le Uati0

Filifili le filifiliga lea e mafai ai ona resitala fa'aoga mo pasi fa'aoga coefsel. E tatau ona e filifilia le COEF po'o le CONSTANT mo le fa'ata'ita'iga ala e mafai ai lenei parakalafa.
Filifili le Uati0, Uati1 po'o le Uati2 e fa'ailoa mai ai le fa'ailo o le uati o lo'o tu'u i totonu mo le tusi resitala fa'aoga coefsel. E tatau ona e filifili Resitala le fa'aoga coefsel ina ia mafai ai lenei parakalafa.
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Parameter
O le a le fa'apogai mo fa'aoga manino e le'i tutusa?

IP Fausia Parameter

Taua

gui_coef_regi ster_aclr

LEAI ACLR0 ACLR1

O le a le fa'apogai mo fa'aoga manino fa'atasi

gui_coef_regi ster_sclr

LEAI SCLR0 SCLR1

Coefficient_0 Configuration

coef0_0 i le coef0_7

0x00000 0xFFFFFFFF

Coefficient_1 Configuration

coef1_0 i le coef1_7

0x00000 0xFFFFFFFF

Coefficient_2 Configuration

coef2_0 i le coef2_7

0x00000 0xFFFFFFFF

Coefficient_3 Configuration

coef3_0 i le coef3_7

0x00000 0xFFFFFFFF

8.6.5. Accumulator Tab

Fuafuaga 34. Accumulator Tab

Parameter

IP Fausia Parameter

Taua

Fa'aola le accumulator?

accumulator

IOE, LEAI

O le a le ituaiga gaioiga o le accumulator?

accum_directi ADD,

SUB

Fa'atatau Taua E LEAI
E LEAI
0x0000000 0
0x0000000 0
0x0000000 0
0x0000000 0

Fa'amatalaga
Fa'amaoti mai le puna manino asynchronous mo le resitara fa'aoga coefsel. E tatau ona e filifili Resitala le fa'aoga coefsel ina ia mafai ai lenei parakalafa.
Fa'amaoti mai le puna manino fa'atasi mo le tusi resitala fa'aoga coefsel. E tatau ona e filifili Resitala le fa'aoga coefsel ina ia mafai ai lenei parakalafa.
Fa'amaoti le tau fa'atatau mo lenei fa'atele muamua. Ole numera o bits e tatau ona tutusa e pei ona faʻamaonia ile O le a le lautele e tatau ona i ai le lautele o le coef? fa'ata'oto. E tatau ona e filifilia le COEF po'o le CONSTANT mo le fa'ata'ita'iga ala e mafai ai lenei parakalafa.
Fa'amaoti le tau fa'atatau mo lenei fa'atele lona lua. Ole numera o bits e tatau ona tutusa e pei ona faʻamaonia ile O le a le lautele e tatau ona i ai le lautele o le coef? fa'ata'oto. E tatau ona e filifilia le COEF po'o le CONSTANT mo le fa'ata'ita'iga ala e mafai ai lenei parakalafa.
Fa'amaoti le tau fa'atatau mo lenei fa'atele lona tolu. Ole numera o bits e tatau ona tutusa e pei ona faʻamaonia ile O le a le lautele e tatau ona i ai le lautele o le coef? fa'ata'oto. E tatau ona e filifilia le COEF po'o le CONSTANT mo le fa'ata'ita'iga ala e mafai ai lenei parakalafa.
Fa'amaoti le tau fa'atatau mo le fa'atele lenei. Ole numera o bits e tatau ona tutusa e pei ona faʻamaonia ile O le a le lautele e tatau ona i ai le lautele o le coef? fa'ata'oto. E tatau ona e filifilia le COEF po'o le CONSTANT mo le fa'ata'ita'iga ala e mafai ai lenei parakalafa.

Tau Fa'aletonu NO
FA'AFI

Fa'amatalaga
Filifili IOE ina ia mafai ai le fa'aputu. E tatau ona e filifilia le Resitala o galuega a le adder unit pe a fa'aogaina le fa'aputuga.
Fa'amaoti le fa'agaioiga o le fa'aputuga: · ADD mo le fa'aopoopoga o galuega · SUB mo le fa'agaioiga toese. E tatau ona e filifilia IOE mo Enable accumulator? parakalafa e mafai ai lenei filifiliga.
faaauau…

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Parameter
Mu'i uta Talosaga Fa'aaga pea muamua le uta

IP Fausia Parameter

Taua

gui_ena_prelo luga

ad_const

Tape

O le a le fa'aoga o le tau fa'aputu e feso'ota'i i ai?

gui_accumula ACCUM_SLOAD, te_port_select SLOAD_ACCUM

Filifili le tau mo le uta loadconst_val 0 – 64

tumau

O le a le fa'apogai mo le fa'aogaina o le uati?

gui_accum_sl oad_register_ uati

Uati0 Uati1 Uati2

O le a le fa'apogai mo fa'aoga manino e le'i tutusa?

gui_accum_sl oad_register_ aclr

LEAI ACLR0 ACLR1

O le a le fa'apogai mo fa'aoga manino fa'atasi?

gui_accum_sl oad_register_ sclr

LEAI SCLR0 SCLR1

Fa'aagaaga lua fa'aputu

gui_double_a I luga

fua

Tape

Tau Fa'atonu

Fa'amatalaga

Tape

Fa'aaga le accum_sload po'o

sload_accum faailoilo ma resitara mea e fai

e dynamically filifili le sao i le

fa'aputu.

A maualalo le accum_sload po'o le sload_accum, o le fa'ateleina mea e maua e fafaga i totonu o le accumulator.

A maualuga le accum_sload po'o le sload_accum, e fafaga i totonu o le accumulator se tagata e fa'atonuina muamua le uta.

E tatau ona e filifilia IOE mo Enable accumulator? parakalafa e mafai ai lenei filifiliga.

ACCUM_SL OAD

Fa'ailoa mai le amio a accum_sload/ sload_accum faailo.
ACCUM_SLOAD: Ave le accum_sload maualalo e uta ai le fa'aopoopo fa'aopoopo i le fa'aputu.
SLOAD_ACCUM: Avea le sload_accum maualuga e uta ai le fa'aopoopo fa'aopoopo i le fa'aputu.
E tatau ona e filifili Enable preload constant option e mafai ai lenei parakalafa.

Fa'ailoa le tau fa'atulagaina tumau.

O lenei tau e mafai ona avea ma 2N pe a N o le tau fa'atulagaina tumau.

Pe a N=64, o lona uiga o se zero tumau.

E tatau ona e filifili Enable preload constant option e mafai ai lenei parakalafa.

Uati0

Filifili le Uati0 , Uati1 po'o le Uati2 e fa'ailoa mai ai le fa'ailo o le uati ulufale mo le resitara accum_sload/sload_accum.
E tatau ona e filifili Enable preload constant option e mafai ai lenei parakalafa.

E LEAI

Fa'ailoa mai le puna manino asynchronous mo le resitara accum_sload/sload_accum.
E tatau ona e filifili Enable preload constant option e mafai ai lenei parakalafa.

E LEAI

Fa'ailoa mai le puna manino fa'atasi mo le resitara accum_sload/sload_accum.
E tatau ona e filifili Enable preload constant option e mafai ai lenei parakalafa.

Tape

Fa'aagaaga le resitara fa'aputu fa'alua.

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8.6.6. Systolic/Chainout Tab

Laulau 35. Systolic/Chainout Adder Tab

Parameter Fa'aaga mea fa'aopoopo filifili

IP Fausia Parameter

Taua

chainout_add IOE,

LEAI

O le a le ituaiga fa'aogaina o mea fa'apipi'i filifili?

chainout_add ADD,

er_direction

SUB

Fa'aaga le mea e tu'uina atu mo le fa'aopoopo filifili?

Port_negate

PORT_USED, PORT_UNUSED

Resitala 'te'e' fa'aoga? negate_regist er

LE RESISTA, UATI0, UATI1, UATI2, UATI3

O le a le fa'apogai mo fa'aoga manino e le'i tutusa?

negate_aclr

LEAI ACLR0 ACLR1

O le a le fa'apogai mo fa'aoga manino fa'atasi?

negate_sclr

LEAI SCLR0 SCLR1

Fa'atuai Systolic
Fa'aaga resitara fa'atuai systolic

gui_systolic_d On

elay

Tape

O le a le fa'apogai mo le fa'aogaina o le uati?

gui_systolic_d CLOCK0,

elay_clock

Uati1,

Tau Fa'atonu
LEAI

Fa'amatalaga
Filifili le IOE e fa'aagaaga ai le module fa'aopoopo fa'aulu.

FA'AFI

Fa'ama'oti le fa'agaioiga o mea fa'aopoopo e filifili ai.
Mo le fa'agaioiga toese, e tatau ona filifilia le SAINI mo O le a le fa'atusa fa'atusa mo mea fa'aopoopo A? ma O le a le fa'atusa fa'atusa mo mea fa'aopoopo B? i le Fa'atele Fa'asaga.

PORT_UN USED

Filifili PORT_USED e mafai ai ona fa'afitia le fa'ailoga fa'aoga.
E le aoga lenei fa'amaufa'ailoga pe a fa'aletonu le mea fa'apipi'i filifili.

LE'I RESISTA ERED

Ina ia mafai ai e le tusi resitala fa'aoga mo le fa'afitia o le fa'ailo fa'aulu ma fa'amaoti le fa'ailo o le uati ulufale mo le resitala fa'afiti.
Filifili UNREGISTERED pe afai e le mana'omia le resitalaina o mea e fa'aoga ai
E le aoga lenei parakalafa pe a e filifilia:
· LEAI mo le fa'aagaoioi le mea fa'aopoopo fa'atasi po'o
· PORT_UNUSED mo le Fa'aagaoioiga 'tia'e' fa'aoga mo le fa'aopoopo fa'alava? para'a po'o

E LEAI

Fa'amaoti mai le puna manino asynchronous mo le resitala fa'aletonu.
E le aoga lenei parakalafa pe a e filifilia:
· LEAI mo le fa'aagaoioi le mea fa'aopoopo fa'atasi po'o
· PORT_UNUSED mo le Fa'aagaoioiga 'tia'e' fa'aoga mo le fa'aopoopo fa'alava? para'a po'o

E LEAI

Fa'amaoti le puna manino fa'atasi mo le resitala fa'afiti.
E le aoga lenei parakalafa pe a e filifilia:
· LEAI mo le fa'aagaoioi le mea fa'aopoopo fa'atasi po'o
· PORT_UNUSED mo le Fa'aagaoioiga 'tia'e' fa'aoga mo le fa'aopoopo fa'alava? para'a po'o

Ta'e uati0

Filifili lenei filifiliga e mafai ai le systolic mode. E avanoa lenei parakalafa pe a e filifilia le 2, po'o le 4 mo le O le a le numera o fa'atele? fa'ata'oto. E tatau ona e fa'atagaina le fa'aulufalega o le Resitala a le iunite fa'aopoopo e fa'aoga ai tusi resitala fa'atuai.
Fa'ailoa mai le fa'ailo o le uati o lo'o fa'auluina mo le resitala fa'atuai o le systolic.
faaauau…

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Parameter

IP Fausia Parameter

Taua

Uati2,

O le a le fa'apogai mo fa'aoga manino e le'i tutusa?

gui_systolic_d elay_aclr

LEAI ACLR0 ACLR1

O le a le fa'apogai mo fa'aoga manino fa'atasi?

gui_systolic_d elay_sclr

LEAI SCLR0 SCLR1

Tau Fa'atonu
E LEAI
E LEAI

Fa'amatalaga
E tatau ona e filifili e mafai ona resitala le tuai o le systolic e mafai ai lenei filifiliga.
Fa'ama'oti mai le puna manino asynchronous mo le resitala fa'atuai systolic. E tatau ona e filifili e mafai ona resitala le tuai o le systolic e mafai ai lenei filifiliga.
Fa'amaoti mai le puna manino fa'atasi mo le resitala fa'atuai systolic. E tatau ona e filifili e mafai ona resitala le tuai o le systolic e mafai ai lenei filifiliga.

8.6.7. Pipeli Tab

Laulau 36. Pipelining Tab

Fa'atonuga o paipa Parameter

IP Fausia Parameter

Taua

Ete mana'o e fa'aopoopo le resitara o paipa ile fa'aoga?

gui_pipelining Leai, Ioe

Tau Fa'atonu
Leai

Fa'amolemole fa'ailoa mai le

taofiga

numera o le uati leo

taamilosaga

So'o se tau e sili atu ile 0 nai lo le 0

O le a le fa'apogai mo le fa'aogaina o le uati?

gui_input_late ncy_clock

Uati0, Uati1, Uati2

O le a le fa'apogai mo fa'aoga manino e le'i tutusa?

gui_input_late ncy_aclr

LEAI ACLR0 ACLR1

O le a le fa'apogai mo fa'aoga manino fa'atasi?

gui_input_late ncy_sclr

LEAI SCLR0 SCLR1

Uati0 LEAI LEAI

Fa'amatalaga
Filifili le Ioe ina ia mafai ai ona fa'aopoopo se tulaga fa'aopoopo o le resitara o paipa i fa'ailoga fa'aoga. E tatau ona e fa'ama'oti se tau e sili atu i le 0 mo Fa'amolemole fa'ailoa le numera o ta'amilosaga o le uati le tumau.
Fa'ama'oti le fa'agata mana'omia i ta'amilosaga o le uati. Tasi le tulaga o le resitara paipa = 1 latency i le taamilosaga uati. E tatau ona e filifilia le IOE mo E te mana'o e fa'aopoopo le resitara o paipa ile fa'aoga? ina ia mafai ai lenei filifiliga.
Filifili le Uati0, Uati1 po'o le Uati2 e fa'aaga ma fa'amaoti ai le fa'ailoga o le uati fa'aulu. E tatau ona e filifili IOE mo E te mana'o e fa'aopoopo le resitara paipa ile mea e tu'uina atu? e mafai ai lenei filifiliga.
Fa'ama'oti mai le resitara fa'apogai manino asynchronous mo le fa'aopoopo resitara paipa. E tatau ona e filifili IOE mo E te mana'o e fa'aopoopo le resitara paipa ile mea e tu'uina atu? e mafai ai lenei filifiliga.
Fa'ama'oti mai le tusi resitala fa'apogai manino mo le fa'aopoopoina o le resitara paipa. E tatau ona e filifili IOE mo E te mana'o e fa'aopoopo le resitara paipa ile mea e tu'uina atu? e mafai ai lenei filifiliga.

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683490 | 2020.10.05 Auina Manatu

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core

Fa'alogo:

Ua aveese e Intel le lagolago o lenei IP ile Intel Quartus Prime Pro Edition version 20.3. Afai o le IP autu i lau mamanu e taulaʻi masini i le Intel Quartus Prime Pro Edition, e mafai ona e suia le IP ile LPM_MULT Intel FPGA IP pe toe faʻatupu le IP ma faʻapipiʻi lau mamanu e faʻaaoga ai le polokalama Intel Quartus Prime Standard Edition.

O le ALTMEMMULT IP core e fa'aoga e fatu ai mea fa'atele e fa'atatau i le manatua e fa'aaoga ai poloka manatua o le onchip o lo'o maua ile Intel FPGAs (fa'atasi ai ma poloka manatua M512, M4K, M9K, ma MLAB). O lenei IP autu e aoga pe afai e le lava au punaoa e faʻatino ai faʻaopoopoga i elemene faʻapitoa (LEs) poʻo punaoa faʻapipiʻi faʻapitoa.
O le ALTMEMMULT IP core o se galuega fa'atasi e mana'omia ai se uati. O le ALTMEMMULT IP autu o lo'o fa'atinoina se fa'aopoopo fa'atasi ma le la'ititi la'ititi la'ititi ma le fa'agata e mafai mo se seti tu'ufa'atasiga ma fa'amatalaga.
O le ata o loʻo i lalo o loʻo faʻaalia ai ports mo le ALTMEMMULT IP core.

Ata 21. ALTMEMMULT Taulaga

ALTMEMMULT

data_in[] sload_data coeff_in[]

i'uga [] fa'ai'uga

sload_coeff

sclr uati
inst

Fa'amatalaga Fa'atatau ile itulau 71

9.1. Vaega
O le ALTMEMMULT IP autu o loʻo ofoina atu uiga nei: · Faia naʻo faʻateleina faʻapipiʻi manatua e faʻaaoga ai poloka manatua i luga ole masini o loʻo maua i totonu.
Intel FPGAs · Lagolagoina le lautele o faʻamatalaga o le 1 bits · Lagolagoina le sainia ma le le faʻamaonia le faʻatusaina o faʻamatalaga · Lagolago pipelining ma faʻamautu galuega le tumau

ISO 9001:2015 Resitala

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05
· Teuina le tele o mea faifai pea i le manatua avanoa (RAM)
· Tuuina atu se filifiliga e filifili le ituaiga poloka RAM
· Lagolago avanoa fa'akomepiuta manino ma fa'atonutonu uta fa'aoga
9.2. Verilog HDL Prototype
Ole Verilog HDL prototype o lo'o iai ile Verilog Design File (.v) altera_mf.v i le eda synthesis directory.
module altmemmult #( parameter coeff_representation = "SIGNED", parameter coefficient0 = "LE USED", parameter data_representation = "SIGNED", parameter intended_device_family = "le faʻaaogaina", parameter max_clock_cycles_per_result = 1, parameter numera_of_coefficients = 1, parameter ram_block_type = ram_block_type total_latency = 1, parameter width_c = 1, parameter width_d = 1, parameter width_r = 1, parameter width_s = 1, parameter lpm_type = “altmemmult”, parameter lpm_hint = “le faaaogaina”) ( uaea ulufale, uaea ulufale [width_c-1: 0]coeff_in, uaea ulufale [width_d-1:0] data_in, uaea galuega faatino load_done, uaea gaosiga [width_r-1:0] i'uga, uaea oloa gaosi taunuuga_vali, uaea ulufale sclr, uaea ulufale [width_s-1:0] sel, tuuina i totonu uaea sload_coeff, uaea ulufale sload_data)/* synthesis syn_black_box=1 */; endmodule
9.3. VHDL Fa'aaliga Vaega
O le ta'utinoga vaega VHDL o lo'o maua ile VHDL Design File (.vhd) altera_mf_components.vhd i le librariesvhdlaltera_mf directory.
vaega altmemmult generic ( coeff_representation: manoa : = "SAIGNED"; coefficient0: manoa : = "LE USED"; data_representation: manoa: = "SIGNED"; intended_device_family: manoa : = "le faʻaaogaina"; max_clock_cycles_per_result:natural:= 1; numera_of_coefficient : = 1 ; “altmemult”); uati (uati: i std_logic; coeff_in: i std_logic_vector(width_c-1 i lalo i le 1): = (isi => '0'); data_in: i std_logic_vector(width_d-0 downto 1);

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load_done:out std_logic; i'uga: fafo std_logic_vector(width_r-1 i lalo i le 0); result_valid:out std_logic; sclr:in std_logic := '0'; sel:i std_logic_vector(width_s-1 i lalo i le 0):= (isi => '0'); sload_coeff:i le std_logic := '0'; sload_data:in std_logic := '0'); vaega pito;

9.4. Taulaga

O siata o lo'o i lalo o lo'o lisiina ai ports o lo'o i totonu ma fa'aulufalega mo le ALTMEMMULT IP core.

Laulau 37. ALTMEMMULT Taulaga Ulufale

Igoa o le Taulaga

Manaomia

Fa'amatalaga

uati

Ioe

Fa'aoga uati i le fa'atele.

coeff_in[]

Leai

Coefficient uafu ulufale mo le faatele. Ole tele ole uafu fa'aoga e fa'alagolago ile tau ole parameter WIDTH_C.

data_i totonu []

Ioe

Tau fa'amatalaga tu'u i le fa'atele. Ole tele ole uafu fa'aoga e fa'alagolago ile tau ole parameter WIDTH_D.

sclr

Leai

Fa'aoga manino fa'atasi. Afai e le'o fa'aaogaina, o le tau fa'aletonu o lo'o galue maualuga.

filifili []

Leai

Filifiliga fa'amaumau. Ole tele ole uafu fa'aoga e fa'alagolago ile WIDTH_S

tau fa'ailoga.

sload_coeff

Leai

Fa'atasi le uta fa'aoga uafu. Suia le tau o le coefficient ua filifilia i le tau o lo'o fa'amaoti mai i totonu o le coeff_in input.

sload_data

Leai

Fa'asoa fa'amatalaga uta fa'aoga uafu. Fa'ailoga e fa'ailoa mai ai le fa'agaioiga fou ma fa'aleaogaina so'o se fa'agaioiga fa'atele o iai. Afai o le MAX_CLOCK_CYCLES_PER_RESULT parameter e 1 lona tau, e le amana'ia le sload_data input port.

Fuafuaga 38. ALTMEMMULT Taulaga o Galuega

Igoa o le Taulaga

Manaomia

Fa'amatalaga

i'uga[]

Ioe

Taulaga fa'atele. Ole tele ole uafu fa'aoga e fa'alagolago ile WIDTH_R parameter value.

taunuuga_vali

Ioe

Fa'ailoa mai pe a fa'apea o le fua fa'atatau o le taunu'uga aoga lea o se fa'atelega atoa. Afai o le MAX_CLOCK_CYCLES_PER_RESULT parameter e iai le tau o le 1, o le result_valid output port e le fa'aogaina.

uta_faia

Leai

Fa'ailoa ina ua uma le utaina o le coefficient fou. O le load_done signal e fa'ailoa mai pe a mae'a le utaina o se coefficient fou. Se'i vagana ua maualuga le faailo o le load_done, e leai se isi tau aofa'i e mafai ona utaina i le manatua.

9.5. Parakalafa

O le laulau o loʻo i lalo o loʻo lisiina ai faʻamaufaʻailoga mo le ALTMEMMULT IP core.

Laulau 39.
WIDTH_D WIDTH_C

ALTMEMMULT Parameter
Igoa Parameter

Ituaiga Manaomia

Fa'amatalaga

Integer Ioe

Fa'ailoa mai le lautele o le data_in[] port.

Integer Ioe

Fa'ailoa mai le lautele o le coeff_in[] uafu. faaauau…

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Igoa Parameter WIDTH_R WIDTH

Pepa / Punaoa

intel FPGA Integer Arithmetic IP Cores [pdf] Taiala mo Tagata Fa'aoga
FPGA Integer Arithmetic IP Cores, Integer Arithmetic IP Cores, Arithmetic IP Cores, IP Cores

Fa'asinomaga

Tusi Taiala

FPGA Integer Arithmetic IP Cores

Pepa / Punaoa

Fa'asinomaga

Tuu se faamatalaga

Fa'aleaogaina le tali