How to use Trigger Multiplexer in Traveo II Family

About this document

This application note describes the Trigger Multiplexer for the Traveo™ II Family and explains how to route trigger signals from source peripherals to their destinations.

Associated Part Family

Traveo II Family

Introduction

Every peripheral in the Traveo II device is interconnected using trigger signals. Trigger signals are means by which peripherals inform the occurrence of an event or transition to a different state. Trigger signals are used to initiate an action in other peripherals. For example, triggers can initiate data transfer over DMA (see section 3.1 Triggering P-DMA transfer by TCPWM timer), conversion on SAR ADC (see sections 3.2 Simultaneous ADC conversion on three SARs by single TCPWM timer and 3.3 Triggering ADC conversion by TCPWM timer), or start a timer (see section 3.4 Simultaneous starting of TCPWM timer by SW trigger). Trigger multiplexers are simple multiplexers designed to route these trigger signals from the source peripherals to the desired destinations.

In this application note, you will learn how to set up trigger routes from the source peripherals to the desired destinations.

To know more about the functionality and terminology used in this application note, see the "Trigger Multiplexer" chapter of the Architecture Technical Reference Manual (TRM).

Trigger multiplexer overview

The trigger inputs are output signals from the source peripheral. The trigger outputs are typically input signals to the destination peripheral. The trigger multiplexer multiplexes trigger input and trigger output.

Trigger multiplexer has two group types:

• Multiplexer-based group type (Group trigger): Connects a peripheral input trigger to multiple peripheral output triggers.
• One-to-one-based group type (One-to-one trigger): Connects a peripheral input trigger to a specific output trigger.

Each group type consists of multiple trigger groups (up to 16). Each group type is associated with the trigger inputs of a specific peripheral. The following diagram illustrates the trigger multiplexer block diagram:

Figure 1: Trigger multiplexer block diagram

Diagram Description: A block labeled "Trigger Multiplexer" has two main paths. The upper path is for "Group Trigger" (up to 16 groups), taking input TRIG_IN_MUX_x (up to 256 inputs) and producing output TRIG_OUT_MUX_x (up to 256 outputs). The lower path is for "One-to-one Trigger" (up to 16 groups), taking input TRIG_IN_1TO1_x (up to 256 inputs) and producing output TRIG_OUT_1TO1_x (up to 256 outputs). Below the main block, "Software (SW) Trigger", "Inverted Output", and "Level/Edge Output" are indicated as potential control signals.

Trigger multiplexer has the following input and output signals:

• TRIG_IN_MUX_x is the input trigger of group trigger, with up to 256 input signals.
• TRIG_IN_1TO1_x is the input trigger of one-to-one trigger, with up to 256 input signals.
• TRIG_OUT_MUX_x is the output trigger of group trigger, with up to 256 output signals.
• TRIG_OUT_1TO1_x is the output trigger of one-to-one trigger, with up to 256 output signals.

Trigger multiplexer features SW trigger, inverted output trigger, and level or edge sensitive trigger. SW trigger is initiated by SW and can trigger any signal in the trigger multiplexer. Inverted output specifies the polarity of output signals. Level or edge trigger specifies if the output trigger is treated as a level sensitive or edge sensitive trigger.

The suffix "x" represents the name of the peripheral block. Table 1 shows the output triggers and the input triggers of a group trigger that can be routed to each other, and the availability of routing in the Traveo II device series. However, some combinations cannot be routed to some unit and channel numbers. For details on the units and channels of each peripheral, see the datasheets.

Table 1: Routing between output trigger and input trigger of group trigger by series

Table 1 (Continued): Routing between output trigger and input trigger of group trigger by series

Table 2: Trigger outputs of MUX Group 5 of CYT2B7 series

Table 3: Trigger inputs of MUX Group 5 of CYT2B7 series

Table 3 (Continued): Trigger inputs of MUX Group 5 of CYT2B7 series

Figure 3 shows the input trigger and output trigger structure.

Figure 3: Trigger routing between 16-bit TCPWM and P-DMA0 of CYT2B7 series

Diagram Description: This figure illustrates the connection between input triggers and output triggers for a specific group. Input triggers, identified by "j" (e.g., PDMA0_TR_OUT[0:15] mapped to j=1:16), are shown on the left. Output triggers, identified by "k" (e.g., TCPWM: TCPWM_ALL_CNT_TR_IN[16] mapped to k=0), are shown on the right. Arrows connect specific input trigger ranges to specific output trigger numbers within Group i=5. For example, input triggers 1:16 connect to output triggers 0 through 4, and input triggers 41:72 connect to output triggers 32 through 63.

The following explains how to connect P-DMA0 channel 9 and 16-bit TCPWM channel 0:

1. Configuration register selection: MUX Group 5 (i=5). Output trigger TCPWM_ALL_CNT_TR_IN[16] (k=0). Therefore, the register is specified as PERI_TR_GR5_TR_CTL0.
2. Input trigger selection: Input trigger SCB_RX_TR_OUT[0] (j=74). The configuration will be PERI_TR_GR5_TR_CTL0.TR_SEL = 74.

Example 2:

Activation of SAR ADC unit, on ADC channel, can be triggered by Event Generator. Generic trigger inputs are shared between ADC channels. One of the five generic triggers can be routed to any ADC channel. Group trigger for SAR ADC typically specializes in trigger control of multiple SAR ADC units. One-to-one trigger for SAR ADC is typically useful for trigger control of ADC logical channels within a SAR ADC unit. For more details on SAR ADC generic trigger inputs, see the "SAR ADC" chapter of the Architecture TRM.

For example, in CYT2B7 series, the input trigger Event Generator 0 is routed to a generic trigger 0 of SAR. This trigger routing is included in MUX Group 6. This example is based on Table 4 and Table 5 extracted from CYT2B7 series datasheet that provides trigger group, input trigger, and output trigger.

Table 4: Trigger outputs of MUX Group 6 of CYT2B7 series

Table 5: Trigger inputs of MUX Group 6 of CYT2B7 series

For the Trigger Group Inputs and Trigger Group Outputs tables of each series, see the device datasheets.

Figure 4 shows the input trigger and output trigger structure.

Figure 4: Trigger routing between TCPWM 16-bit Motor and Generic Trigger 2 in ADC of CYT2B7 series

Diagram Description: This figure illustrates the routing of triggers for SAR ADC conversion. Input triggers (e.g., PDMA0_TR_OUT[0:15] mapped to j=1:16) are shown on the left. Output triggers (e.g., PASS_GEN_TR_IN[0] mapped to k=0) are shown on the right, connecting to SAR ADC generic triggers. Within Group i=6, specific input triggers are routed to output triggers that feed into GENERIC TRIGGER 0, 1, 2, 3, and 4. For instance, input trigger EVTGEN_TR_OUT[0] (j=23) is routed to output trigger PASS_GEN_TR_IN[0] (k=0), which connects to GENERIC TRIGGER 0.

The following explains how the trigger source Event Generator 0 is routed to a generic trigger 0 of SAR0:

1. Configuration register selection: MUX Group 6 (i=6). Output trigger PASS_GEN_TR_IN[0] (k=0). Therefore, the register is specified as PERI_TR_GR6_TR_CTL0.
2. Input trigger selection: Input trigger EVTGEN_TR_OUT[0] (j=23). The configuration will be PERI_TR_GR6_TR_CTL0.TR_SEL = 23.
3. Generic trigger selection: Generic trigger SAR_TR_IN_SEL0.IN0_SEL = 0.

Table 6 shows the bit registers for a group trigger that explains the inverted output trigger and the level or edge sensitive trigger. For more details, see the Registers TRM.

Table 6: Group trigger control bit registers

2.2 One-to-one trigger

For a one-to-one trigger, an input trigger, TRIG_IN_1TO1_x, is connected to the output trigger TRIG_OUT_1TO1_x. A one-to-one group has AND gate functionality to disable an input trigger. Figure 5 shows the one-to-one trigger block diagram.

Figure 5: One-to-one trigger

Diagram Description: A block labeled "Trigger Multiplexer" shows an "Input Trigger k" entering a "SW Input Trigger Qualification" stage, followed by a "Trigger Manipulation" stage, and finally an "Output Trigger k". Control signals like "SW Trigger", "PERI_TR_GR[i]_TR_CTL[k].TR_SEL", "PERI_TR_GR[i]_TR_CTL[k].TR_EDGE", and "PERI_TR_GR[i]_TR_CTL[k].TR_INV" are indicated.

One-to-one group trigger can be specified by the PERI_TR_1TO1_GR[i]_TR_CTL[k] register. Here, suffices "i" and "k" indicate the trigger group number and the output trigger number, respectively.

PERI_TR_1TO1_GR[i]_TR_CTL[k].TR_SEL is used to control the enabling/disabling of input trigger. If set to '1', the input trigger is enabled. If set to '0', the input trigger is disabled and set to constant signal level '0'.

This section describes an example of one-to-one trigger.

Example:

This is an example to trigger data transmission on P-DMA1 channel 15 by SCB UART channel 3. This trigger routing is included in MUX Group 8. The example is based on Table 7 extracted from the CYT2B7 series datasheet that provides trigger group and input trigger.

Table 7: Trigger one-to-one MUX Group 8 of CYT2B7 series

For the Trigger One-to-One table of each series, see the device datasheets.

The following describes how to connect SCB channel 3 to P-DMA1 channel 15. Note that in a one-to-one group trigger, one input trigger is directly connected to a specific output trigger. Thus, specifying only the input trigger number is sufficient to indicate its output trigger.

1. Configuration register selection: MUX Group 8 (i=8). Input trigger SCB3_RX_TR_OUT, which directly connects to output trigger PDMA1_TR_IN[15] (k=7). Therefore, the register is specified as PERI_TR_1TO1_GR8_TR_CTL7.
2. Input trigger configuration: Typically, input trigger of one-to-one trigger is enabled. The configuration will be PERI_TR_1TO1_GR8_TR_CTL7.TR_SEL = 1.

Table 8 shows the bit registers for one-to-one trigger that explains the inverted output trigger and the level or edge sensitive trigger. For more details, see the Registers TRM.

Table 8: Group trigger control bit registers

2.3 Software trigger

Each group supports a software trigger. For a group trigger, either an input trigger or output trigger can be selected for SW trigger. For one-to-one trigger, an output trigger can be selected for SW trigger. Figure 6 shows the group trigger with SW trigger block diagram. Figure 7 shows the one-to-one trigger with SW trigger block diagram.

Figure 6: SW trigger in group trigger

Diagram Description: A block shows an "Input Trigger j" feeding into "SW Input Trigger Qualification", then "SW Output Trigger Qualification", and finally an "Output Trigger k". Control signals are shown: PERI_TR_CMD.ACTIVATE, PERI_TR_CMD.GROUP_SEL, PERI_TR_CMD.TR_SEL, PERI_TR_CMD.TR_EDGE, and PERI_TR_CMD.TR_OUT_SEL. A path from PERI_TR_GR[i]_TR_CTL[k].TR_SEL is also shown feeding into the SW Output Trigger Qualification.

Figure 7: SW trigger in one-to-one trigger

Diagram Description: A block shows an "Input Trigger k" feeding into "SW Output Trigger Qualification", then "Trigger Manipulation", and finally an "Output Trigger k". Control signals are shown: PERI_TR_CMD.ACTIVATE, PERI_TR_CMD.GROUP_SEL, PERI_TR_CMD.TR_SEL, and PERI_TR_CMD.TR_EDGE.

The activation of a trigger through software can be made via PERI_TR_CMD. This register is useful for SW initiated triggers or for debugging purposes. For group trigger, to specify an activated trigger as input trigger (=j) or output trigger (=k), configure PERI_TR_CMD.OUT_SEL. If set to '0', input trigger is selected. If set to '1', output trigger is selected. Note that this configuration is not used for one-to-one trigger. The activated trigger number can be specified by PERI_TR_CMD.TR_SEL=j or k. The trigger group number can be specified by PERI_TR_CMD.GROUP_SEL=i. The level or edge sensitive trigger of the activated trigger can be specified by PERI_TR_CMD.TR_EDGE. PERI_TR_CMD.ACTIVATE can be set to '1' to activate a trigger. PERI_TR_CMD.ACTIVATE cannot be set together with the other PERI_TR_CMD field. This section describes an example of software trigger.

Example:

This is an example to trigger data transfer on P-DMA0 channel 0. This trigger routing is included in MUX Group 0 of group trigger and specifies the output trigger as the activated trigger. Table 9 lists the values that need to be set for PERI_TR_CMD.GROUP_SEL (=i) and PERI_TR_CMD.TR_SEL (=k). Table 9, extracted from the CYT2B7 series datasheet, provides trigger group and output trigger.

Table 9: Trigger outputs of MUX Group 0 of CYT2B7 series

For the Trigger Group Outputs table of each series, see the device datasheets.

Figure 8 shows the trigger of data transfer on P-DMA0 by SW.

Figure 8: P-DMA0 data transfer start by SW

Diagram Description: This figure shows a software-triggered data transfer. An "Input Trigger j" feeds into "SW Input Trigger Qualification", then "SW Output Trigger Qualification", and finally an "Output Trigger k" (PDMA0_TR_IN[0]). Control signals are shown: PERI_TR_CMD.ACTIVATE, PERI_TR_CMD.GROUP_SEL = 0, PERI_TR_CMD.TR_SEL = 0, PERI_TR_CMD.TR_EDGE = 1, and PERI_TR_CMD.TR_OUT_SEL = 1.

The following describes how to initiate data transfer on P-DMA0:

1. Activated trigger selection: PERI_TR_CMD.TR_SEL = 0: Output trigger PDMA0_TR_IN[0] (k=0). PERI_TR_CMD.GROUP_SEL = 0: MUX Group 0 of group trigger (i=0). PERI_TR_CMD.TR_EDGE = 1: Edge sensitive trigger.
2. Specifying activated trigger: PERI_TR_CMD.OUT_SEL = 1: Output trigger.
3. Activate SW trigger: PERI_TR_CMD.ACTIVATE = 1.

For details on Trigger Group Inputs and Trigger Group Outputs of each series, see the device datasheets.

Application

This section describes the following use cases for group trigger, one-to-one trigger, and SW trigger:

• Triggering P-DMA transfer by TCPWM timer: Group trigger use case
• Simultaneous ADC conversion on three SARs by single TCPWM timer: Group trigger use case
• Triggering ADC conversion by TCPWM timer: One-to-one trigger use case
• Simultaneous starting of TCPWM timer by SW trigger: SW trigger use case

3.1 Triggering P-DMA transfer by TCPWM timer

This section explains how an input trigger in a group trigger initiates data transfer of a P-DMA0 channel.

3.1.1 Use case description of triggering P-DMA transfer by TCPWM timer

Figure 9 shows an example application for group trigger in CYT2B7 series. Data transfer of P-DMA0 channel 9 is triggered by TCPWM 16-bit channel 0 on group trigger Multiplexer Group 3. TCPWM counter overflow event triggers P-DMA0 channel 9 to start its data transfer from the SRAM source buffer to the SRAM destination buffer. Figure 10 demonstrates the operation. For more details on TCPWM and DMA Components, see the "TCPWM" and "Direct Memory Access" chapters of the Architecture TRM.

Figure 9: Example of group trigger in CYT2B7 series

Diagram Description: A block diagram shows a TCPWM#0 (16-bit) timer configured for overflow. Its output is connected to a Trigger Multiplexer (MUX Group 3), which routes it to P-DMA0 channel 9. The connection is specified by PERI_TR_GR3_TR_CTL1.

Figure 10: Example operation: Triggering P-DMA transfer by TCPWM counter overflow

Diagram Description: This figure illustrates the operation of triggering P-DMA transfer. A TCPWM#0 (16-bit) timer generates overflow events. Each overflow event enables DMA transfer of 8 bytes.

Triggers must be set to implement this application. Figure 11 describes the procedure for setting the trigger. Figure 11 also provides the setting for TCPWM counter and P-DMA0 channel.

Figure 11: Example of setting for group trigger in CYT2B7 series

Diagram Description: A flowchart outlines the steps to configure a group trigger for P-DMA transfer. Steps include disabling and configuring P-DMA0, disabling and configuring TCPWM#0, configuring the group trigger (selecting output and input triggers, invert, edge sensitivity), enabling TCPWM#0, and triggering a SW start on TCPWM#0.

The configuration for output trigger and input trigger for group trigger in Step (7) are described as follows.

Trigger Multiplexer Setting

Table 10 and Table 11 list the values to be set. These tables are extracted from the CYT2B7 series datasheet that provides trigger group, input trigger, and output trigger.

Table 10: Trigger outputs of MUX Group 3 of CYT2B7 series

Table 11: Trigger inputs of MUX Group 3 of CYT2B7 series

Figure 12 shows the input trigger and output trigger structure.

Figure 12: Trigger routing between 16-bit TCPWM and P-DMA0 of CYT2B7 series

Diagram Description: This figure shows the routing of triggers from TCPWM counters to P-DMA0. Input triggers from TCPWM (e.g., TCPWM_32_TR_OUT0[0:3] mapped to j=1:4) are on the left. Output triggers to P-DMA0 (e.g., PDMA0_TR_IN[8] mapped to k=0) are on the right. Within Group i=3, specific TCPWM outputs are connected to P-DMA0 inputs. For example, TCPWM_16_TR_OUT0[0] (j=17) connects to PDMA0_TR_IN[9] (k=1).

The following explains how to connect P-DMA0 channel 9 and 16-bit TCPWM channel 0:

1. Configuration register selection: MUX Group 3 (i=3). Output trigger PDMA0_TR_IN[9] (k=1). Therefore, the register is specified as PERI_TR_GR3_TR_CTL1.
2. Input trigger selection: Input trigger TCPWM_16_TR_OUT0[0] (j=17). The configuration will be PERI_TR_GR3_TR_CTL1.TR_SEL = 17. It is necessary to refer to Trigger Multiplexer diagram of each series to make sure the correct multiplexer group and accurate input and output trigger are selected. To find the trigger setting of group trigger of another MUX group and another series, see the device datasheets.

3.1.2 Example program for triggering P-DMA transfer by TCPWM timer

Code Listing 1 shows the example program for Figure 11. The code snippets in this application note are part of the Sample Driver Library (SDL). See Other References for the SDL.

Code Listing 1: Example for triggering P-DMA transfer by TCPWM timer

void Cy_PDMA_Disable(volatile stc_DW_t *pstcPDMA)
{
    pstcPDMA->unCTL.stcField.u1ENABLED = 0;
}

cy_en_pdma_status_t Cy_PDMA_Descr_Init(cy_stc_pdma_descr_t* descriptor, const cy_stc_pdma_descr_config_t* config)
{
    cy_en_pdma_status_t retVal = CY_PDMA_ERR_UNC;

    if ((descriptor != NULL) && (config != NULL))
    {
        descriptor->unPDMA_DESCR_CTL.stcField.u2WAIT_FOR_DEACT = config->deact;
        descriptor->unPDMA_DESCR_CTL.stcField.u2INTR_TYPE = config->intrType;
        descriptor->unPDMA_DESCR_CTL.stcField.u2TR_OUT_TYPE = config->trigoutType;
        descriptor->unPDMA_DESCR_CTL.stcField.u2TR_IN_TYPE = config->triginType;
        descriptor->unPDMA_DESCR_CTL.stcField.u1SRC_TRANSFER_SIZE = config->srcTxfrSize;
        descriptor->unPDMA_DESCR_CTL.stcField.u1DST_TRANSFER_SIZE = config->destTxfrSize;
        descriptor->unPDMA_DESCR_CTL.stcField.u1CH_DISABLE = config->chStateAtCmplt;
        descriptor->unPDMA_DESCR_CTL.stcField.u2DATA_SIZE = config->dataSize;
        descriptor->unPDMA_DESCR_CTL.stcField.u2DESCR_TYPE = config->descrType;
        descriptor->u32PDMA_DESCR_SRC = (uint32_t)config->srcAddr;
        descriptor->u32PDMA_DESCR_DST = (uint32_t)config->destAddr;

        switch(config->descrType)
        {
            case (uint32_t)CY_PDMA_1D_TRANSFER:
            {
                descriptor->unPDMA_DESCR_X_CTL.stcField.u12SRC_X_INCR = (uint32_t)config->srcXincr;
                descriptor->unPDMA_DESCR_X_CTL.stcField.u12DST_X_INCR = (uint32_t)config->destXincr;
                descriptor->unPDMA_DESCR_X_CTL.stcField.u8X_COUNT = (uint32_t)((config->xCount) - 1u);
                descriptor->unPDMA_DESCR_Y_CTL.u32Register = (uint32_t)config->descrNext;
                break;
            }
        }
    }
    retVal = CY_PDMA_SUCCESS;
    return retVal;
}

cy_en_pdma_status_t Cy_PDMA_Chnl_Init(volatile stc_DW_t *pstcPDMA, uint32_t chNum, const cy_stc_pdma_chnl_config_t* chnlConfig)
{
    cy_en_pdma_status_t retVal = CY_PDMA_ERR_UNC;

    if ((pstcPDMA != NULL) && (chnlConfig != NULL))
    {
        /* Set current descriptor */
        pstcPDMA->CH_STRUCT[chNum].unCH_CURR_PTR.u32Register = (uint32_t)chnlConfig->PDMA_Descriptor;
        /* Set if the channel is preemtable */
        pstcPDMA->CH_STRUCT[chNum].unCH_CTL.stcField.u1PREEMPTABLE = chnlConfig->preemptable;
        /* Set channel priority */
        pstcPDMA->CH_STRUCT[chNum].unCH_CTL.stcField.u2PRIO = chnlConfig->priority;
        /* Set enabled status */
        pstcPDMA->CH_STRUCT[chNum].unCH_CTL.stcField.u1ENABLED = chnlConfig->enable;

        retVal = CY_PDMA_SUCCESS;
    }
    return (retVal);
}

void Cy_PDMA_Enable(volatile stc_DW_t *pstcPDMA)
{
    pstcPDMA->unCTL.stcField.u1ENABLED = 1;
}

void Cy_Tcpwm_Counter_Disable(volatile stc_TCPWM_GRP_CNT_t *ptscTCPWM)
{
    ptscTCPWM->unCTRL.stcField.u1ENABLED = 0x00;
}

uint32_t Cy_Tcpwm_Counter_Init(volatile stc_TCPWM_GRP_CNT_t *ptscTCPWM, cy_stc_tcpwm_counter_config_t const *config)
{
    uint32_t status = CY_RET_BAD_PARAM;

    if ((NULL != ptscTCPWM) && (NULL != config))
    {
        ptscTCPWM->unCTRL.stcField.u1ONE_SHOT = config->runMode;
        ptscTCPWM->unCTRL.stcField.u2UP_DOWN_MODE = config->countDirection;
        ptscTCPWM->unCTRL.stcField.u3MODE = config->CompareOrCapture;
        ptscTCPWM->unCTRL.stcField.u1DBG_FREEZE_EN = config->debug_pause;
        ptscTCPWM->unCTRL.stcField.u1AUTO_RELOAD_CC0 = config->enableCompare0Swap;
        ptscTCPWM->unDT.stcField.u8DT_LINE_OUT_L = config->clockPrescaler;

        if (CY_TCPWM_COUNTER_COUNT_UP == config->runMode)
        {
            ptscTCPWM->unCOUNTER.u32Register = CY_TCPWM_CNT_UP_INIT_VAL;
        }

        ptscTCPWM->unCC0.u32Register = config->compare0;
        ptscTCPWM->unCC0_BUFF.u32Register = config->compare0_buff;
        ptscTCPWM->unPERIOD.u32Register = config->period;
        ptscTCPWM->unTR_IN_SEL0.stcField.u8CAPTURE0_SEL = config->capture0Input;
        ptscTCPWM->unTR_IN_SEL0.stcField.u8RELOAD_SEL = config->reloadInput;
        ptscTCPWM->unTR_IN_SEL0.stcField.u8STOP_SEL = config->stopInput;
        ptscTCPWM->unTR_IN_SEL0.stcField.u8COUNT_SEL = config->countInput;
        ptscTCPWM->unTR_IN_SEL1.stcField.u8START_SEL = config->startInput;
        ptscTCPWM->unTR_IN_EDGE_SEL.stcField.u2CAPTURE0_EDGE = config->capture0InputMode;
        ptscTCPWM->unTR_IN_EDGE_SEL.stcField.u2RELOAD_EDGE = config->reloadInputMode;
        ptscTCPWM->unTR_IN_EDGE_SEL.stcField.u2START_EDGE = config->startInputMode;
        ptscTCPWM->unTR_IN_EDGE_SEL.stcField.u2STOP_EDGE = config->stopInputMode;
        ptscTCPWM->unTR_IN_EDGE_SEL.stcField.u2COUNT_EDGE = config->countInputMode;
        ptscTCPWM->unTR_OUT_SEL.stcField.u3OUT0 = config->trigger1;
        ptscTCPWM->unTR_OUT_SEL.stcField.u3OUT1 = config->trigger2;
        ptscTCPWM->unINTR_MASK.u32Register = config->interruptSources;
        ptscTCPWM->unCTRL.stcField.u1AUTO_RELOAD_CC1 = config->enableCompare1Swap;
        ptscTCPWM->unCC1.u32Register = config->compare1;
        ptscTCPWM->unCC1_BUFF.u32Register = config->compare1_buff;
        ptscTCPWM->unTR_IN_SEL1.stcField.u8CAPTURE1_SEL = config->capture1Input;
        ptscTCPWM->unTR_IN_EDGE_SEL.stcField.u2CAPTURE1_EDGE = config->capture1InputMode;

        status = CY_RET_SUCCESS;
    }
    return(status);
}

cy_en_trigmux_status_t Cy_TrigMux_Connect(uint32_t inTrig, uint32_t outTrig, uint32_t invert, en_trig_type_t trigType,
                                            uint32_t dbg_frz_en)
{
    volatile stc_PERI_TR_GR_TR_CTL_field_t* pTR_CTL;
    cy_en_trigmux_status_t retVal = CY_TRIGMUX_BAD_PARAM;

    if ((inTrig & CY_TR_GROUP_MASK) == (outTrig & CY_TR_GROUP_MASK))
    {
        pTR_CTL = &(PERI->TR_GR[(outTrig & CY_TR_GROUP_MASK) >> CY_TR_GROUP_SHIFT].unTR_CTL[outTrig & CY_TR_MASK].stcField); //Select output trigger TRIG_OUT_MUX_3_PDMA0_TR_IN9
        pTR_CTL->u8TR_SEL = inTrig; //Select input trigger TRIG_IN_MUX_3_TCPWM_16_TR_OUT00
        pTR_CTL->u1TR_INV = invert; //Invert input trigger
        pTR_CTL->u1TR_EDGE = trigType; //Select edge sensitive trigger as output trigger type
        retVal = CY_TRIGMUX_SUCCESS;
    }
    return retVal;
}

void Cy_Tcpwm_Counter_Enable(volatile stc_TCPWM_GRP_CNT_t *ptscTCPWM)
{
    ptscTCPWM->unCTRL.stcField.u1ENABLED = 0x1;
}

void Cy_Tcpwm_TriggerStart(volatile stc_TCPWM_GRP_CNT_t *ptscTCPWM)
{
    ptscTCPWM->unTR_CMD.stcField.u1START = 0x01;
}

3.2 Simultaneous ADC conversion on three SARs by single TCPWM timer

This section explains how an input trigger in a group trigger initiates ADC channel conversion on three SAR units.

3.2.1 Use case description of simultaneous ADC conversion on three SARs by single TCPWM timer

Activation of multiple SAR ADC units, on ADC channel, can be triggered simultaneously by a single TCPWM timer. Generic trigger inputs are shared between ADC channels. One of the five generic triggers can be routed to any ADC channel. Figure 13 shows an example application in which ADC channel conversion of SAR0, SAR1, and SAR2 are triggered by TCPWM 16-bit Motor Control counter on group trigger Multiplexer Group 6. Compare match 0 on TCPWM counter generates a trigger to SAR ADC, which is connected to the generic triggers. The generic triggers are routed to ADC channel 3 of SAR0, SAR1, and SAR2, which initiates the simultaneous conversion.

Figure 14 demonstrates the operation. For more details on TCPWM and SAR ADC, see the "TCPWM" and "SAR ADC" chapters of the Architecture TRM.

Figure 13: Example of group trigger and ADC generic trigger input in CYT2B7 series

Diagram Description: A block diagram shows a TCPWM#1 (16-bit for Motor) timer with CC0 match output connected to a Trigger Multiplexer (MUX Group 6). The multiplexer routes this to PASS_GEN_TR_IN[1], which connects to SAR ADC2, SAR ADC1, and SAR ADC0 via generic triggers. Each SAR ADC channel 3 is shown receiving a trigger, leading to an ADC Core and ADC Result Register.

Figure 14: Example operation: Simultaneous ADC conversion on three SARs by single TCPWM timer

Diagram Description: This figure illustrates the simultaneous ADC conversion process. Three SAR units (SAR0, SAR1, SAR2) are shown. Each SAR unit has an ADC Core and ADC Result Register. An ADC trigger is sent to channel 3 of each SAR unit. This trigger originates from a TCPWM#1 (16-bit for Motor) timer's CC0 match output.

Triggers must be set to implement this application. Figure 15 demonstrates the procedure for setting the trigger.

Figure 15: Setting for ADC generic trigger input and group trigger in CYT2B7 series

Diagram Description: A flowchart outlines the steps for configuring ADC generic trigger input and group trigger. Steps include disabling TCPWM#1, configuring SAR structure, configuring generic trigger input selection, configuring the group trigger (output, input, invert, edge sensitivity), configuring SAR channel 3, enabling SAR channel 3, configuring TCPWM#1 for timer mode, configuring output trigger selection for TCPWM#1, setting compare values for TCPWM#1, enabling TCPWM#1, and triggering a SW start on TCPWM#1.

The configuration for the output trigger and input trigger for a group trigger in Step (4) are described as follows.

Trigger Multiplexer Setting

Table 12 and Table 13 list the values to be set. These tables are extracted from the CYT2B7 series datasheet that provides trigger group, input trigger, and output trigger.

Table 12: Trigger outputs of MUX Group 6 of CYT2B7 series

Table 13: Trigger inputs of MUX Group 6 of CYT2B7 series

Figure 16 shows the input trigger and output trigger structure.

Figure 16: Trigger routing between TCPWM 16-bit motor and generic trigger 2 in SAR0 unit of CYT2B7 series

Diagram Description: This figure illustrates the trigger routing for SAR ADC conversion. Input triggers from TCPWM and other peripherals are listed on the left (e.g., PDMA0_TR_OUT[0:15] mapped to j=1:16). Output triggers, PASS_GEN_TR_IN[0:11] mapped to k=0:11, are shown connecting to SAR0. Within Group i=6, various input triggers are routed to specific output triggers that feed into GENERIC TRIGGER 0, 1, 2, 3, and 4. For example, TCPWM_16M_TR_OUT1[1] (j=69) is routed to PASS_GEN_TR_IN[8] (k=8), which connects to GENERIC TRIGGER 2.

The following explains how the trigger source TCPWM 16-bit Motor Control counter is routed to a generic trigger 2 of each SAR:

1. Configuration register selection: MUX Group 6 (i=6). Output trigger, generic trigger 8 or PASS_GEN_TR_IN[8] (k=8). Therefore, the register is specified as PERI_TR_GR6_TR_CTL8.
2. Input trigger selection: Input trigger TCPWM_16M_TR_OUT1[1] (j=69). The configuration will be PERI_TR_GR6_TR_CTL8.TR_SEL = 69.
3. Generic trigger 8 is forwarded to SAR generic trigger input 2, IN2 of the corresponding SAR unit:
   • For SAR0, the configuration will be SAR_TR_IN_SEL0.IN2_SEL = 8
   • For SAR1, the configuration will be SAR_TR_IN_SEL1.IN2_SEL = 8
   • For SAR2, the configuration will be SAR_TR_IN_SEL2.IN2_SEL = 8
4. IN2 triggers channel 3 of the corresponding SAR unit:
   • For SAR0, the configuration for SAR trigger select will be PASS0_SAR0_CH3_TR_CTL.SEL = 4 (This value represents SAR Generic trigger input 2)
   • For SAR1, the configuration for SAR trigger select will be PASS0_SAR1_CH3_TR_CTL.SEL = 4
   • For SAR2, the configuration for SAR trigger select will be PASS0_SAR2_CH3_TR_CTL.SEL = 4

To find the trigger setting of the group trigger, see the device datasheets.

3.2.2 Example program for simultaneous ADC conversion on three SARs by single TCPWM timer

Code Listing 2 shows the example program for Figure 15.

Code Listing 2: Example of simultaneous ADC conversion on three SARs by single TCPWM timer

void Cy_Tcpwm_Counter_Disable(volatile stc_TCPWM_GRP_CNT_t *ptscTCPWM)
{
    ptscTCPWM->unCTRL.stcField.u1ENABLED = 0x00;
}

cy_en_adc_status_t Cy_Adc_Init(volatile stc_PASS_SAR_t * base, const cy_stc_adc_config_t * config)
{
    cy_en_adc_status_t ret = CY_ADC_SUCCESS;
    un_PASS_SAR_CTL_t unSarCtl = { 0 };

    if (NULL != config)
    {
        /* CTL register setting */
        base->unPRECOND_CTL.stcField.u4PRECOND_TIME = config->preconditionTime;

        /* CTL register setting */
        unSarCtl.stcField.u8PWRUP_TIME = config->powerupTime;
        unSarCtl.stcField.u1IDLE_PWRDWN = config->enableIdlePowerDown ? 1u : 0;
        unSarCtl.stcField.u1MSB_STRETCH = config->msbStretchMode;
        unSarCtl.stcField.u1HALF_LSB = config->enableHalfLsbConv ? 1u : 0;
        unSarCtl.stcField.u1SARMUX_EN = config->sarMuxEnable ? 1u : 0;
        unSarCtl.stcField.u1ADC_EN = config->adcEnable ? 1u : 0;
        unSarCtl.stcField.u1ENABLED = config->sarIpEnable ? 1u : 0;
        base->unCTL.u32Register = unSarCtl.u32Register;
    }
    else
    {
        ret = CY_ADC_BAD_PARAM;
    }
    return ret;
}

cy_en_adc_status_t Cy_Adc_SetGenericTriggerInput(volatile stc_PASS_EPASS_MMIO_t * base, uint8_t numOfAdc, uint8_t
                                                    triggerInputNumber, uint8_t genericTriggerValue)
{
    cy_en_adc_status_t ret = CY_ADC_SUCCESS;

    switch(triggerInputNumber)
    {
        case 2:
            base->unSAR_TR_IN_SEL[numOfAdc].stcField.u4IN2_SEL = genericTriggerValue; //Select GENERIC TRIGGER 2
            break;
    }
    return ret;
}

cy_en_trigmux_status_t Cy_TrigMux_Connect(uint32_t inTrig, uint32_t outTrig, uint32_t invert, en_trig_type_t trigType,
                                            uint32_t dbg_frz_en)
{
    volatile stc_PERI_TR_GR_TR_CTL_field_t* pTR_CTL;
    cy_en_trigmux_status_t retVal = CY_TRIGMUX_BAD_PARAM;

    if ((inTrig & CY_TR_GROUP_MASK) == (outTrig & CY_TR_GROUP_MASK))
    {
        pTR_CTL = &(PERI->TR_GR[(outTrig & CY_TR_GROUP_MASK) >> CY_TR_GROUP_SHIFT].unTR_CTL[outTrig & CY_TR_MASK].stcField); //Select output trigger TRIG_OUT_MUX_6_PASS_GEN_TR_IN8
        pTR_CTL->u8TR_SEL = inTrig; //Select input trigger TRIG_IN_MUX_6_TCPWM_16M_TR_OUT11
        pTR_CTL->u1TR_INV = invert; //Invert input trigger
        pTR_CTL->u1TR_EDGE = trigType; // Select edge sensitive trigger as output trigger type
        retVal = CY_TRIGMUX_SUCCESS;
    }
    return retVal;
}

cy_en_adc_status_t Cy_Adc_Channel_Init(volatile stc_PASS_SAR_CH_t * base, const cy_stc_adc_channel_config_t * config)
{
    cy_en_adc_status_t ret = CY_ADC_SUCCESS;
    un_PASS_SAR_CH_TR_CTL_t unTrCtl = { 0 };
    un_PASS_SAR_CH_SAMPLE_CTL_t unSampleCtl = { 0 };
    un_PASS_SAR_CH_POST_CTL_t unPostCtl = { 0 };
    un_PASS_SAR_CH_RANGE_CTL_t unRangeCtl = { 0 };
    un_PASS_SAR_CH_INTR_t unIntr = { 0 };

    if (NULL != config)
    {
        /* At first disable the channel */
        base->unENABLE.stcField.u1CHAN_EN = 0u;

        /* Clear whole interrupt flags */
        unIntr.stcField.u1CH_OVERFLOW = 1u;
        unIntr.stcField.u1CH_PULSE = 1u;
        unIntr.stcField.u1CH_RANGE = 1u;
        unIntr.stcField.u1GRP_CANCELLED = 1u;
        unIntr.stcField.u1GRP_DONE = 1u;
        unIntr.stcField.u1GRP_OVERFLOW = 1u;
        base->unINTR.u32Register = unIntr.u32Register;

        unTrCtl.stcField.u3SEL = config->triggerSelection;
        unTrCtl.stcField.u3PRIO = config->channelPriority;
        unTrCtl.stcField.u2PREEMPT_TYPE = config->preenptionType;
        unTrCtl.stcField.u1GROUP_END = config->isGroupEnd ? 1u : 0u;
        unTrCtl.stcField.u1DONE_LEVEL = config->doneLevel ? 1u : 0u;
        base->unTR_CTL.u32Register = unTrCtl.u32Register;

        unSampleCtl.stcField.u6PIN_ADDR = config->pinAddress;
        unSampleCtl.stcField.u2PORT_ADDR = config->portAddress;
        unSampleCtl.stcField.u3EXT_MUX_SEL = config->extMuxSelect;
        unSampleCtl.stcField.u1EXT_MUX_EN = config->extMuxEnable ? 1u : 0u;
        unSampleCtl.stcField.u2PRECOND_MODE = config->preconditionMode;
        unSampleCtl.stcField.u2OVERLAP_DIAG = config->overlapDiagMode;
        unSampleCtl.stcField.u12SAMPLE_TIME = config->sampleTime;
        unSampleCtl.stcField.u1ALT_CAL = config->calibrationValueSelect;
        base->unSAMPLE_CTL.u32Register = unSampleCtl.u32Register;

        unPostCtl.stcField.u3POST_PROC = config->postProcessingMode;
        unPostCtl.stcField.u1LEFT_ALIGN = config->resultAlignment;
        unPostCtl.stcField.u1SIGN_EXT = config->signExtention;
        unPostCtl.stcField.u8AVG_CNT = config->averageCount;
        unPostCtl.stcField.u5SHIFT_R = config->rightShift;
        unPostCtl.stcField.u2RANGE_MODE = config->rangeDetectionMode;
        base->unPOST_CTL.u32Register = unPostCtl.u32Register;

        unRangeCtl.stcField.u16RANGE_LO = config->rangeDetectionLoThreshold;
        unRangeCtl.stcField.u16RANGE_HI = config->rangeDetectionHiThreshold;
        base->unRANGE_CTL.u32Register = unRangeCtl.u32Register;
    }
    else
    {
        ret = CY_ADC_BAD_PARAM;
    }
    return ret;
}

void Cy_Adc_Channel_Enable(volatile stc_PASS_SAR_CH_t * base)
{
    base->unENABLE.stcField.u1CHAN_EN = 1u;
}

3.3 Triggering ADC conversion by TCPWM timer

This section explains how an input trigger in a one-to-one group trigger initiates ADC conversion.

3.3.1 Use case description of triggering ADC conversion by TCPWM timer

Figure 17 shows an example application of one-to-one trigger in CYT2B7 series. ADC conversion of SAR0 is triggered by TCPWM 16-bit counter on one-to-one trigger Multiplexer Group 1. Compare match of TCPWM counter channel 0 and channel 1 trigger the conversion on channel 4 and 5 of SAR0, respectively. Figure 18 demonstrates the operation. For more details on TCPWM and SAR ADC, see the "TCPWM" and "SAR ADC" chapters of the Architecture TRM.

Figure 17: Example of one-to-one trigger in CYT2B7 series

Diagram Description: A block diagram shows TCPWM#0 (16-bit) with CC0 match output connected to a Trigger Multiplexer (MUX Group 2). The multiplexer routes this to TCPWM_TO_PASS_CH_TR[4] and TCPWM_TO_PASS_CH_TR[5]. These signals then go to a SAR Sequencer with HW Trigger Arbitration, which triggers the ADC Core for SAR ADC0 channels 4 and 5.

Figure 18: Example operation: Triggering ADC conversion by TCPWM timer

Diagram Description: This figure illustrates the operation of triggering ADC conversion. A TCPWM#0 (16-bit) timer's CC0 match output triggers an ADC conversion. Similarly, a TCPWM#1 (16-bit) timer's CC0 match output also triggers an ADC conversion. These conversions are for ADC channels 4 and 5.

Triggers must be set to implement this application. Figure 19 describes the procedure for setting the trigger. Figure 19 also provides the setting for TCPWM counter and SAR0 structure.

Figure 19: Setting for one-to-one trigger in CYT2B7 series

Diagram Description: A flowchart outlines the steps for configuring a one-to-one trigger for ADC conversion. Steps include configuring SAR0 structure, configuring SAR0 channels 4 and 5, enabling SAR0 channels 4 and 5, configuring the one-to-one trigger (output, input, invert, edge sensitivity), disabling TCPWM#0,1, configuring TCPWM#0,1 for timer mode, configuring output trigger selection for TCPWM#0,1, setting compare values for TCPWM#0,1, enabling TCPWM#0,1, and configuring/activating SW trigger on TCPWM#0,1.

The configuration for the output trigger and input trigger of a one-to-one trigger in Step (4) are described as follows.

Trigger Multiplexer Setting

Table 14 lists the values to be set. These tables are extracted from CYT2B7 series datasheet that provides the trigger group and input trigger.

Table 14: Trigger one-to-one MUX Group 1 of CYT2B7 series

The following describes how to connect SAR0 channel 4 and channel 5 to 16-bit TCPWM channel 0. Note that in a one-to-one group trigger, one input trigger is directly connected to a specific output trigger. Thus, specifying only the input trigger number is sufficient to indicate its output trigger.

1. Configuration register selection: MUX Group 1 (i=1). Input trigger TCPWM0_16_TR_OUT1[0], directly connects to output trigger PASS0_CH_TR_IN[4] (k=4). Input trigger TCPWM0_16_TR_OUT1[1], directly connects to output trigger PASS0_CH_TR_IN[5] (k=5). Therefore, the registers are specified as PERI_TR_1TO1_GR1_TR_CTL4, and PERI_TR_1TO1_GR1_TR_CTL5, respectively.
2. Input trigger configuration: Typically, input trigger of one-to-one trigger is enabled. The configurations are PERI_TR_1TO1_GR1_TR_CTL4.TR_SEL = 1, and PERI_TR_1TO1_GR1_TR_CTL5.TR_SEL = 1.

For more details on Trigger Input and Trigger Output, see the device datasheets.

3.3.2 Example program for triggering ADC conversion by TCPWM timer

Code Listing 3 demonstrates the example program for Figure 19.

Code Listing 3: Example of triggering ADC conversion by TCPWM timer

cy_en_adc_status_t Cy_Adc_Init(volatile stc_PASS_SAR_t * base, const cy_stc_adc_config_t * config)
{
    cy_en_adc_status_t ret = CY_ADC_SUCCESS;
    un_PASS_SAR_CTL_t unSarCtl = { 0 };

    if (NULL != config)
    {
        /* CTL register setting */
        base->unPRECOND_CTL.stcField.u4PRECOND_TIME = config->preconditionTime;

        /* CTL register setting */
        unSarCtl.stcField.u8PWRUP_TIME = config->powerupTime;
        unSarCtl.stcField.u1IDLE_PWRDWN = config->enableIdlePowerDown ? 1u : 0;
        unSarCtl.stcField.u1MSB_STRETCH = config->msbStretchMode;
        unSarCtl.stcField.u1HALF_LSB = config->enableHalfLsbConv ? 1u : 0;
        unSarCtl.stcField.u1SARMUX_EN = config->sarMuxEnable ? 1u : 0;
        unSarCtl.stcField.u1ADC_EN = config->adcEnable ? 1u : 0;
        unSarCtl.stcField.u1ENABLED = config->sarIpEnable ? 1u : 0;
        base->unCTL.u32Register = unSarCtl.u32Register;
    }
    return ret;
}

cy_en_adc_status_t Cy_Adc_Channel_Init(volatile stc_PASS_SAR_CH_t * base, const cy_stc_adc_channel_config_t * config)
{
    cy_en_adc_status_t ret = CY_ADC_SUCCESS;
    un_PASS_SAR_CH_TR_CTL_t unTrCtl = { 0 };
    un_PASS_SAR_CH_SAMPLE_CTL_t unSampleCtl = { 0 };
    un_PASS_SAR_CH_POST_CTL_t unPostCtl = { 0 };
    un_PASS_SAR_CH_RANGE_CTL_t unRangeCtl = { 0 };
    un_PASS_SAR_CH_INTR_t unIntr = { 0 };

    if (NULL != config)
    {
        /* At first disable the channel */
        base->unENABLE.stcField.u1CHAN_EN = 0u;

        /* Clear whole interrupt flags */
        unIntr.stcField.u1CH_OVERFLOW = 1u;
        unIntr.stcField.u1CH_PULSE = 1u;
        unIntr.stcField.u1CH_RANGE = 1u;
        unIntr.stcField.u1GRP_CANCELLED = 1u;
        unIntr.stcField.u1GRP_DONE = 1u;
        unIntr.stcField.u1GRP_OVERFLOW = 1u;
        base->unINTR.u32Register = unIntr.u32Register;

        unTrCtl.stcField.u3SEL = config->triggerSelection;
        unTrCtl.stcField.u3PRIO = config->channelPriority;
        unTrCtl.stcField.u2PREEMPT_TYPE = config->preenptionType;
        unTrCtl.stcField.u1GROUP_END = config->isGroupEnd ? 1u : 0u;
        unTrCtl.stcField.u1DONE_LEVEL = config->doneLevel ? 1u : 0u;
        base->unTR_CTL.u32Register = unTrCtl.u32Register;

        unSampleCtl.stcField.u6PIN_ADDR = config->pinAddress;
        unSampleCtl.stcField.u2PORT_ADDR = config->portAddress;
        unSampleCtl.stcField.u3EXT_MUX_SEL = config->extMuxSelect;
        unSampleCtl.stcField.u1EXT_MUX_EN = config->extMuxEnable ? 1u : 0u;
        unSampleCtl.stcField.u2PRECOND_MODE = config->preconditionMode;
        unSampleCtl.stcField.u2OVERLAP_DIAG = config->overlapDiagMode;
        unSampleCtl.stcField.u12SAMPLE_TIME = config->sampleTime;
        unSampleCtl.stcField.u1ALT_CAL = config->calibrationValueSelect;
        base->unSAMPLE_CTL.u32Register = unSampleCtl.u32Register;

        unPostCtl.stcField.u3POST_PROC = config->postProcessingMode;
        unPostCtl.stcField.u1LEFT_ALIGN = config->resultAlignment;
        unPostCtl.stcField.u1SIGN_EXT = config->signExtention;
        unPostCtl.stcField.u8AVG_CNT = config->averageCount;
        unPostCtl.stcField.u5SHIFT_R = config->rightShift;
        unPostCtl.stcField.u2RANGE_MODE = config->rangeDetectionMode;
        base->unPOST_CTL.u32Register = unPostCtl.u32Register;

        unRangeCtl.stcField.u16RANGE_LO = config->rangeDetectionLoThreshold;
        unRangeCtl.stcField.u16RANGE_HI = config->rangeDetectionHiThreshold;
        base->unRANGE_CTL.u32Register = unRangeCtl.u32Register;
    }
    return ret;
}

3.4 Simultaneous starting of TCPWM timer by SW trigger

This section explains how a SW trigger simultaneously starts multiple TCPWM counters.

3.4.1 Use case description of simultaneous starting of TCPWM timer by SW trigger

Figure 20 shows an example application of SW trigger in CYT2B7 series. In 120-degree commutation control, three TCPWM 16-bit Motor Control counter ccchannel 0, 1, and 2 are triggered simultaneously by SW. In this case, channel 0, channel 1, and channel 2 represent U-phase, V-phase, and W-phase, respectively. Figure 21 demonstrates the operation. The connection between trigger MUX Group 4 and TCPWM 16-bit motor control counter is illustrated in Figure 22. For more details on TCPWM, see the "TCPWM" chapter of the Architecture TRM.

Figure 20: Example of SW trigger in CYT2B7 series

Diagram Description: This figure shows a SW trigger setup for multiple TCPWM counters. A "Software Command Register" is shown connected to a "Trigger Multiplexer". The multiplexer routes signals to TCPWM#0, TCPWM#1, and TCPWM#2 (all 16-bit for Motor). These counters are labeled with U-phase (UH, UL), V-phase (VH, VL), and W-phase (WH, WL) outputs, indicating their use in motor control.

Figure 21: Example operation: Simultaneous starting of TCPWM timer by SW trigger

Diagram Description: This figure illustrates the simultaneous starting of TCPWM timers. It shows the U-phase, V-phase, and W-phase counters, all driven by TCPWM#0,1,2 (16-bit for Motor). The diagram depicts a periodic waveform (10kHz, 100us) that triggers the counters, showing a "Counter Start" event.

Figure 22: Connection between MUX Group 4 and TCPWM 16-bit motor control counter

Diagram Description: This figure details the connection between trigger multiplexer groups and TCPWM counters for SW triggering. MUX Group 4 receives "Triggers Group Inputs" like TCPWM_ALL_CNT_TR_IN[0:15] and is controlled by SW Command (PERI_TR_GR4_TR_CTL[0:15]). MUX Group 5 receives similar inputs and is controlled by SW Command (PERI_TR_GR5_TR_CTL[0:10]). These multiplexers route signals to Counter0, which has inputs for Capture0, Count, Reload, Stop, Start, and Capture1. The selection of these inputs is managed by registers like TCPWM0_GRP0_CNT0_TR_IN_SEL0 and TCPWM0_GRP0_CNT0_TR_IN_SEL1.

Triggers must be set to implement this application. Figure 23 lists the procedure for setting the trigger.

Figure 23: Setting for one-to-one trigger in CYT2B7 series

Diagram Description: A flowchart outlines the steps for configuring SW trigger for TCPWM counters. Steps include disabling TCPWM#0,1,2, configuring them for PWM mode, setting compare values (Compare0, CC0_BUFF, Compare1, CC1_BUFF), enabling TCPWM#0,1,2, and configuring/activating the SW trigger (selecting activated trigger, trigger group, edge sensitivity, and output trigger).

The configuration for SW trigger in Step (8) are described as follows.

Trigger Multiplexer Setting

Table 15 lists the values to be set for PERI_TR_CMD.GROUP_SEL (=i) and PERI_TR_CMD.TR_SEL (=k) can be found in. This table is extracted from CYT2B7 series datasheet that provides trigger group and output trigger.

Table 15: Trigger outputs of MUX Group 4 of CYT2B7 series

Figure 24 shows SW triggering the TCPWM counter.

Figure 24: SW triggering TCPWM counter

Diagram Description: This figure shows the process of triggering a TCPWM counter via software. An "Input Trigger j" feeds into "SW Input Trigger Qualification", then "SW Output Trigger Qualification", and finally an "Output Trigger k" (TCPWM_ALL_CNT_TR_IN[0]). Control signals are shown: PERI_TR_CMD.ACTIVATE, PERI_TR_CMD.GROUP_SEL = 4, PERI_TR_CMD.TR_SEL = 0, PERI_TR_CMD.TR_EDGE = 1, and PERI_TR_CMD.TR_OUT_SEL = 1.

The following describes how to initiate the timer of TCPWM counter.

1. Activated trigger selection: PERI_TR_CMD.TR_SEL = 0: Output trigger TCPWM_ALL_CNT_TR_IN[0] (k=0). PERI_TR_CMD.GROUP_SEL = 4: MUX Group 4 of group trigger (i=4). PERI_TR_CMD.TR_EDGE = 1: Edge sensitive trigger.
2. Specifying activated trigger: PERI_TR_CMD.OUT_SEL = 1: Output trigger.
3. Activate SW trigger: PERI_TR_CMD.ACTIVATE = 1.

Glossary

Table 16: Glossary

Related Documents

The following are the Traveo II family series datasheets and technical reference manuals. Contact Technical Support to obtain these documents.

• Device datasheet
  • CYT2B7 Datasheet 32-Bit Arm® Cortex®-M4F Microcontroller Traveo™ II Family
  • CYT2B9 Datasheet 32-Bit Arm® Cortex®-M4F Microcontroller Traveo™ II Family
  • CYT4BF Datasheet 32-Bit Arm® Cortex®-M7 Microcontroller Traveo™ II Family
  • CYT4DN Datasheet 32-Bit Arm® Cortex®-M7 Microcontroller Traveo™ II Family
• CYT2B Series
  • Traveo™ II Automotive Body Controller Entry Family Architecture Technical Reference Manual (TRM)
  • Traveo™ II Automotive Body Controller Entry Registers Technical Reference Manual (TRM) for CYT2B7
  • Traveo™ II Automotive Body Controller Entry Registers Technical Reference Manual (TRM) for CYT2B9
• CYT4B Series
  • Traveo™ II Automotive Body Controller High Family Architecture Technical Reference Manual (TRM)
  • Traveo™ II Automotive Body Controller High Registers Technical Reference Manual (TRM)
• CYT4D Series
  • Traveo™ II Automotive Cluster 2D Family Architecture Technical Reference Manual (TRM)
  • Traveo™ II Automotive Cluster 2D Registers Technical Reference Manual (TRM)

Other References

Cypress provides the Sample Driver Library (SDL) including startup as sample software to access various peripherals. SDL also serves as a reference to customers, for drivers that are not covered by the official AUTOSAR products. SDL cannot be used for production purposes as it has not been developed using any automotive SW development process. The code snippets in this application note are part of the SDL. Contact Technical Support to obtain the SDL.

Revision history

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

Edition 2021-06-07

Published by Infineon Technologies AG
81726 Munich, Germany

© 2021 Infineon Technologies AG. All Rights Reserved.

Do you have a question about this document? Go to www.cypress.com/support

Document reference: 002-28104 Rev. *A

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