Customer Training Workshop: Traveo™ II Program and Debug Interface

Target Products

Target product list for this training material:

Introduction to Traveo II Body Controller Entry

The program and debug interface is part of the CPU subsystem.

System Resources:

• Power: Sleep Control, POR, BOD, OVD, REF, LVD, PWRSYS-HT, LDO
• Clock: Clock Control, 2xILO, WDT, IMO, ECO, FLL, CSV, 1xPLL
• Reset: Reset Control, XRES
• Test: TestMode Entry, Digital DFT, Analog DFT
• Power Modes: Active/Sleep, Low Power Active/Sleep, DeepSleep, Hibernate

CPU Subsystem:

• Arm Cortex-M0+ (100 MHz) with SWJ/MTB/CTI, Initiator/MMIO, MUL, NVIC, MPU
• eCT Flash (4160 KB Code Flash + 128 KB Work Flash) with FLASH Controller
• SRAM0 (256 KB) with SRAM Controller
• SRAM1 (256 KB) with SRAM Controller
• ROM (32 KB) with ROM Controller
• CRYPTO (AES, SHA, CRC, TRNG, RSA, ECC)

System Interconnect: Multi Layer AHB, IPC, MPU/SMPU

Peripheral Interconnect: MMIO, PPU

• P-DMA0 (92 Channel)
• P-DMA1 (44 Channel)
• M-DMA0 (4 Channel)
• TIMER, CTR, QD, PWM (83x TCPWM)
• CXPI Interface (4x CXPI)
• CAN-FD Interface (8x CANFD)
• I2C, SPI, UART (7x SCB)
• I2C, SPI, UART (1x SCB)
• LIN/UART (12x LIN)
• High-Speed I/O Matrix, Smart I/O, Boundary Scan (5x Smart I/O, Up to 148x GPIO STD, 4x GPIO ENH)
• eFUSE (1024 bit)
• Event Generator (EVTGEN)

I/O Subsystem

Hint Bar: Review TRM chapter 32 for additional details.

Introduction to Traveo II Body Controller High

The program and debug interface is part of the CPU subsystem.

System Resources:

• Power: Sleep Control, POR, BOD, OVP, LVD, REF, PWRSYS-HT, LDO
• Clock: Clock Control, 2xILO, WDT, IMO, ECO, FLL, 4xPLL, CSV
• Reset: Reset Control, XRES
• Test: TestMode Entry, Digital DFT, Analog DFT
• Power Modes: Active/Sleep, Low Power Active/Sleep, DeepSleep, Hibernate

CPU Subsystem:

• Arm Cortex-M7 (350 MHz) with FPU (SP/DP), AHBP, NVIC, MPU, AXI AHBS
• Arm Cortex-M0+ (100 MHz) with SWJ/MTB/CTI, Initiator/MMIO, MUL, NVIC, MPU
• eCT FLASH (8384 KB Code flash + 256 KB Work flash) with FLASH Controller
• SRAM0 (512 KB) with SRAM Controller
• SRAM1 (256 KB) with SRAM Controller
• SRAM2 (256 KB) with SRAM Controller
• ROM (64 KB) with ROM Controller
• CRYPTO (AES, SHA, CRC, TRNG, RSA, ECC)
• ITCM (16 KB), DTCM (16 KB)

System Interconnect: Multi Layer AXI/AHB, IPC, MPU/SMPU

Peripheral Interconnect: MMIO, PPU

• P-DMA0 (143 Channel)
• P-DMA1 (65 Channel)
• M-DMA0 (8 Channel)
• TIMER, CTR, QD, PWM (115x TCPWM)
• I2S/TDM In/Out (3x AUDIOSS)
• Event Generator (EVTGEN)
• FlexRay Interface (1x FLEXRAY)
• CAN-FD Interface (10x CANFD)
• I2C, SPI, UART, LIN (10x SCB)
• I2C, SPI, UART, LIN (1x SCB)
• LIN/UART (20x LIN)
• High-Speed I/O Matrix, Smart I/O, Boundary Scan (5x Smart I/O, Up to 196x GPIO_STD, 4x GPIO_ENH, 40x HSIO)
• SD/SDIO/eMMC (SDHC)
• Serial Memory Interface (Hyperbus, Single SPI, Dual SPI, Quad SPI, Octal SPI) (2x ETH)
• 10/100/1000 Ethernet + AVB
• eFUSE

I/O Subsystem

Hint Bar: Review TRM chapter 36 for additional details.

Introduction to Traveo II Cluster

The program and debug interface is part of the CPU subsystem.

System Resources:

• Power: Sleep Control, POR, BOD, OVP, REF, LVD, PWRSYS-HT, LDO
• Clock: Clock Control, 2xILO, WDT, IMO, ECO, FLL, CSV, 8xPLL, LPECO
• Reset: Reset Control, XRES
• Test: TestMode Entry, Digital DFT, Analog DFT
• Power Modes: Active/Sleep, Low Power Active/Sleep, DeepSleep, Hibernate

CPU Subsystem:

• Arm Cortex-M7 (320 MHz) with FPU (SP/DP), AHBP, NVIC, MPU, AXI AHBS
• Arm Cortex-M0+ (100 MHz) with SWJ/MTB/CTI, Initiator/MMIO, MUL, NVIC, MPU
• eCT FLASH (6336 KB Code Flash + 128 KB Work Flash) with FLASH Controller
• SRAM0 (256 KB) with SRAM Controller
• SRAM1 (256 KB) with SRAM Controller
• SRAM2 (128 KB) with SRAM Controller
• ROM (64 KB) with ROM Controller
• CRYPTO (AES, SHA, CRC, TRNG, RSA, ECC)
• ITCM (64 KB), DTCM (64 KB)

System Interconnect: Multi Layer AXI/AHB, IPC, MPU/SMPU

Peripheral Interconnect: MMIO, PPU

• P-DMA0 (76 Channel)
• P-DMA1 (84 Channel)
• M-DMA0 (8 Channel)
• High-Speed I/O Matrix, Smart I/O, Boundary Scan (1x Smart I/O, 52x GPIO STD, 8x GPIO ENH, 26x GPIO SMC, 70x HSIO STD, 22x HSIO ENH, 4x HSIO ENG DIFF)
• GFX Subsystem: VRAM (4096 KB) with VRAM Controller, Vector Gfx, 2.5D Engine
• GFX Interconnect: AXI

I/O Subsystem

Hint Bar: Review TRM chapter 38 for additional details.

Program and Debug Interface Overview

• The program and debug interface is a communication gateway for an external device to perform programming and debugging.
• The external device includes a Cypress-supplied programmer and a third-party programmer and debugger.
• Communication protocol between the external device and Traveo II microcontroller is supplied by Serial Wire Debug (SWD) and Joint Test Action Group (JTAG).

Hint Bar: Review the Program and Debug Interface TRM chapter for additional details.

Multi-Core Debug for CYT2B6/B7/B9/BL

• Arm® Cortex®-M0+ Core debug components: Cross-triggering interface (CTI), four hardware breakpoints, and two watchpoints.
• Arm Cortex-M4 Core debug components: CTI, six hardware breakpoints, and four watchpoints.
• Enables multi-core debug: Three CTIs connected via cross-triggering matrix (CTM). Start or stop CM0+/CM4 at the same time. Start or stop instruction tracing based on whether or not the trace buffer is full, or on the break.
• Debug and access port (DAP) security: Three access ports (APs) each can be independently disabled. eFuse (permanent). System AP is protected by MPU.

Hint Bar: Review TRM chapter 31 and CoreSight documentation for additional details.

Program and Debug Interface for Debug:

The diagram illustrates the interaction between the Arm Cortex-M0+ and Cortex-M4 subsystems, including the DAP, SWD/JTAG interface, CM0+ and CM4 access ports, Cross Trigger Interfaces (CTI), Micro Trace Buffer (MTB), Embedded Trace Buffer (ETB), Embedded Trace Macro (ETM), and Cross Trigger Matrix (CTM).

Multi-Core Debug for CYT3BB/4BB/3DL/4DN

• Arm® Cortex®-M0+ Core debug components: Cross-triggering interface (CTI), four hardware breakpoints, and two watchpoints.
• Arm Cortex-M7 Core debug components: CTI, six hardware breakpoints, and four watchpoints.
• Enables multi-core debug: Three CTIs connected via cross-triggering matrix (CTM). Start or stop CM0+/CM7 at the same time. Start or stop instruction tracing based on whether or not the trace buffer is full, or on the break.
• Debug and access port (DAP) security: Four access ports (APs) each can be independently disabled. eFuse (permanent). System AP is protected by MPU.

Hint Bar: Review TRM chapter 36 and CoreSight documentation for additional details.

Program and Debug Interface for Debug:

The diagram illustrates the interaction between the Arm Cortex-M0+ and Cortex-M7 subsystems, including the DAP, SWD/JTAG interface, CM0+ and CM7 access ports, Cross Trigger Interfaces (CTI), Micro Trace Buffer (MTB), Embedded Trace Buffer (ETB), Embedded Trace Macro (ETM), and Cross Trigger Matrix (CTM).

Tracing for CYT2B6/B7/B9/BL

• Arm® Cortex®-M0+: Micro trace buffer (MTB) for tracing and storing instructions.
• Arm Cortex-M4: Serial wire viewer (SWV) for output trace information with single pin at SWO. Embedded trace macrocell (ETM) for tracing instructions. Embedded trace buffer (ETB) for tracing instructions and storing them in a local SRAM. Instrumentation trace macrocell (ITM) for tracing output. Trace port interface unit (TPIU) for tracing information from the chip to an external trace port analyzer. Parallel (4 pins, multiplexed with GPIO and clock pin). SWO (multiplexed on JTAG TDO).

Hint Bar: Review TRM chapter 31 and CoreSight Documentations for additional details.

Program and Debug Interface for Tracing:

The diagram shows the components involved in tracing, including the DAP, SWD/JTAG interface, Arm Cortex-M0+ and Cortex-M4 subsystems, Cross Trigger Interfaces (CTI), Micro Trace Buffer (MTB), Embedded Trace Buffer (ETB), Embedded Trace Macro (ETM), and Trace Port Interface Unit (TPIU).

Tracing for CYT3BB/4BB/3DL/4DN

• Arm® Cortex®-M0+: Micro trace buffer (MTB) for tracing and storing instructions.
• Arm Cortex-M7: Embedded trace macrocell (ETM) for tracing instructions. Embedded trace buffer (ETB) for tracing instructions and storing them in a local SRAM. Instrumentation trace macrocell (ITM) for tracing output. Trace port interface unit (TPIU) for tracing information from the chip to an external trace port analyzer. Parallel (4 pins, multiplexed with GPIO and clock pin).

Hint Bar: Review TRM chapter 36 and CoreSight Documentations for additional details.

Program and Debug Interface for Tracing:

The diagram illustrates the tracing components, including the DAP, SWD/JTAG interface, Arm Cortex-M0+ and Cortex-M7 subsystems, Cross Trigger Interfaces (CTI), Micro Trace Buffer (MTB), Embedded Trace Buffer (ETB), Embedded Trace Macro (ETM), and Trace Port Interface Unit (TPIU).

Serial Wire Debug (SWD) and JTAG Interface

• The SWD protocol is a packet-based serial transaction protocol.
• JTAG controller and interface are compliant to IEEE-1149.1-2001.
• The test access port (TAP) interface is used to control the values in the boundary scan cells. Boundary scan test supported.

Debug Interface Pin Configuration on Boot ROM:

After reset, the debug pins remain in high-impedance mode until Boot ROM initializes them.

Hint Bar: Review the Program and Debug Interface TRM chapter for additional details.

Programmer and IDEs for Traveo II

Flash Programmer

Integrated Design Environment (IDE)

Revision History