Microchip MSC015SMA070SD 700V N-Channel SiC MOSFET

Product Overview

The MSC015SMA070SD is a 700V, 15 mΩ typical (at V_GS = 20V) N-Channel Silicon Carbide (SiC) MOSFET. It features 17 mΩ typical resistance at V_GS = 18V and is housed in a TO-263-7L XL package with a source sense pin.

The device includes an illustration of the TO-263 package with pin numbering (1-7) and an internal schematic showing the Gate, Drain, and Source terminals, along with a dedicated Source Sense terminal (Pin 2). The backside tab is identified as the Drain connection.

Features

AEC-Q101 qualified option available
Low capacitances and low gate charge
Fast switching speed due to low internal gate resistance (ESR)
Stable operation at high junction temperature, T_J(max) = 175 °C
Fast and reliable body diode
Superior avalanche ruggedness
RoHS compliant

Benefits

High efficiency to enable lighter and more compact systems
Simple to drive and easy to parallel
Improved thermal capabilities and lower switching losses
Eliminates the need for an external freewheeling diode
Lower system cost of ownership

Applications

Photovoltaic (PV) inverter, converter, and industrial motor drives
Smart grid transmission and distribution
Induction heating and welding
Hybrid Electric Vehicle (HEV) powertrain and Electric Vehicle (EV) charger
Power supply and distribution

Device Specifications

1.1 Absolute Maximum Ratings

The following table details the absolute maximum ratings for the MSC015SMA070SD.

Symbol	Parameter	Ratings	Unit
V_DSS	Drain source voltage	700	V
I_D	Continuous drain current at T_C = 25 °C	172	A
I_D	Continuous drain current at T_C = 100 °C	121	A
I_DM	Pulsed drain current¹	450	A
V_GS	Gate-source voltage	23 to -10	V
V_GS	Transient gate-source voltage	25 to -12	V
P_D	Total power dissipation at T_C = 25 °C	692	W
—	Linear derating factor	4.5	W/°C

¹ Repetitive rating: pulse width and case temperature are limited by the maximum junction temperature.

Thermal and Mechanical Characteristics

The following table lists the thermal and mechanical characteristics of the device.

Symbol	Characteristic/Test Conditions	Min.	Typ.	Max.	Unit
R_θJC	Junction-to-case thermal resistance	—	0.17	0.22	°C/W
T_J	Operating junction temperature	-55	—	175	°C
T_STG	Storage temperature	-55	—	175	°C
—	Reflow temperature	—	—	260	°C
W_t	Package weight	—	1.6	—	g

ESD practices should comply with JESD-625.

1.2 Electrical Performance

The following table shows the static characteristics of this device. T_J = 25 °C unless otherwise specified.

Symbol	Characteristic	Test Conditions	Min.	Typ.	Max.	Unit
V_(BR)DSS	Drain-source breakdown voltage	V_GS = 0V, I_D = 100 µA	700	—	—	V
R_DS(on)¹	Drain-source on resistance	V_GS = 20V, I_D = 40A	—	15	19	mΩ
R_DS(on)	Drain-source on resistance	V_GS = 18V, I_D = 40A	—	17	—	mΩ
V_GS(th)	Gate-source threshold voltage	V_GS = V_DS, I_D = 4 mA	1.9	3.0	5.0	V
I_DSS	Zero gate voltage drain current	V_DS = 700V, V_GS = 0V	—	0.3	35	µA
I_DSS	Zero gate voltage drain current	V_DS = 700V, V_GS = 0V, T_J = 175 °C	—	3.5	—	µA
I_GSS	Gate-source leakage current	V_GS = 20V/-10V	—	—	±100	nA

¹ Pulse test: pulse width < 380 µs, duty cycle < 2%.

Dynamic Characteristics

The following table shows the dynamic characteristics of this device. T_J = 25 °C unless otherwise specified. The dynamic characteristics are characterized, not 100% tested, at the recommended operating V_GS = 20V/-5V.

Symbol	Characteristic	Test Conditions	Min.	Typ.	Max.	Unit
C_iss	Input capacitance	V_GS = 0V	—	4324	—	pF
C_rss	Reverse transfer capacitance	V_DD = 700V	—	44	—	pF
C_oss	Output capacitance	V_AC = 25 mV, f = 200 kHz	—	506	—	pF
Q_G	Total gate charge	V_GS = -5V/20V	—	215	—	nC
Q_GS	Gate-source charge	V_DD = 470V	—	58	—	nC
Q_GD	Gate-drain charge	I_D = 40A	—	35	—	nC
t_d(on)	Turn-on delay time	V_DD = 470V	—	27	—	ns
t_r	Voltage rise time	V_GS = -5V/20V	—	22	—	ns
t_d(off)	Turn-off delay time	I_D = 50A	—	40	—	ns
t_f	Voltage fall time	R_G(ext) = 4Ω	—	12	—	ns
E_on	Turn-on switching energy	Freewheeling diode = MSC015SMA070SD (V_GS = -5V); reference Figure 1-18	—	413	—	µJ
E_off	Turn-off switching energy	—	89	—	µJ
E_SR	Gate equivalent series resistance	f = 1 MHz, 25 mV, drain short	—	0.69	—	Ω
t_SCWT	Short circuit withstand time	V_DS = 560V, V_GS = 20V	—	3.0	—	µs
E_AS	Avalanche energy, single pulse	I_D = 40A	—	6400	—	mJ

The following table shows the body diode characteristics of this device. T_J = 25 °C unless otherwise specified. The body diode reverse recovery is characterized, not 100% tested.

Symbol	Characteristic	Test Conditions	Min.	Typ.	Max.	Unit
V_SD	Diode forward voltage	I_SD = 40A, V_GS = 0V	—	3.3	—	V
V_SD	Diode forward voltage	I_SD = 40A, V_GS = -5V	—	3.6	5.0	V
t_rr	Reverse recovery time	I_SD = 50A, V_GS = -5V, Drive R_G = 4Ω, V_DD = 470V, dI/dt = -10900 A/µs	—	18	—	ns
Q_rr	Reverse recovery charge	—	1010	—	nC
I_RRM	Reverse recovery current	—	89	—	A

1.3 Typical Performance Curves

Data for performance curves are characterized, not 100% tested.

Figure 1-1: Drain Current vs. V_DS at T_J: This graph shows the relationship between Drain Current (I_D) and Drain-to-Source Voltage (V_DS) at various Junction Temperatures (T_J) from -55°C to 175°C, with Gate-Source Voltage (V_GS) held constant at 20V.
Figure 1-2: Drain Current vs. V_DS at V_GS: This graph illustrates Drain Current (I_D) versus Drain-to-Source Voltage (V_DS) for different Gate-Source Voltages (V_GS) ranging from 6V to 20V, at a Junction Temperature (T_J) of 25°C.
Figure 1-3: Drain Current vs. V_DS at V_GS: Similar to Figure 1-2, but presented for a Junction Temperature (T_J) of 150°C.
Figure 1-4: Drain Current vs. V_DS at V_GS: Similar to Figure 1-2, but presented for a Junction Temperature (T_J) of 175°C.
Figure 1-5: R_DS(on) vs. Junction Temperature: This plot shows the normalized Drain-to-Source on Resistance (R_DS(on)) as a function of Junction Temperature (T_J). The resistance is normalized to V_GS = 20V, I_D = 40A, and 25°C, with separate curves for V_GS = 18V and V_GS = 20V.
Figure 1-6: Gate Charge Characteristics: This graph plots Gate-to-Source Voltage (V_GS) against Gate Charge (Q_G) under specific test conditions (I_GS = 1 mA, I_DS = 40 A, V_DS = 470 V).
Figure 1-7: Capacitance vs. Drain-to-Source Voltage: This log-log plot displays Input Capacitance (C_iss), Output Capacitance (C_oss), and Reverse Transfer Capacitance (C_rss) as a function of Drain-to-Source Voltage (V_DS). Test conditions include f = 200 kHz, V_AC = 25 mV, and V_GS = 0V.
Figure 1-8: Output Charge vs. Drain-to-Source Voltage: This log-log graph illustrates Output Charge versus Drain-to-Source Voltage (V_DS).
Figure 1-9: I_D vs. V_DS 3rd Quadrant Conduction: This graph shows Drain Current (I_D) versus Drain-to-Source Voltage (V_DS) in the third quadrant (negative V_DS and negative I_D) for various Gate-Source Voltages (V_GS) from -5V to +20V, at a Junction Temperature (T_J) of 25°C.
Figure 1-10: I_D vs. V_DS 3rd Quadrant Conduction: Similar to Figure 1-9, but presented for a Junction Temperature (T_J) of 150°C.
Figure 1-11: Switching Energy E_on vs. V_DS & I_D: This plot shows the Turn-on Switching Energy (E_on) as a function of Drain-to-Source Voltage (V_DS) for different Drain Currents (I_D) of 30A, 50A, and 70A, with an external Gate Resistance (R_G) of 4Ω.
Figure 1-12: Switching Energy E_off vs. V_DS & I_D: This plot shows the Turn-off Switching Energy (E_off) as a function of Drain-to-Source Voltage (V_DS) for different Drain Currents (I_D) of 30A, 50A, and 70A, with an external Gate Resistance (R_G) of 4Ω.
Figure 1-13: Switching Energy vs. R_G: This graph illustrates Total Switching Energy (E_tot), Turn-on Energy (E_on), and Turn-off Energy (E_off) as a function of external Gate Resistance (R_G), under conditions of V_DS = 470V and I_D = 50A.
Figure 1-14: Switching Energy vs. Junction Temperature: This graph displays Total Switching Energy (E_tot), Turn-on Energy (E_on), and Turn-off Energy (E_off) as a function of Junction Temperature (T_J), under conditions of V_DS = 470V, I_D = 50A, and R_G = 4Ω.
Figure 1-15: Threshold Voltage vs. Junction Temperature: This plot shows the Gate-Source Threshold Voltage (V_GS(th)) as a function of Junction Temperature (T_J), for the condition V_GS = V_DS and I_D = 4 mA.
Figure 1-16: Forward Safe Operating Area (SOA): This log-log graph depicts the Forward Safe Operating Area, showing Drain Current (I_D) versus Drain-to-Source Voltage (V_DS). It indicates that the linear operation region is not characterized.
Figure 1-17: Maximum Transient Thermal Impedance: This log-log plot shows the transient thermal impedance (Z_θJC) as a function of Pulse Duration (seconds) for various duty cycles (D) and a single pulse condition. A note explains how to calculate peak junction temperature (T_J) using P_DM, Z_θJC, and case temperature (T_C).
Figure 1-18: Switching Waveform: This diagram illustrates the idealized switching waveforms for Drain-Source Voltage (V_DS) and Gate-Source Voltage (V_GS) over time, indicating key switching time parameters: t_d(on) (turn-on delay), t_r (rise time), t_d(off) (turn-off delay), and t_f (fall time).

Package Specification

2.1 Package Outline Drawing

The following figure illustrates the TO-263-7L XL package outline. The drawing provides Top View, Side View, Bottom View, and End View perspectives, detailing dimensions and features like lead pitch (e), overall width (E), and thermal pad dimensions.

Symbol	Description	Min. (mm)	Max. (mm)
N	Number of leads	7	—
e	Pitch	1.27 BSC	—
A	Overall height	4.30	4.70
A1	Seating plane height	—	0.25
A2	Seating plane to lead	2.20	2.60
b	Lead width	0.52	0.72
b1	—	0.60	0.80
c	Lead thickness	0.42	0.62
c2	Thermal pad thickness	1.07	1.47
L	Lead length	4.55	4.95
L1	Tab length	0.87	1.27
L2	Foot length	2.48	2.88
D	Molded body length	9.05	9.45
D1	Thermal pad length	7.58	7.98
E	Total width	9.80	10.20
E1	Thermal pad width step back	6.30	6.70
E2	Thermal pad width	7.80	8.20
Ø	Lead foot angle	0°	8°

Note: Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic dimension. Theoretically exact value shown without tolerances.

2.2 Recommended Land Pattern

The following figure and table illustrate the recommended land pattern for PCB layout for this device.

Figure 2-2: Recommended Land Pattern: This diagram shows the recommended footprint for the TO-263-7L XL package, including pad dimensions (X1, X2, Y1, Y2, C1, C2, G1, G2) and silk screen markings for component placement.

Symbol	Description	Min. (mm)	Nom. (mm)	Max. (mm)
E	Contact pitch	1.27 BSC	—	—
X2	Center pad width	—	—	8.30
Y2	Center pad length	—	—	8.45
C1	Contact pad spacing	—	6.45	—
C2	Contact pad spacing	—	4.30	—
X1	Contact pad width (X7)	—	—	0.80
Y1	Contact pad length (X7)	—	—	2.90
G1	Contact pad to center pad (X7)	3.88	—	—
G2	Contact pad to contact pad (X6)	0.47	—	—

Notes:

Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic dimension. Theoretically exact value shown without tolerances.
For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process.

Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Revision	Date	Description
A	09/2024	Initial revision

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