Gowin PSRAM Memory Interface HS IP User Guide
IPUG943-1.4, 2025-07-04
1 About This Manual
This user guide provides descriptions of the Gowin PSRAM Memory Interface HS IP's structure, port definitions, timing, configuration, and reference designs. It aims to help users quickly understand the product's features, characteristics, and usage methods. The guide primarily focuses on the single-channel configuration, with notes for dual-channel usage. Software interface screenshots are based on version 1.9.11.03, and may differ slightly from future versions.
1.1 Manual Content
Covers IP structure, port descriptions, timing, configuration, and reference designs.
1.2 Related Documents
Available for download on the Gowin Semiconductor website (www.gowinsemi.com.cn):
- DS117, GW1NR Series FPGA Product Datasheet
- DS861, GW1NSR Series FPGA Product Datasheet
- DS821, GW1NS Series FPGA Product Datasheet
- DS100, GW1N Series FPGA Product Datasheet
- DS102, GW2A Series FPGA Product Datasheet
- DS226, GW2AR Series FPGA Product Datasheet
- DS961, GW2ANR Series FPGA Product Datasheet
- DS971, GW2AN-18X & 9X Device Datasheet
- DS976, GW2AN-55 Device Datasheet
- SUG100, Gowin Cloud Software User Guide
1.3 Terms and Abbreviations
| Term/Abbreviation | Full Name | Meaning |
|---|---|---|
| 2CH | 2 Channels | Dual Channel |
| GSR | Global System Reset | Global System Reset |
| HS | Horizontal Sync | Horizontal Sync |
| IP | Intellectual Property | Intellectual Property |
| LUT | Look-up Table | Look-up Table |
| PSRAM | Pseudo Static Random Access Memory | Pseudo Static Random Access Memory |
| RAM | Random Access Memory | Random Access Memory |
1.4 Technical Support and Feedback
For any questions or suggestions during use, please contact Gowin Semiconductor:
- Website: www.gowinsemi.com.cn
- E-mail: support@gowinsemi.com
- Tel: +86 755 8262 0391
2 Overview
The Gowin PSRAM Memory Interface HS IP is a general-purpose PSRAM high-speed memory interface IP that complies with the PSRAM standard protocol. This IP includes the PSRAM memory control logic (Memory Controller Logic) and the corresponding physical interface (PHY) design. It provides users with a generic command interface to interconnect with PSRAM memory chips and fulfill user access requirements.
| Gowin PSRAM Memory Interface HS IP | Description |
|---|---|
| Logic Resources | See Table 3-1. |
| Deliverables | |
| Design Files | Verilog (encrypted) |
| Reference Design | Verilog |
| TestBench | Verilog |
| Test Flow | |
| Synthesis Software | GowinSynthesis |
| Application Software | Gowin Software (V1.9.8Beta and above) |
Note: Chip support information can be found on the Gowin Semiconductor website.
3 Key Features and Performance
3.1 Key Features
- Supports PSRAM chip models: W955D8MKY-61
- Supports memory data path widths: 8, 16, 24, and 32 bits
- Supports x8 memory chip width
- Programmable burst length: 16, 32, 64, 128
- Clock ratio: 1:2
- Initial latency: 6
- Fixed latency mode support
- Power-down option
- Configurable drive strength
- Configurable self-refresh region
- Configurable refresh rate
- Single-channel and dual-channel operation modes available
3.2 Operating Frequency and Bandwidth Efficiency
The Gowin PSRAM Memory Interface HS IP supports the following data rates and efficiencies:
- Maximum operating frequency: 166MHz. Actual maximum frequency may vary due to FPGA device performance differences.
- Burst length 128: Bandwidth efficiency 76%.
- Burst length 64: Bandwidth efficiency 61%.
- Burst length 32: Bandwidth efficiency 44%.
- Burst length 16: Bandwidth efficiency 28%.
3.3 Resource Utilization
The Gowin PSRAM Memory Interface HS IP is implemented in Verilog and is applicable to the Gowin Little Bee, Chenxi, and other Gowin FPGA families. Resource utilization for the GW1NR-9 family is shown in Table 3-1. For verification on other Gowin FPGAs, please refer to future releases.
| DQ_WIDTH | LUT | REGS | I/O | fMAX | Device Series | Speed Grade |
|---|---|---|---|---|---|---|
| 16(x8) | 1004 | 620 | 29 | 333Mbps | GW1NR-9 | C6/15 |
Note: In Table 3-1, the Gowin PSRAM Memory Interface HS IP is configured with a user address width of 21 bits and a PSRAM WITDH of x8, with a burst length of 128. Resource utilization will increase slightly when using the dual-channel PSRAM IP.
4 Functional Description
4.1 Overall Structure
The basic structure of the Gowin PSRAM Memory Interface HS IP is shown in Figure 4-1. It mainly includes modules such as Memory Controller Logic and Physical Interface. The User Design in Figure 4-1 represents the user's design that needs to connect to the external PSRAM chip within the FPGA.
Figure 4-1 Gowin PSRAM Memory Interface HS IP Block Diagram
[Diagram: A block diagram showing the FPGA connected to the PSRAM via the Memory Controller Logic and Physical Interface. Signals like clk, rst_n, addr, cmd, cmd_en, wr_data, data_mask, rd_data, rd_data_valid, clk_out, init_calib are shown between the User Design and the Memory Controller Logic. Signals like O_psram_ck, O_psram_ck_n, O_psram_cs_n, O_psram_reset_n, IO_psram_dq, IO_psram_rwds are shown between the Physical Interface and the PSRAM.]
4.2 Memory Controller Logic
The Memory Controller Logic is the logic module of the Gowin PSRAM Interface HS IP, located between the User Design and the PHY. It receives commands, addresses, and data from the user interface and stores them in a specific order according to certain logic. When the user sends write, read, or other commands and addresses, the Memory Controller Logic sorts and reorganizes them to form data that meets the PSRAM protocol. During write operations, the Memory Controller Logic reorganizes and buffers the data to meet the initial latency requirements between commands and data. During read operations, it samples and reorganizes the returned data to recover the correct data.
4.3 PHY
The PHY defines the physical layer and interface between the Memory Controller Logic and the external PSRAM. It receives commands, addresses, and data from the Memory Controller Logic and provides signals that meet timing and order requirements to the PSRAM interface. The basic structure of the PHY, as shown in Figure 4-3, includes four modules: initialization module, data path, command/address control path, and I/O logic module.
Figure 4-2 PSRAM Memory Controller Logic Block Diagram
[Diagram: A block diagram illustrating the PSRAM Memory Controller Logic with modules for CMD, WR_Data, and RD_Data.]
Figure 4-3 PSRAM PHY Block Diagram
[Diagram: A block diagram of the PSRAM PHY showing modules for Initialization, Data Path, Command/Address Control Path, and I/O Logic.]
4.3.1 Initialization Unit
The initialization module is responsible for PSRAM power-on initialization and read calibration. After all initialization and read calibration are completed, the 'init_calib' signal transitions from low to high, indicating the completion of the entire initialization process.
Power-on Initialization
According to PSRAM protocol standards, initialization, including reset, mode register configuration, and read calibration, must be performed on the PSRAM chip after power-on.
4.3.2 Data Path Unit
The data path handles both write and read data operations.
4.3.3 Command/Address Control Path Unit
The command/address control path is a unidirectional path that receives command and address signals from the Memory Controller Logic. It works with the data path to process write/read data delay parameters and sends commands to the I/O logic module.
4.3.4 I/O Logic Unit
The I/O logic module is primarily responsible for clock domain conversion of data, commands, and addresses passed through the data path and command/address path.
4.4 Main Functions
The PSRAM Memory Interface HS IP supports the following functions:
- PSRAM chip initialization
- Sending addresses and commands
- Writing data
- Reading data
4.4.1 Initialization
Read calibration must be performed on the PSRAM before normal read/write operations. Therefore, upon power-on, the PHY performs initialization and read calibration on the PSRAM. After initialization, it returns an 'init_calib' signal indicating completion. For single-channel PSRAM IP, two PSRAM chips are initialized simultaneously. For dual-channel IP, each PSRAM chip is initialized independently, and the completion signals are sent to the user accordingly. The operation completion signal is returned to the user after initialization, as shown in Figure 4-4.
Figure 4-4 Initialization Completion Signal Timing Diagram
[Diagram: Timing diagram showing the 'init_calib' signal transitioning high after initialization is complete, synchronized with the clock.]
4.4.2 Sending Addresses and Commands
Users can send operation commands and addresses through user ports such as 'addr', 'cmd', and 'cmd_en'.
- addr: Address data port. The IP uses data bit extension to increase bandwidth. When using multiple PSRAM chips, the IP treats multiple PSRAM chips as a single PSRAM during access. Users do not need to worry about address width changes when selecting single or multiple PSRAM chips. For single-channel IP driving two PSRAM chips, one address stores two bytes. For continuous read/write operations, the address increment is half the burst length.
- cmd: Command data port.
- cmd_en: Address and command enable signal, active high.
- Dual-channel PSRAM HS IP operates similarly to single-channel PSRAM HS IP, but the command and address for each channel are independent and require separate control signals.
In application, there is a mapping relationship between the user interface address bus and the physical memory's ROW, Upper Column, and Lower Column. In this design, the arrangement follows the order of ROW-Upper Column-Lower Column for addressing, as shown in Figure 4-5. Users only need to provide the address, without worrying about the mapping relationship.
Figure 4-5 Row-Column Addressing Scheme
[Diagram: Illustrates the mapping of user address to PSRAM Row, Upper Column, and Lower Column addresses.]
The commands that can be sent via the 'cmd' port are shown in Table 4-1.
| Command | cmd |
|---|---|
| Read | 1'b0 |
| Write | 1'b1 |
The timing relationship between commands, addresses, and enable signals at the user interface is shown in Figure 4-6. When 'cmd_en' is high, 'cmd' and 'addr' are valid.
Figure 4-6 Command, Address, and Enable Signal Timing Diagram
[Diagram: Timing diagram showing 'cmd_en' enabling 'cmd' and 'addr' signals.]
4.4.3 Writing Data
Users can send write data through user ports like 'wr_data' and 'data_mask' to the Gowin PSRAM Memory Interface HS IP. The write data is processed and then sent to the PSRAM chip.
- wr_data: Write data port.
- data_mask[1]: Write mask port.
Note: Refer to "Data Mask (data_mask)" for usage instructions.
There can be various timing scenarios between the write data channel and the command channel. The following illustrates a burst length of 16.
For dual-channel PSRAM IP, the write operation mode is the same as single-channel PSRAM IP. However, the data ports for dual-channel PSRAM IP are independent and require separate write data.
Figure 4-7 Write Data Port Timing Diagram
[Diagram: Timing diagram showing 'wr_data' and 'data_mask' signals during a write operation.]
When the user configures a burst length of 32, the write data occupies 8 clock cycles, as shown in Figure 4-8.
Figure 4-8 Write Data Timing Diagram for Burst Length 32
[Diagram: Timing diagram showing write data transfer for a burst length of 32.]
When the user configures a burst length of 64, the write data occupies 16 clock cycles, as shown in Figure 4-9.
Figure 4-9 Write Data Timing Diagram for Burst Length 64
[Diagram: Timing diagram showing write data transfer for a burst length of 64.]
When the user configures a burst length of 128, the write data occupies 32 clock cycles, as shown in Figure 4-10.
Figure 4-10 Write Data Timing Diagram for Burst Length 128
[Diagram: Timing diagram showing write data transfer for a burst length of 128.]
Data Mask (data_mask)
For data that the user does not need to write, the 'data_mask' signal can be used for data masking. Each bit of 'data_mask' controls one byte of 'wr_data'. A high level is effective. The mapping is as follows: 'data_mask[0]' controls 'wr_data[7:0]', 'data_mask[1]' controls 'wr_data[15:8]', 'data_mask[2]' controls 'wr_data[23:16]', and so on.
As shown in Figure 4-11, when writing data with 'wr_data[15:0]=16'hcdef', the written 16'hcdef is not returned during reading. This is because the 16'hcdef was written to a position in PSRAM that did not overwrite the original data. 16'hxxxx represents the data before write masking.
Figure 4-11 Data Mask and Read/Write Data Relationship Timing Diagram
[Diagram: Timing diagram illustrating the relationship between data_mask and read/write data.]
4.4.4 Reading Data
Users can read data returned by the PSRAM through the user ports 'rd_data' and 'rd_data_valid'.
- rd_data: Port for returning read data.
- rd_data_valid: Signal indicating the validity of read data. When high, it indicates that the returned 'rd_data' is valid.
- There are various timing scenarios between the read data channel and the command channel. The following illustrates a burst length of 16.
- For dual-channel PSRAM IP, the read operation mode is the same as single-channel PSRAM IP. However, the data ports for dual-channel PSRAM IP are independent and require separate reception of 'rd_data_valid' signals and 'rd_data'.
Figure 4-12 Read Data Port Timing Diagram
[Diagram: Timing diagram showing 'rd_data' and 'rd_data_valid' signals during a read operation.]
When the user configures a burst length of 32, the read data occupies 8 clock cycles, as shown in Figure 4-13.
Figure 4-13 Read Data Timing Diagram for Burst Length 32
[Diagram: Timing diagram showing read data transfer for a burst length of 32.]
When the user configures a burst length of 64, the read data occupies 16 clock cycles, as shown in Figure 4-14.
Figure 4-14 Read Data Timing Diagram for Burst Length 64
[Diagram: Timing diagram showing read data transfer for a burst length of 64.]
When the user configures a burst length of 128, the read data occupies 32 clock cycles, as shown in Figure 4-15.
Figure 4-15 Read Data Timing Diagram for Burst Length 128
[Diagram: Timing diagram showing read data transfer for a burst length of 128.]
5 Port List
For single-channel selection, the IO ports of the Gowin PSRAM Memory Interface HS IP are listed in Table 5-1.
| Signal | Width | Direction | Description |
|---|---|---|---|
| User Interface | |||
| addr | ADDR_WIDTH | Input | Address input |
| cmd | 1 | Input | Command channel |
| cmd_en | 1 | Input | Command and address enable signal: 0: Invalid, 1: Valid |
| rd_data | 4*DQ_WIDTH | Output | Read data channel |
| rd_data_valid | 1 | Output | rd_data valid signal: 0: Invalid, 1: Valid |
| wr_data | 4*DQ_WIDTH | Input | Write data channel |
| data_mask | MASK_WIDTH | Input | Mask signal for wr_data |
| clk | 1 | Input | Reference input clock, typically from an onboard crystal oscillator. |
| init_calib | 1 | Output | Initialization completion signal |
| clk_out | 1 | Output | Clock for user logic design, frequency is half of Memory Clk. |
| rst_n | 1 | Input | User input reset signal: 0: Active, 1: Inactive |
| memory_clk | 1 | Input | Input clock for the PSRAM chip, typically a high-speed clock from a PLL multiplier, or can be used without a PLL. |
| pll_lock | 1 | Input | If memory_clk is from a PLL multiplier, connect to the PLL's pll_lock pin. If not using a PLL, connect to 1'b1. |
| PSRAM Interface | |||
| O_psram_cs_n | CS_WIDTH | Output | Chip select, active low. |
| O_psram_ck | CS_WIDTH | Output | Clock signal provided to PSRAM. |
| O_psram_ck_n | CS_WIDTH | Output | Differential signal pair with O_psram_ck. |
| O_psram_reset_n | CS_WIDTH | Output | PSRAM reset signal. |
| IO_psram_dq | DQ_WIDTH | Bidirection | PSRAM data. |
| IO_psram_rwds | RWDS_WIDTH | Bidirection | PSRAM data strobe and mask signal. |
For dual-channel selection, the IO ports of the Gowin PSRAM Memory Interface HS IP are listed in Table 5-2.
| Signal | Width | Direction | Description |
|---|---|---|---|
| User Interface | |||
| addr0 | ADDR_WIDTH | Input | Channel 0 address input |
| addr1 | ADDR_WIDTH | Input | Channel 1 address input |
| cmd0 | 1 | Input | Channel 0 command channel |
| cmd1 | 1 | Input | Channel 1 command channel |
| cmd_en0 | 1 | Input | Channel 0 command and address enable signal: 0: Invalid, 1: Valid |
| cmd_en1 | 1 | Input | Channel 1 command and address enable signal: 0: Invalid, 1: Valid |
| rd_data0 | [31:0] | Output | Channel 0 read data |
| rd_data1 | [31:0] | Output | Channel 1 read data |
| rd_data_valid0 | 1 | Output | Channel 0 rd_data valid signal: 0: Invalid, 1: Valid |
| rd_data_valid1 | 1 | Output | Channel 1 rd_data valid signal: 0: Invalid, 1: Valid |
| wr_data0 | [31:0] | Input | Channel 0 write data |
| wr_data1 | [31:0] | Input | Channel 1 write data |
| data_mask0 | [3:0] | Input | Mask signal for Channel 0 wr_data |
| data_mask1 | [3:0] | Input | Mask signal for Channel 1 wr_data |
| init_calibo | 1 | Output | Channel 0 initialization completion signal |
| init_calib1 | 1 | Output | Channel 1 initialization completion signal |
| clk | 1 | Input | Reference input clock, typically from an onboard crystal oscillator. |
| memory_clk | 1 | Input | Input clock for the PSRAM chip, typically a high-speed clock from a PLL multiplier, or can be used without a PLL. |
| pll_lock | 1 | Input | If memory_clk is from a PLL multiplier, connect to the PLL's pll_lock pin. If not using a PLL, connect to 1'b1. |
| clk_out | 1 | Output | Clock for user logic design, frequency is half of Memory Clk. |
| rst_n | 1 | Input | User input reset signal: 0: Active, 1: Inactive |
| PSRAM Interface | |||
| O_psram_cs_n | [1:0] | Output | Chip select, active low. |
| O_psram_ck | [1:0] | Output | Clock signal provided to PSRAM. |
| O_psram_ck_n | [1:0] | Output | Differential signal pair with O_psram_ck. |
| O_psram_reset_n | [1:0] | Output | PSRAM reset signal. |
| IO_psram_dq | [15:0] | Bidirection | PSRAM data. |
| IO_psram_rwds | [1:0] | Bidirection | PSRAM data strobe and mask signal. |
6 Parameter Configuration
The Gowin PSRAM Memory Interface HS IP supports PSRAM devices. Users need to configure various static and timing parameters according to their design requirements. Table 6-1 lists the static parameter options for the Gowin PSRAM Memory Interface.
| Name | Description | Options |
|---|---|---|
| Memory TYPE | PSRAM chip model | W955D8MBYA, Custom |
| CLk Ratio | Clock ratio between PSRAM PHY and internal logic (e.g., user cannot operate). | 1:2 |
| Memory Clock | Desired chip operating frequency | 50MHz~166MHz |
| Channel Number | Single-channel and dual-channel selection | 1 channel: Single-channel 2 channel: Dual-channel |
| Psram Width | PSRAM chip DQ width | 8 |
| Dq Width | User-defined data width | 8, 16, 24, 32, 40, 48, 56, 64 |
| Addr Width | Chip address width; user should fill in according to the specific chip. | 21 |
| Data Width | User data width | 4*Dq Width |
| CS Width | Chip select width | Dq Width/Psram Width |
| Mask Width | Mask width | Data Width/Psram Width |
| Burst Mode | Data burst length | 16, 32, 64, 128 |
| Burst Num | Number of burst data | Burst Mode/4 |
| Fixed Latency Enable | Fixed latency enable | "Fixed" |
| Initial Latency | Initial latency value | 6 |
| Drive Strength | Drive strength | 35, 50, 100, 200 |
| Deep Power Down | Power-down option | "OFF", "ON" |
| Hybrid Sleep Mode | Hybrid sleep mode | "OFF", "ON" |
| Refresh Rate | Refresh rate | "normal", "faster" |
| PASR | Self-refresh region | full, bottom_1/2, bottom_1/4, bottom_1/8, top_1/2, top_1/4, top_1/8 |
| Shift Delay | Sampling window adjustment | Generally, use default values. If errors occur during high/low temperature tests, adjust as needed. Range: 0~255. |
7 Interface Configuration
Users can invoke and configure the Gowin PSRAM Memory Interface HS IP through the IP Core Generator in the Gowin Semiconductor Cloud Source software. This section introduces the main configuration interfaces, configuration flow, and the meaning of each configuration option, using the W955D8MBYA PSRAM memory chip as an example.
1. Open IP Core Generator
After creating the project, click the "Tools" tab in the upper left corner, then click "IP Core Generator" to open the Gowin IP core generation tool, as shown in Figure 7-1.
Figure 7-1 Open IP Core Generator
[Diagram: Screenshot of the Gowin FPGA Designer interface, highlighting the path to open the IP Core Generator.]
2. Open PSRAM Memory Interface HS IP Core
Click on the "Memory Control" option, then double-click "PSRAM Memory Interface HS" to open the configuration interface for the PSRAM Memory Interface HS IP core, as shown in Figure 7-2.
Figure 7-2 Open PSRAM Memory Interface HS IP Core
[Diagram: Screenshot of the IP Core Generator interface showing the selection of the PSRAM Memory Interface HS IP core.]
3. PSRAM Memory Interface HS IP Core Interface Diagram
The left side of the configuration interface displays the interface schematic of the PSRAM Memory Interface HS IP core, as shown in Figure 7-3. The right side of the interface diagram shows the PSRAM Memory Controller and the user interface. Users connect their custom design to the PSRAM Memory Interface HS IP to send and receive commands and data. The left side shows the PHY (Physical Interface) and its connection to the memory chip, allowing users to access data by connecting to their desired memory chip. The signal width and number of signals in the interface diagram will change based on the user's different configuration information.
Figure 7-3 IP Core Interface Diagram
[Diagram: A detailed view of the PSRAM Memory Interface HS IP core's interface connections, showing user-side and PHY-side connections.]
4. Configure Basic Information
The upper part of the configuration interface is the basic project information configuration. This example uses the GW1NR-9 chip model with the MBGA100PF package.
- "Module Name": This is the name of the top-level file generated for the project, defaulting to "PSRAM_Memory_Interface_HS_Top". Users can modify it.
- "File Name": This is the folder where the IP core files are generated, containing the necessary files for the PSRAM Memory Interface HS IP. The default is "psram_memory_interface_hs". Users can change the path.
- "Create In": This option specifies the path for generating the IP core folder. Users can modify this path.
Figure 7-4 Basic Information Configuration Interface
[Diagram: Screenshot of the basic information configuration section within the IP Core Generator.]
5. Interface Parameter Configuration Description
Refer to Section 6 "Parameter Configuration" for descriptions of interface parameter configurations.
Note: For PSRAM HS 2CH IP, Dq Width and Psram Width are fixed. For a four-chip device, the top-level file will instantiate two channels, forming a dual-channel transmission, with two chips per channel.
8 Reference Design
To help users quickly get familiar with and use the Gowin PSRAM Memory Interface HS IP, a simple reference design is provided. The basic structure of the reference design is shown in Figure 8-1.
Figure 8-1 Reference Design Block Diagram
[Diagram: A block diagram of the reference design, showing the psram_syn_top module, psram_test module, Key_debounce module, and the Gowin PSRAM Interface IP.]
In the reference design, the 'psram_syn_top' module is the top-level module. Its ports connect to the input reference clock, external reset signals, etc. Port connections are shown in Table 8-1. The 'psram_test' module generates the address, data, and read/write commands required for the Gowin PSRAM Interface HS IP and can be synthesized. The 'Key_debounce' module is a debouncing module used to eliminate signal jitter caused by key presses or DIP switch controls.
| Name | Description |
|---|---|
| clk | Input reference clock, default 50MHz. |
| rst_n | Input reset signal. |
| init_calib | IP initialization success signal; high indicates successful initialization. |
| error | Data check bit signal; high indicates a read data check error. |
The PSRAM_test module generates 'n' continuous write signals and data, then performs 'n' continuous read operations on the written data, followed by data verification. After verification, it repeats the previous write-read operations. In this reference design, the memory chip selected is W955D8MBYA, configured with Burst Mode 128 and DQ width of 16 bits.
Figure 8-2 shows partial signal simulation waveforms between the 'psram_test' and PSRAM Memory Interface HS IP ports.
Figure 8-2 Partial Signal Simulation Waveforms of psram_test
[Diagram: Simulation waveforms showing key signals like clk, rst_n, init_done, addr, cmd, wr_data, rd_data, etc., from the psram_test module.]
9 File Delivery
The Gowin PSRAM Memory Interface HS IP delivery package mainly includes three parts: documentation, design source code, and reference design.
9.1 Documentation
The folder mainly contains the user guide PDF document.
| Name | Description |
|---|---|
| IPUG943, Gowin PSRAM Memory Interface HS IP User Guide | Gowin PSRAM Memory Interface IP User Manual, i.e., this manual. |
9.2 Design Source Code (Encrypted)
The encrypted code folder contains the RTL encrypted code of the Gowin PSRAM Memory Interface HS IP, used with the GUI to generate the required IP core with Gowin Cloud Source software.
| Name | Description |
|---|---|
| PSRAM_TOP.V | IP core top-level file, providing interface information to the user, not encrypted. |
| psram_code.v | GOWIN PSRAM Memory Interface HS IP design RTL source file, encrypted. |
| psram_define.v | Gowin PSRAM memory controller parameter definition module, generated by the user via GUI configuration, not encrypted. |
| psram_local_define.v | Gowin PSRAM memory controller parameter definition processing module, encrypted. |
| psram_param.v | Gowin PSRAM memory controller parameter configuration module, generated by the user via GUI configuration, not encrypted. |
| psram_local_param.v | Gowin PSRAM memory controller parameter processing module, processes parameters passed by the GUI, encrypted. |
9.3 Reference Design
The Ref. Design folder mainly contains the netlist file of the Gowin PSRAM Memory Interface HS IP, reference design, constraint files, debouncing module, top-level file, and project folder, etc.
| Name | Description |
|---|---|
| psram_syn_top.v | Reference design top-level module. |
| key_debounce.v | Key debouncing module. |
| psram_test.v | Test stimulus generation module. |
| PSRAM_Memory_Interface_HS.vo | Gowin PSRAM Memory Interface HS IP netlist file. |
| psram.cst | PSRAM project physical constraint file. |
| psram.sdc | PSRAM project timing constraint file. |
| psram.gao | Capture PSRAM chip data. |
| PSRAM_Memory_Interface_HS | PSRAM HS IP project folder. |
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