DisplayPort Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

Updated for Intel® Quartus® Prime Design Suite: 21.4
IP Version: 21.0.0

1. DisplayPort Intel FPGA IP Design Example Quick Start Guide

The DisplayPort Intel® FPGA IP design examples for Intel Agilex™ F-tile devices feature a simulating testbench and a hardware design that supports compilation and hardware testing.

The DisplayPort Intel FPGA IP offers the following design examples:

DisplayPort SST parallel loopback without a Pixel Clock Recovery (PCR) module at static rate

When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

Note: Intel Quartus® Prime 21.4 software version only supports Preliminary Design Example for Simulation, Synthesis, Compilation, and Timing analysis purposes. Hardware functionality is not fully verified.

Development Stages:

Design Example Generation → Compilation (Simulator) → Functional Simulation

Design Example Generation → Compilation (Quartus Prime) → Hardware Testing

Related Information:

DisplayPort Intel FPGA IP User Guide
Migrating to Intel Quartus Prime Pro Edition

1.1. Directory Structure

The directory structure for the design example includes folders for Quartus, hwtest, rtl, and simulation. Key files include IP variations (.ip), Verilog/VHDL files (.sv, .v), simulation scripts (.sh), and testbench components.

Design Example Components:

Folders	Files
rtl/core	dp_core.ip, dp_rx.ip, dp_tx.ip
rtl/rx_phy	dp_gxb_rx/ ((DP PMA UX building block), dp_rx_data_fifo.ip, rx_top_phy.sv
rtl/tx_phy	dp_gxb_rx/ ((DP PMA UX building block), dp_tx_data_fifo.ip, dp_tx_data_fifo.ip

1.2. Hardware and Software Requirements

Hardware:

Intel Agilex I-Series Development Kit

Software:

Intel Quartus Prime
Synopsys* VCL Simulator

1.3. Generating the Design

Use the DisplayPort Intel FPGA IP parameter editor in Intel Quartus Prime software to generate the design example.

Design Generation Flow:

Start Parameter Editor → Specify IP Variation and Select Device → Select Design Parameters → Specify Example Design → Initiate Design Generation

Select Tools > IP Catalog, and select Intel Agilex F-tile as the target device family.
In the IP Catalog, locate and double-click DisplayPort Intel FPGA IP. The New IP Variation window appears.
Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
You may select a specific Intel Agilex F-tile device in the Device field, or keep the default Intel Quartus Prime software device selection.
Click OK. The parameter editor appears.
Configure the desired parameters for both TX and RX.
On the Design Example tab, select DisplayPort SST Parallel Loopback Without PCR.
Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example. You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
Click Generate Example Design.

1.4. Simulating the Design

The DisplayPort Intel FPGA IP design example testbench simulates a serial loopback design from a TX instance to an RX instance. An internal video pattern generator module drives the DisplayPort TX instance and the RX instance video output connects to CRC checkers in the testbench.

Design Simulation Flow:

Change to <Simulator> Directory → Run <Simulation Script> → Analyze Results

Go to Synopsys simulator folder and select VCS.
Run simulation script: Source vcs_sim.sh
The script performs Quartus TLG, compiles and runs the testbench in the simulator.
Analyze the result. A successful simulation ends with Source and Sink SRC comparison.

Example successful output:

# SINK CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c,
# SOURCE CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c,
# Pass: Test Completed

1.5. Compiling and Simulating the Design

To compile and run a demonstration test on the hardware example design, follow these steps:

Compilation and Simulation Flow:

Compile Design in Quartus Prime Software → Set Up Hardware → Program Device → Test Design in Hardware

Ensure hardware example design generation is complete.
Launch the Intel Quartus Prime Pro Edition software and open <project>/quartus/agi_dp_demo.qpf.
Click Processing > Start Compilation.
Wait until Compilation completes.

Note: The design example does not functionally verify Preliminary Design Example on hardware in this Quartus release.

Related Information:

Intel Agilex I-Series FPGA Development Kit User Guide

1.6. DisplayPort Intel FPGA IP Design Example Parameters

The following parameters can be configured for the DisplayPort Intel FPGA IP Design Example for Intel Agilex F-tile Devices:

Parameter	Value	Description
Available Design Example	- None - DisplayPort SST Parallel Loopback without PCR	Select the design example to be generated. - None: No design example is available for the current parameter selection. - DisplayPort SST Parallel Loopback without PCR: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source without a Pixel Clock Recovery (PCR) module when you turn on the Enable Video Input Image Port parameter.
Design Example Files	Simulation (On, Off) Synthesis (On, Off)	Turn on Simulation to generate the necessary files for the simulation testbench. Turn on Synthesis to generate the necessary files for Intel Quartus Prime compilation and hardware design.
Generated HDL Format	Verilog, VHDL	Select your preferred HDL format for the generated design example fileset. Note: This option only determines the format for the generated top level IP files. All other files (e.g., example testbenches and top level files for hardware demonstration) are in Verilog HDL format.
Target Development Kit	- No Development Kit - Intel Agilex I-Series Development Kit - Custom Development Kit	Select the board for the targeted design example. - No Development Kit: Excludes all hardware aspects; IP core sets all pin assignments to virtual pins. - Intel Agilex I-Series FPGA Development Kit: Automatically selects the project's target device to match the device on this development kit. You may change the target device using the Change Target Device parameter if your board revision has a different device variant. The IP core sets all pin assignments according to the development kit. Note: Preliminary Design Example is not functionally verified on hardware in this Quartus release. - Custom Development Kit: Allows the design example to be tested on a third-party development kit with an Intel FPGA. You may need to set the pin assignments on your own.
Target Device	Change Target Device (On, Off)	Turn on this option and select the preferred device variant for the development kit.

2. Parallel Loopback Design Examples

The DisplayPort Intel FPGA IP design examples demonstrate parallel loopback from DisplayPort RX instance to DisplayPort TX instance without a Pixel Clock Recovery (PCR) module at static rate.

Design Example	Designation	Data Rate	Channel Mode	Loopback Type
DisplayPort SST parallel loopback without PCR	DisplayPort SST	HBR3	Simplex	Parallel without PCR

2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback Design Features

The SST parallel loopback design examples demonstrate the transmission of a single video stream from DisplayPort sink to DisplayPort source without Pixel Clock Recovery (PCR) at static rate.

Features of the Intel Agilex F-tile DisplayPort SST Parallel Loopback without PCR:

In this variant, the DisplayPort source's parameter, TX_SUPPORT_IM_ENABLE, is turned on and the video image interface is used.
The DisplayPort sink receives video and/or audio streaming from an external video source such as a GPU and decodes it into a parallel video interface.
The DisplayPort sink video output directly drives the DisplayPort source video interface and encodes to the DisplayPort main link before transmitting to the monitor.
The IOPLL drives both the DisplayPort sink and source video clocks at a fixed frequency.
If DisplayPort sink and source's MAX_LINK_RATE parameter is configured to HBR3 and PIXELS_PER_CLOCK is configured to Quad, the video clock runs at 300 MHz to support 8Kp30 pixel rate (1188 / 4 = 297 MHz).

2.2. Clocking Scheme

The clocking scheme illustrates the clock domains in the DisplayPort Intel FPGA IP design example. The core system includes RX and TX sub-systems, each with PIO, Avalon-MM Interconnect, Debug FIFO, and EDID RAM (for RX) or Debug FIFO (for TX). The RX and TX PHY tops connect to these sub-systems and include Reset Sync and Parallel Data FIFO, connecting to DP RX/TX FGT PMA Building Blocks. The IOPLL IP and Reference and System PLL Clock IP manage the clocking.

Clocking Scheme Signals:

Clock in diagram	Description
SysPLL refclk	F-tile System PLL reference clock. In this design example, system_pll_clk_link and rx/tx refclk_link share the same SysPLL refclk, which is 150 MHz. It must be a free-running clock connected from a dedicated transceiver reference clock pin to the input clock port of Reference and System PLL Clocks IP, before connecting the corresponding output port to DisplayPort Phy Top.
system_pll_clk_link	The minimum System PLL output frequency to support all DisplayPort rates is 320 MHz. This design example uses 900 MHz (highest) output frequency so that SysPLL refclk can be shared with rx/tx refclk_link, which is 150 MHz.
rx_cdr_refclk_link / tx_pll_refclk_link	Rx CDR and Tx PLL Link refclk, fixed to 150 MHz to support all DisplayPort data rates.
rx_ls_clkout / tx_ls_clkout	DisplayPort Link Speed Clock to clock DisplayPort IP core. Frequency equivalent to Data Rate divided by parallel data width. Example: Frequency = data rate / data width = 8.1G (HBR3) / 40bits = 202.5 MHz.

2.3. Simulation Testbench

The simulation testbench simulates the DisplayPort TX serial loopback to RX.

DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block Diagram:

The block diagram shows the Core System (Platform Designer) with RX Sub-System and TX Sub-System. Each sub-system contains Debug FIFO and DisplayPort RX/TX Core. These connect to RX/TX Phy Top which includes Reset Sync and Parallel Data FIFO, connecting to DP RX/TX FGT PMA Building Block. The IOPLL IP and Reference and System PLL Clock IP are central components. The testbench also includes components like Testbench Control and Video Pattern Generation.

Testbench Components:

Component	Description
Video Pattern Generator	Produces configurable color bar patterns. Video format timing can be parameterized.
Testbench Control	Controls the simulation test sequence and generates stimulus signals to the TX core. Reads CRC values from source and sink for comparison.
RX Link Speed Clock Frequency Checker	Verifies if the RX transceiver recovered clock frequency matches the desired data rate.
TX Link Speed Clock Frequency Checker	Verifies if the TX transceiver recovered clock frequency matches the desired data rate.

Testbench Verifications:

Test Criteria	Verification
Link Training at Data Rate HBR3 Read the DPCD registers to check if the DP Status sets and measures both TX and RX Link Speed frequency.	Integrates Frequency Checker to measure the Link Speed clock's frequency output from the TX and RX transceiver.
Run video pattern from TX to RX. Verify the CRC for both source and sink to check if they match	Connects video pattern generator to the DisplayPort Source to generate the video pattern. Testbench control reads out both Source and Sink CRC from DPTX and DPRX registers and compares to ensure both CRC values are identical. Note: To ensure CRC is calculated, you must enable the Support CTS test automation parameter.

3. Document Revision History for the DisplayPort Intel Agilex F-tile FPGA IP Design Example User Guide

Document Version	Intel Quartus Prime Version	IP Version	Changes
2021.12.13	21.4	21.0.0	Initial release.

Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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