Instructions for MICROCHIP models including: 005S SmartFusion 2 and IGLOO 2 Automotive Grade 2 AC-DC Electrical Characteristics, 005S, SmartFusion 2 and IGLOO 2 Automotive Grade 2 AC-DC Electrical Characteristics, IGLOO 2 Automotive Grade 2 AC-DC Electrical Characteristics, Automotive Grade 2 AC-DC Electrical Characteristics, Grade 2 AC-DC Electrical Characteristics, Electrical Characteristics, Characteristics
SmartFusion 2 FPGAs | Microchip Technology
I/O Input voltage for MSIOD/DDRIO I/O Bank. –0.3 2.75 ... LVTTL/LVCMOS 3.3 V DC Input Voltage Specification ... LVCMOS 1.8V DC Output Voltage Specification.
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DocumentDocumentSmartFusion® 2 and IGLOO® 2 Automotive Grade 2 AC/DC Electrical Characteristics INTRODUCTION Microchip's automotive grade SmartFusion® 2 System-on-Chip (SoC) Field Programmable Gate Array (FPGA) and IGLOO® 2 FPGA families offer the best-in-class security, industry leading high reliability and lowest static power in a flash-based fabric. With a strong heritage of supplying to Military and Aviation customers, Microchip automotive grade devices are ideally suited to meet the demands of the automotive industry providing the lowest total-cost-of-ownership. These next-generation devices integrate an industry standard 4-input Lookup Table-based (LUT) FPGA fabric with integrated mathblocks, multiple embedded memory blocks, high-performance SerDes communications interfaces on a single chip with extended temperature support. Automotive grade SmartFusion 2 and IGLOO 2 devices offer up to 90K Logic Elements, up to 5 MB of embedded RAM, up to 4 SerDes lanes, up to 2 PCIe endpoints and integrated hard DDR3 memory controllers with single error correct and double error detect. IGLOO 2 automotive grade devices integrate a high-performance memory subsystem (HPMS) with on-chip flash, 32 kbyte embedded SRAM, and multiple DMA controllers. SmartFusion 2 automotive grade SoC FPGAs provide a low-power real time microcontroller subsystem (MSS) with an embedded ARM® Cortex®-M3 encapsulating the benefits of HPMS along with a rich set of industry standard peripherals including Ethernet, USB, and CAN. SmartFusion 2 and IGLOO 2 FPGAs are the best alternative to ASICs and SRAM based FPGAs with their advantages of Zero FIT reliability, tamper-free advanced security, industry's lowest static power and supply assurance for long product lifetime support. DEVICE STATUS The following table lists the SmartFusion 2 and IGLOO 2 devices that are available. TABLE 1: IGLOO® 2 FPGA AND SMARTFUSION® 2 SOC FPGA DEVICE STATUS Design Security Device Densities Status 005S Production 010TS Production 025TS Production 060TS Production 090TS Production PRODUCT BRIEFS AND PIN DESCRIPTIONS The product brief and pin descriptions are published separately: · IGLOO® 2 FPGA Product Brief · IGLOO® 2 Pin Descriptions · SmartFusion® 2 SoC FPGA Product Brief · SmartFusion® 2 Pin Descriptions 2023 Microchip Technology Inc. and its subsidiaries DS50003487A-page 1 Contents Introduction ..................................................................................................................................................1 Device Status ...............................................................................................................................................1 Product Briefs and Pin Descriptions ............................................................................................................1 1.0 General Specifications .........................................................................................................................3 1.1 Operating Conditions............................................................................................................................................................ 3 1.2 Overshoot/Undershoot Limits............................................................................................................................................... 7 1.3 Thermal Characteristics ....................................................................................................................................................... 7 2.0 Power Consumption ...........................................................................................................................10 2.1 Quiescent Supply Current .................................................................................................................................................. 10 2.2 Programming Currents ....................................................................................................................................................... 11 3.0 Average Fabric Temperature and Voltage Derating Factors .............................................................13 4.0 Timing Model .....................................................................................................................................14 5.0 User I/O Characteristics .....................................................................................................................16 5.1 Input Buffer and AC Loading .............................................................................................................................................. 16 5.2 Output Buffer and AC Loading ........................................................................................................................................... 16 5.3 Tristate Buffer and AC Loading .......................................................................................................................................... 18 5.4 I/O Speeds ...................................................................................................................................................................... 19 5.5 Detailed I/O Characteristics ....................................................................................................................................... 21 5.6 Single-Ended I/O Standards............................................................................................................................................... 22 5.7 Memory Interface and Voltage Referenced I/O Standards ................................................................................................ 38 5.8 Differential I/O Standards ................................................................................................................................................... 54 5.9 I/O Register Specifications ................................................................................................................................................. 64 5.10 DDR Module Specification ............................................................................................................................................... 68 6.0 Logic Element Specifications .............................................................................................................74 6.1 4-input LUT (LUT-4) ........................................................................................................................................................... 74 6.2 Sequential Module.............................................................................................................................................................. 75 7.0 Switching Characteristics ...................................................................................................................77 7.1 Global Resource Characteristics ........................................................................................................................................ 77 7.2 FPGA Fabric SRAM ........................................................................................................................................................... 78 7.3 Embedded NVM (eNVM) Characteristics ......................................................................................................................... 94 7.4 Crystal Oscillator ................................................................................................................................................................ 94 7.5 Clock Conditioning Circuits (CCC) ................................................................................................................................... 95 7.6 JTAG .............................................................................................................................................................................. 100 7.7 Power-up to Functional Times.......................................................................................................................................... 100 7.8 DEVRST_N Characteristics ............................................................................................................................................ 102 7.9 DEVRST_N to Functional Times ...................................................................................................................................... 102 7.10 System Controller SPI Characteristics ....................................................................................................................... 105 7.11 Mathblock Timing Characteristics .................................................................................................................................. 106 7.12 Flash*Freeze Timing Characteristics ............................................................................................................................ 108 7.13 DDR Memory Interface Characteristics ......................................................................................................................... 108 7.14 SFP Transceiver Characteristics .................................................................................................................................... 109 7.15 PCIe Electrical and Timing AC and DC Characteristics ................................................................................................. 109 7.16 SmartFusion 2 Specifications ......................................................................................................................................... 111 7.17 SRAM PUF ..................................................................................................................................................................... 115 7.18 Non-Deterministic Random Bit Generator Characteristics ............................................................................................. 116 7.19 Cryptographic Block Characteristics .............................................................................................................................. 116 7.20 CAN Controller Characteristics ...................................................................................................................................... 117 7.21 USB Characteristics ....................................................................................................................................................... 117 7.22 SerDes Protocol Compliance ........................................................................................................................................ 118 7.23 MMUART Characteristics ............................................................................................................................................... 118 7.24 IGLOO 2 Specifications .................................................................................................................................................. 118 Appendix A: List of Changes ...................................................................................................................121 The Microchip WebSite ............................................................................................................................123 Customer Change Notification Service ....................................................................................................123 Customer Support ....................................................................................................................................123 Worldwide Sales and Service ..................................................................................................................125 DS50003487A-page 2 2023 Microchip Technology Inc. and its subsidiaries 1.0 GENERAL SPECIFICATIONS 1.1 Operating Conditions Stresses beyond those listed in Table 1-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the recommended operating conditions specified in Table 1-1 is not implied. The following tables list the operating conditions details. TABLE 1-1: ABSOLUTE MAXIMUM RATINGS Limits Symbol Parameter Min Max Units Notes VDD DC core supply voltage. Must always power this 0.3 1.32 V -- pin. VPP Power supply for charge pumps (for normal 0.3 3.63 V -- operation and programming). Must always power this pin. MSS_MDDR_PLL_VDDA Analog power pad for MDDR PLL 0.3 3.63 V -- HPMS_MDDR_PLL_VDDA Analog power pad for MDDR PLL 0.3 3.63 V -- FDDR_PLL_VDDA Analog power pad for FDDR PLL 0.3 3.63 V -- PLL0_PLL1_MSS_MDDR_VDDA Analog power pad for MDDR PLL 0.3 3.63 V -- PLL0_PLL1_HPMS_MDDR_VDDA Analog power pad for MDDR PLL 0.3 3.63 V -- CCC_XX[01]_PLL_VDDA Analog power pad for PLL05 0.3 3.63 V -- SERDES_[01]_PLL_VDDA High supply voltage for PLL SERDES[01] 0.3 3.63 V -- SERDES_[01]_L[0123]_VDDAPLL Analog power for SERDES[01] PLL lane0 to lane3. 0.3 2.75 V -- This is a +2.5 V SERDES internal PLL supply. SERDES_[01]_L[0123]_VDDAIO TX/RX analog I/O voltage. Low voltage power for 0.3 1.32 V -- the lanes of SERDESIF0. This is a +1.2 V SERDES PMA supply. SERDES_[01]_VDD PCIe/PCS power supply 0.3 1.32 V -- VDDIx DC FPGA I/O buffer supply voltage for MSIO I/O 0.3 3.63 V -- Bank DC FPGA I/O buffer supply voltage for MSIOD/DDRIO I/O Banks 0.3 2.75 V -- VI I/O Input voltage for MSIO I/O Bank 0.3 3.63 V -- I/O Input voltage for MSIOD/DDRIO I/O Bank 0.3 2.75 V -- VPPNVM Analog sense circuit supply of embedded 0.3 3.63 V -- nonvolatile memory (eNVM). Must be shorted to VPP. TSTG TJ Note 1: Storage temperature 65 150 °C 1 Junction temperature -- 145 °C -- For flash programming and retention maximum limits, refer to Table 1-3. For recommended operating con- ditions, refer to Table 1-2. 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 3 TABLE 1-2: RECOMMENDED OPERATING CONDITIONS Symbol Parameter Conditions Min Typ Tj Operating Junction Automotive -40 25 Temperature Grade 2 Programming Junction -- Temperature -- 0 25 -40 25 VDD DC core supply voltage. -- Must always power this pin. 1.14 1.2 VPP Power Supply for Charge Pumps (for Normal Operation and Programming) for 010, 025, and 060 Devices 2.5V Range 3.3V Range 2.375 2.5 3.15 3.3 Power Supply for Charge Pumps (for Normal Operation and Programming) for 090 devices 3.3V Range 3.15 3.3 MSS_MDDR_PLL_VDDA Analog power pad for MDDR PLL 2.5V Range 2.375 2.5 3.3V Range 3.15 3.3 HPMS_MDDR_PLL_VDDA Analog power pad for MDDR PLL 2.5V Range 2.375 2.5 3.3V Range 3.15 3.3 FDDR_PLL_VDDA Analog power pad for FDDR PLL 2.5V Range 2.375 2.5 3.3V Range 3.15 3.3 PLL0_PLL1_MSS_MDDR_VDDA Analog power pad for MDDR PLL 2.5V Range 2.375 2.5 3.3V Range 3.15 3.3 PLL0_PLL1_HPMS_MDDR_VDDA Analog power pad for MDDR PLL 2.5V Range 2.375 2.5 3.3V Range 3.15 3.3 CCC_XX[01]_PLL_VDDA Analog power pad for PLL0-5 2.5V Range 2.375 2.5 3.3V Range 3.15 3.3 SERDES_[01]_PLL_VDDA High supply voltage for 2.5V PLL SERDES[01] Range 2.375 2.5 3.3V Range 3.15 3.3 Max Units Notes 125 °C -- 85 °C -- 100 °C -- 1.26 V -- 2.625 V -- 3.45 V -- 3.45 V -- 2.625 V -- 3.45 V -- 2.625 V -- 3.45 V -- 2.625 V -- 3.45 V -- 2.625 V -- 3.45 V -- 2.625 V -- 3.45 V -- 2.625 V -- 3.45 V -- 2.625 V 2 3.45 V 2 DS50003487A-page 4 2023 Microchip Technology Inc. and its subsidiaries TABLE 1-2: RECOMMENDED OPERATING CONDITIONS (CONTINUED) Symbol Parameter Conditions Min Typ Max Units Notes SERDES_[01]_L[0123]_VDDAPLL Analog power for -- SERDES[01] PLL lanes 0-3. It is a +2.5V SERDES internal PLL supply. 2.375 2.5 2.625 V -- SERDES_[01]_L[0123]_VDDAIO TX/RX analog I/O -- voltage. Low voltage power for the lanes of SERDESIF0. It is a +1.2V SERDES PMA supply. 1.14 1.2 1.26 V -- SERDES_[01]_VDD PCIe/PCS Power supply -- 1.14 1.2 1.26 V -- VDDIx 1.2V DC supply voltage -- 1.14 1.2 1.26 V -- 1.5V DC supply voltage -- 1.425 1.5 1.575 V -- 1.8V DC supply voltage -- 1.71 1.8 1.89 V -- 2.5V DC supply voltage -- 2.375 2.5 2.625 V -- 3.3V DC supply voltage -- (3.3V only available in MSIO) 3.15 3.3 3.45 V -- LVDS differential I/O -- 2.375 2.5 3.45 V -- BLVDS, MLVDS, Mini- -- LVDS, RSDS differential I/O 2.375 2.5 2.625 V -- LVPECL differential I/O -- 3.15 3.3 3.45 V -- VREFx Reference Voltage -- Supply for FDDR (Bank0) and MDDR(Bank5) 0.49 × 0.5 × 0.51 × V -- VDDIx VDDIx VDDIx VPPNVM Analog sense circuit supply of embedded nonvolatile memory (eNVM). Must be shorted to VPP 2.5V Range 3.3V Range 2.375 2.5 2.625 V -- 3.15 3.3 3.45 V -- Note 1: 2: 3: Programming at this temperature range is available only with VPP in 3.3V Range Power supply ramps must all be strictly monotonic, without plateaus. PLL supply voltages should be either 2.5V or 3.3V. Mixed voltages are not allowed. 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 5 TABLE 1-3: FPGA OPERATING LIMITS Product Grade Element Programming Operating Temperature Temperature Programming Digest Cycles Temperature Digest Retention Cycle (Biased/ Unbiased) Automotive Grade 21, 2 FPGA Min TJ = 0°C Min TJ = -40°C 500 Max TJ = 85°C Max TJ = 125°C Min TJ = -40°C 2000 10 Years Max TJ = 100°C Min TJ = -40°C Min TJ = -40°C 500 Max TJ = 100°C Max TJ = 125°C Min TJ = -40°C 2000 10 Years Max TJ = 100°C 1. The retention specification is defined as the total number of programming and digest cycles. For example, 10 years of retention after 500 programming cycles. If your product qualification requires accelerated programming cycles, contact Technical Support at http://www.microchip.com/support for Product Quality and Reliability report. 2. Programming at Industrial temperature range is available only with VPP in 3.3V Range TABLE 1-4: EMBEDDED FLASH LIMITS Product Grade Element Automotive Grade 2 Embedded flash Programming Temperature Min TJ = -40°C Max TJ = 125°C Maximum Operating Temperature Programming Cycles Retention (Biased/Unbiased) Min TJ = -40°C Max TJ = 125°C < 10,000 cycles per pages, up to one million cycles per eNVM array 10 Years TABLE 1-5: DEVICE STORAGE TEMPERATURE AND RETENTION Product Grade Storage Temperature (Tstg) Retention Automotive Grade 2 Min TJ = -40°C Max TJ = 125°C 10 Years TABLE 1-6: Tj (C) 90 HIGH TEMPERATURE DATA RETENTION (HTR) LIFETIME HTR Lifetime1 (Years) 20.0 95 20.0 100 20.0 105 17.0 110 15.0 115 13.0 120 11.5 125 10.0 130 8.0 135 6.0 140 4.5 145 3.0 150 1.5 Note 1: HTR Lifetime is the period during which a verify failure is not expected due to flash leakage. DS50003487A-page 6 2023 Microchip Technology Inc. and its subsidiaries The following figure shows the high temperature data retention. FIGURE 1-1: HIGH TEMPERATURE DATA RETENTION (HTR) 1.2 Overshoot/Undershoot Limits For AC signals, the input signal may undershoot during transitions to -1.0V for no longer than 10% or the period. The current during the transition must not exceed 100 mA. For AC signals, the input signal may overshoot during transitions to VCCI +1.0V for no longer than 10% of the period. The current during the transition must not exceed 100 mA. Note: The above specification does not apply to the PCI standard. The IGLOO 2 and SmartFusion 2 PCI I/Os are compliant to the PCI standard including the PCI overshoot/undershoot specifications. 1.3 Thermal Characteristics 1.3.1 INTRODUCTION The temperature variable in the Microchip's Designer software refers to the junction temperature, not the ambient, case, or board temperatures. This is an important distinction because dynamic and static power consumption will cause the chip's junction temperature to be higher than the ambient, case, or board temperatures. Equations 1 through 3 give the relationship between thermal resistance, temperature gradient, and power. EQUATION 1-1: THERMAL RESISTANCE JA = -T---J----P-----T----A- EQUATION 1-2: TEMPERATURE GRADIENT JB = -T---J----P-----T----B- EQUATION 1-3: POWER JC = -T---J----P-----T----C- 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 7 where JA = Junction-to-air thermal resistance JB = Junction-to-board thermal resistance JC = Junction-to-case thermal resistance TJ = Junction temperature TA = Ambient temperature TB = Board temperature (measured 1.0 mm away from the package edge) TC = Case temperature P = Total power dissipated by the device The following table lists the package thermal resistance. TABLE 1-7: PACKAGE THERMAL RESISTANCE Product M2GL/M2S JA Still Air 1.0 m/s 2.5 m/s 005 FGG484 19.36 15.81 14.63 VFG256 41.30 38.16 35.30 VFG400 20.19 16.94 15.41 010 FGG484 18.22 14.83 13.62 VFG256 37.36 34.26 31.45 VFG400 19.40 15.75 14.22 025 FGG484 17.03 13.66 12.45 VFG256 33.85 30.59 27.85 VFG400 18.36 14.89 13.36 060 FGG484 15.40 12.06 10.85 VFG400 17.45 14.01 12.47 FGG676 15.49 12.21 11.06 090 FGG484 14.64 11.37 10.16 FGG676 14.52 11.19 10.37 JB 9.74 28.41 8.86 JC 5.27 3.94 4.95 8.83 4.92 24.84 7.89 8.11 4.22 7.66 4.18 21.63 6.13 7.12 3.41 6.14 3.15 6.22 2.69 7.07 3.87 5.43 2.77 6.17 3.24 Units °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W 1.3.2 THETA-JA Junction-to-ambient thermal resistance (JA) is determined under standard conditions specified by JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used with caution, but it is useful for comparing the thermal performance of one package to another. The maximum power dissipation allowed is calculated using the following equation. EQUATION 1-4: POWER DISSIPATION Maximum Power Allowed = -T---J---(-M----A---X---)----J---A-T----A---(--M---A----X---) DS50003487A-page 8 2023 Microchip Technology Inc. and its subsidiaries The absolute maximum junction temperature is 125°C. The following equation shows a sample calculation of the absolute maximum power dissipation allowed for the M2GL060TS-1FGG484 package at Automotive Grade 2 temperature and in still air, where: JA = 15.4°C/W (taken from Table 1-7). TA = 105°C EQUATION 1-5: POWER Maximum Power Allowed = -1---2---5-1---°5--C-.--4----°--C--1--/-0-W--5----°--C--- = 1.3 W The power consumption of a device can be calculated using the Microchip's power calculator. The device's power consumption must be lower than the calculated maximum power dissipation by the package. If the power consumption is higher than the device's maximum allowable power dissipation, a heat sink can be attached on top of the case, or the airflow inside the system must be increased. 1.5.3 THETA-JB Junction-to-board thermal resistance (JB) measures the ability of the package to dissipate heat from the surface of the chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance from junction to board uses an isothermal ring cold plate zone concept. The ring cold plate is simply a means to generate an isothermal boundary condition at the perimeter. The cold plate is mounted on a JEDEC standard board with a minimum distance of 5.0 mm away from the package edge. 1.5.4 THETA-JC Junction-to-case thermal resistance (JC) measures the ability of a device to dissipate heat from the surface of the chip to the top or bottom surface of the package. It is applicable for packages used with external heat sinks. Constant temperature is applied to the surface in consideration and acts as a boundary condition. This only applies to situations where all or nearly all of the heat is dissipated through the surface in consideration. 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 9 2.0 POWER CONSUMPTION 2.1 Quiescent Supply Current The following tables list the Quiescent Supply Current details. TABLE 2-1: QUIESCENT SUPPLY CURRENT CHARACTERISTICS Modes and Configurations Power Supplies/Blocks Non-Flash*Freeze Mode Flash*Freeze Mode Notes FPGA Core ON OFF -- VDD / SERDES_[01]_VDD ON ON 1 VPP / VPPNVM ON ON -- MDDR_PLL_VDDA CCC_XX[01]_PLL_VDDA PLL0_PLL1_MDDR_VDDA FDDR_PLL_VDDA 0V 0V -- SERDES_[01]_PLL_VDDA 0V 0V 3 SERDES_[01]_L[0123]_VDDAPLL / VDD_2V5 ON ON 3 SERDES_[01]_L[0123]_VDDAIIO ON ON 3 VDDIx ON ON 2, 4 VREFx ON ON -- MSSDDR CLK 32 kHz 32 kHz -- RAM ON Sleep state -- HPMS Controller 50 MHz 50 MHz -- 50 MHz Oscillator (enable/disable) Enabled Disabled -- 1 MHz Oscillator (enable/disable) Disabled Disabled -- Crystal Oscillator (enable/disable) Disabled Disabled -- Note 1: 2: 3: 4: SERDES_[01]_VDD Power Supply is shorted to VDD. VDDIx has been set to ON for test conditions as described. Banks on the east side should always be powered with the appropriate VDDI Bank supplies. For details on bank power supplies, refer to the "Recommendation for Unused Bank Supplies" table in the AN4153: Board and Layout Design Guidelines for SmartFusion® 2 SoC and IGLOO® 2 FPGAs. SerDes and DDR blocks to be unused. No Differential (that is to say, LVDS) I/O's or ODT attributes to be used. DS50003487A-page 10 2023 Microchip Technology Inc. and its subsidiaries TABLE 2-2: SMARTFUSION® 2 AND IGLOO® 2 QUIESCENT SUPPLY CURRENT TYPICAL PROCESS 005 010 025 060 090 Parameter Modes Conditions VDD = 1.2V VDD = 1.2V VDD = 1.2V VDD = 1.2V VDD = 1.2V Units IDC1 IDC2 Non- Typical 6.2 Flash*Freeze (TJ = 25°C) Automotive 60.9 Grade 2 (TJ = 125°C) Flash*Freeze Typical 1.4 (TJ = 25°C) Automotive 33.5 Grade 2 (TJ = 125°C) 6.9 73.0 2.6 55.6 8.9 106.4 3.7 74.2 15.3 215.4 5.0 98.5 15.4 mA 217.5 mA 5.1 mA 99.5 mA TABLE 2-3: SMARTFUSION® 2 AND IGLOO® 2 QUIESCENT SUPPLY CURRENT WORST-CASE PROCESS 005 010 025 060 090 Parameter Modes Conditions VDD=1.26V VDD=1.26V VDD=1.26V VDD=1.26V VDD=1.26V Units IDC1 Non- Automotive 114.9 151.5 227.4 438.8 443.1 mA Flash*Freeze Grade 2 (TJ = 125°C) IDC2 Flash*Freeze Automotive 81.1 127.2 144.2 193.1 195.0 mA Grade 2 (TJ = 125°C) 2.2 Programming Currents The following tables represent programming, verify and Inrush currents for SmartFusion 2 SoC and IGLOO 2 FPGA devices. TABLE 2-4: CURRENTS DURING PROGRAM CYCLE, 0°C < = TJ <= 85°C, TYPICAL PROCESS Power Supplies Voltage (V) 005 010 025 060 090 Units VDD 1.26 46 53 55 30 42 mA VPP 3.46 8 11 6 9 12 mA VPPNVM 3.46 1 2 2 3 3 mA VDDI 2.62 31 16 17 12 12 mA 3.46 62 31 36 12 17 mA Number of banks 7 8 8 10 9 -- TABLE 2-5: CURRENTS DURING VERIFY CYCLE, 0°C <= TJ <= 85°C, TYPICAL PROCESS Power Supplies Voltage (V) 005 010 025 060 090 Units VDD 1.26 44 53 55 33 41 mA VPP 3.46 6 5 3 8 11 mA VPPNVM 3.46 1 0 0 0 1 mA 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 11 TABLE 2-5: VDDI CURRENTS DURING VERIFY CYCLE, 0°C <= TJ <= 85°C, TYPICAL PROCESS 2.62 31 16 17 12 11 mA 3.46 61 32 36 12 17 mA Number of banks 7 8 8 10 9 -- TABLE 2-6: INRUSH CURRENTS AT POWER UP, -40°C <= TJ <=125°C, TYPICAL PROCESS Power Supplies Voltage (V) 005 010 025 060 090 Units VDD 1.26 36 53 78 54 98 mA VPP 3.46 35 57 50 14 36 mA VDDI 2.62 134 141 161 106 283 mA Number of banks 7 8 8 10 9 -- DS50003487A-page 12 2023 Microchip Technology Inc. and its subsidiaries 3.0 AVERAGE FABRIC TEMPERATURE AND VOLTAGE DERATING FACTORS The following table list the average fabric temperature and voltage derating details. TABLE 3-1: AVERAGE TEMPERATURE AND VOLTAGE DERATING FACTORS FOR FABRIC TIMING DELAYS--(NORMALIZED TO TJ = 125°C, WORST-CASE VDD = 1.14V) Core Voltage VDD (V) 1.14 1.2 1.26 Junction Temperature (°C) 55°C 40°C 0°C 0.91 0.91 0.93 0.82 0.83 0.84 0.75 0.75 0.77 25°C 0.94 0.85 0.77 70°C 0.96 0.87 0.79 85°C 0.97 0.87 0.80 100°C 0.98 0.88 0.81 125°C 1.00 0.90 0.75 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 13 4.0 TIMING MODEL The following figure shows the timing model. FIGURE 4-1: TIMING MODEL E Combinational Cell Y I/O Module (Non-Registered) G F Combinational Cell Y LVDS Buffer I/O Module (Registered) A DDR3 B D Q Input Clock C LVCMOS 2.5V I/O Module D (Non-Registered) Register Cell L D Q Combinational Cell H Y Buffer I/O Module (Non-Registered) I LVCMOS 2.5V Output drive strength = 16mA MSIO IO Bank Buffer Combinational Cell J Y I/O Module (Non-Registered) K LVCMOS 2.5V Output drive strength = 8mA MSIO IO Bank M Combinational Cell Y I/O Module (Non-Registered) P LVCMOS 1.5V Output drive strength =12mA DDRIO IO Bank Combinational Cell M Y Register Cell L D Q Buffer I/O Module (Registered) N D O Q SSTL2 ClassI LVDS Input Clock C LVCMOS 2.5V Input Clock C LVCMOS 2.5V TABLE 4-1: TIMING MODEL PARAMETERS Index Parameter Description A tPY Propagation Delay of DDR3 Receiver B tICLKQ Clock-to-Q of the Input Data Register tISUD Setup Time of the Input Data Register Speed Grade 1 1.672 0.165 0.369 Units ns ns ns Notes See Table 5-55 for more information See Table 5-93 for more information See Table 5-93 for more information DS50003487A-page 14 2023 Microchip Technology Inc. and its subsidiaries C tRCKH Input High Delay for Global Clock 1.55 ns See Table 7-1 - Table 7-2 for more information tRCKL Input Low Delay for Global Clock 0.861 ns See Table 7-1 - Table 7-2 for more information D tPY Input Propagation Delay of LVDS Receiver 3.061 ns See Table 5-70 for more information E tDP Propagation Delay of a three input AND 0.217 ns See Table 6-1 for more Gate information F tDP Propagation Delay of a OR Gate 0.17 ns See Table 6-1 for more information G tDP Propagation Delay of a LVDS Transmitter 2.299 ns See Table 5-71 for more information H tDP Propagation Delay of a three input XOR 0.236 ns See Table 6-1 for more Gate information I tDP Propagation Delay of LVCMOS 2.5 V 2.717 ns See Table 5-17 for more Transmitter, Drive strength of 16mA on information the MSIO Bank J tDP Propagation Delay of a two input NAND 0.17 Gate ns See Table 6-1 for more information K tDP Propagation Delay of LVCMOS 2.5 V 2.594 ns See Table 5-17 for more Transmitter, Drive strength of 8mA on the information MSIO Bank L tCLKQ Clock-to-Q of the Data Register 0.112 ns See Table 5-93 for more information tSUD Setup Time of the Data Register 0.262 ns See Table 5-93 for more information M tDP Propagation Delay of a two input AND 0.17 gate ns See Table 6-1 for more information N tOCLKQ Clock-to-Q of the Output Data Register 0.272 ns See Table 5-94 for more information tOSUD Setup Time of the Output Data Register 0.196 ns See Table 5-94 for more information O tDP Propagation Delay of SSTL2, Class I 2.283 ns See Table 5-48 for more Transmitter on the MSIO Bank information P tDP Propagation Delay of LVCMOS 1.5 V 3.703 ns See Table 5-30 for more Transmitter, Drive strength of 12mA, fast information slew on the DDRIO Bank 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 15 5.0 USER I/O CHARACTERISTICS There are three types of I/Os supported in the IGLOO 2 FPGA and SmartFusion 2 SoC FPGA families: MSIO, MSIOD, and DDRIO I/O banks. The I/O standards supported by the different I/O banks is described in the "I/Os" section of the IGLOO 2 FPGA and SmartFusion 2 SoC FPGA Fabric User Guide. 5.1 Input Buffer and AC Loading The following figure shows the input buffer AC loading. FIGURE 5-1: INPUT BUFFER AC LOADING tPY tPYS PAD IN Y tPY = MAX(tPY(R), tPY(F)) tPYS = MAX(tPYS(R), tPYS(F)) VIH Vtrip IN Y GND 50% tPY (R) tPYS (R) Vtrip VDD VIL 50% tPY (F) tPYS (F) 5.2 Output Buffer and AC Loading FIGURE 5-2: OUTPUT BUFFER AC LOADING DS50003487A-page 16 2023 Microchip Technology Inc. and its subsidiaries Single-Ended I/O Test Setup tDP D OUT PAD tDP = MAX(tDP(R), tDP(F)) Cload HSTL/PCI Test Setup tDP VTT/VDDI D OUT PAD tDP = MAX(tDP(R), tDP(F)) Rtt_test Cload Voltage-Referenced, Singled-Ended I/O Test Setup tDP VTT D OUT PAD Rtt_test Cload tDP = MAX(tDP(R), tDP(F)) Differential I/O Test Setup tDP OUT PAD_P D PAD_N tDP = MAX(tDP(R), tDP(F)) tPY PAD_P IN PAD_N tPY = MAX(tPY(R), tPY(F)) tPYS = MAX(tPYS(R), tPYS(F)) 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 17 5.3 Tristate Buffer and AC Loading The tristate path for enable path loadings is described in the respective specifications. The methodology of characterization is illustrated by the enable path test point shown in the following figure. FIGURE 5-3: TRISTATE BUFFER FOR ENABLE PATH TEST POINT tZL, tZH, tHZ, tLZ E PAD Rent to VDDI for tZL, tLZ D OUT Rent to GND for tZH, tHZ Cent tZL, tLZ, tZH, tHZ Data (D) Enable (E) PAD 50% tZL 10% VDDI 50% tHZ 90% VDDI 50% tZH 90% VDDI 50% tLZ 10% VDDI DS50003487A-page 18 2023 Microchip Technology Inc. and its subsidiaries 5.4 I/O Speeds TABLE 5-1: MAXIMUM DATA RATE SUMMARY FOR WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS Single-Ended I/O MSIO MSIOD DDRIO Units PCI 3.3V 560 -- -- Mbps LVTTL 3.3V 540 -- -- Mbps LVCMOS 3.3V 540 -- -- Mbps LVCMOS 2.5V 360 370 360 Mbps LVCMOS 1.8V 260 360 360 Mbps LVCMOS 1.5V 140 190 210 Mbps LVCMOS 1.2V 100 140 180 Mbps LPDDR LVCMOS 1.8V Mode -- -- 360 Mbps Voltage-Referenced I/O LPDDR -- -- 360 Mbps HSTL1.5V -- -- 360 Mbps SSTL 2.5V 450 480 360 Mbps SSTL 1.8V 600 Mbps Voltage-Referenced I/O SSTL 1.5V -- -- 600 Mbps Differential I/O LVPECL (input only) 810 -- -- Mbps LVDS 3.3V 480 480 -- Mbps LVDS 2.5V 480 480 -- Mbps RSDS 460 480 -- Mbps BLVDS 450 -- -- Mbps MLVDS 450 -- -- Mbps Mini-LVDS 460 480 -- Mbps 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 19 TABLE 5-2: MAXIMUM FREQUENCY SUMMARY FOR WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS Single-Ended I/O MSIO MSIOD DDRIO Units PCI 3.3V 280 -- -- MHz LVTTL 3.3V 270 -- -- MHz LVCMOS 3.3V 270 -- -- MHz LVCMOS 2.5V 180 185 180 MHz LVCMOS 1.8V 130 180 180 MHz LVCMOS 1.5V 70 95 105 MHz LVCMOS 1.2V 50 70 90 MHz LPDDR - LVCMOS 1.8V mode -- -- 180 MHz Voltage-Referenced I/O LPDDR -- -- 180 MHz HSTL1.5V SSTL 2.5V SSTL 1.8V SSTL 1.5V -- -- 180 MHz 225 240 180 MHz -- -- 300 MHz -- -- 300 MHz Differential I/O LVPECL (input only) 405 -- -- MHz LVDS 3.3V 240 240 -- MHz LVDS 2.5V 240 240 -- MHz RSDS 230 240 -- MHz BLVDS 225 -- -- MHz MLVDS 225 -- -- MHz Mini-LVDS 230 240 -- MHz DS50003487A-page 20 2023 Microchip Technology Inc. and its subsidiaries 5.5 Detailed I/O Characteristics TABLE 5-3: INPUT CAPACITANCE Symbol Definition Conditions Min Max Units CIN Input Capacitance -- -- 10 pF IIL (dc) Input Current LOW (Applicable to HSTL/SSTL inputs only)1 VDDI = 2.5V VDDI = 1.8V -- 400 µA -- 500 µA VDDI = 1.5V -- 600 µA Input Current LOW -- (Applicable to all other digital inputs) -- 10 µA IIH (dc) Input Current HIGH (Applicable to HSTL/SSTL inputs only)1 VDDI = 2.5V VDDI = 1.8V -- 400 µA -- 500 µA VDDI = 1.5V -- 600 µA Input Current HIGH -- (Applicable to all other digital inputs) TRAMPIN2 Input Ramp Time -- (Applicable to all digital inputs) -- 10 µA -- 50 ns 1. Applicable when IO pair is programmed with HSTL/SSTL IO type on IOP and an un-terminated IO type (LVCMOS, and so on) on ION pad. 2. Voltage ramp must be monotonic. TABLE 5-4: I/O WEAK PULL-UP/PULL-DOWN RESISTANCE VALUES FOR DDRIO, MSIO, AND MSIOD BANKS--MINIMUM AND MAXIMUM WEAK PULL-UP/PULL-DOWN RESISTANCE VALUES AT VOH/VOL LEVEL VDDI Domain DDRIO I/O Bank MSIO I/O Bank MSIOD I/O Bank 3.3V 2.5V 1.8V 1.5V 1.2V R(WEAK PULL-UP) at VOH () R(WEAK PULL-DOWN) at VOL () R(WEAK PULL-UP) at VOH () R(WEAK PULL-DOWN) at VOL () R(WEAK PULL-UP) at VOH () R(WEAK PULL-DOWN) at VOL () Min Max Min Max Min Max Min Max Min Max Min Max Notes N/A N/A N/A N/A 9.9K 17.1K 9.98K 17.5K N/A N/A N/A N/A 10K 17.8K 9.98K 18K 10K 17.6K 10.1K 18.4K 9.6K 16.6K 9.5K 16.4K 1, 2 10.3K 19.1K 10.3K 19.5K 10.4K 19.1K 10.4K 20.4K 9.7K 17.3K 9.7K 17.1K 1, 2 10.6K 20.2K 10.6K 21.1K 10.7K 20.4K 10.8K 22.2K 9.9K 18K 9.8K 17.6K 1, 2 11.1K 22.7K 11.2K 24.6K 11.3K 23.2K 11.5K 26.7K 10.3K 19.6K 10K 19.1K 1, 2 Note 1: R(WEAK PULL-DOWN) = (VOLspec)/I(WEAK PULL-DOWN MAX) 2: R(WEAK PULL-UP) = (VDDImax - VOHspec)/I(WEAK PULL-UP MIN) 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 21 TABLE 5-5: SCHMITT TRIGGER INPUT HYSTERESIS--HYSTERESIS VOLTAGE VALUE FOR SCHMITT TRIGGER MODE INPUT BUFFERS Input Buffer Configuration Hysteresis Value (Typical, unless otherwise noted) 3.3V LVTTL / LVCMOS / PCI / PCI-X 0.05 × VDDI (Worst-case) 2.5V LVCMOS 0.05 × VDDI (Worst-case) 1.8V LVCMOS 0.1 × VDDI (Worst-case) 1.5V LVCMOS 60 mV 1.2V LVCMOS 20 mV 5.6 Single-Ended I/O Standards 5.6.1 LOW VOLTAGE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (LVCMOS) LVCMOS is a widely used switching standard implemented in CMOS transistors. This standard is defined by JEDEC (JESD 8-5). The LVCMOS standards supported in IGLOO 2 FPGAs and SmartFusion 2 SoC FPGAs are: LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25, and LVCMOS33. 5.6.2 3.3V LVCMOS/LVTTL LVCMOS 3.3V or Low-Voltage Transistor-Transistor Logic (LVTTL) is a general standard for 3.3V applications. 5.6.2.1 Minimum and Maximum AC/DC Input and Output Levels Specification TABLE 5-6: LVTTL/LVCMOS 3.3V DC VOLTAGE SPECIFICATION (APPLICABLE TO MSIO I/O BANK ONLY) Symbol Parameters Conditions Min Typ Max Units LVTTL/LVCMOS 3.3 V Recommended DC Operating Conditions VDDI Supply voltage 3.15 3.3 3.45 V LVTTL/LVCMOS 3.3 V DC Input Voltage Specification VIH (DC) DC input logic High 2.0 -- 3.45 V VIL (DC) IIH (DC)1 IIL (DC)1 DC input logic Low Input current High Input current Low 0.3 -- 0.8 V -- -- -- -- LVCMOS 3.3 V DC Output Voltage Specification VOH2 DC output logic High VOL2 DC output logic Low 2.4 -- -- V -- -- 0.4 V LVTTL 3.3 V DC Output Voltage Specification VOH DC output logic High 2.4 -- -- V VOL DC output logic Low -- -- 0.4 V 1. For more information about input current high (IIH) and input current low (IIL), see Table 5-3. 2. The VOH/VOL test points selected ensure compliance with LVCMOS 3.3V JESD8-B requirements. TABLE 5-7: LVTTL/LVCMOS 3.3V MAXIMUM SWITCHING SPEEDS (APPLICABLE TO MSIO I/O BANK ONLY) Symbol Parameters Conditions Min Typ Max Units LVTTL/LVCMOS 3.3V Maximum Switching Speed Dmax Maximum data rate AC loading: 17 pF load, maximum -- (for MSIO I/O Bank) drive/slew -- 540 Mbps DS50003487A-page 22 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-8: LVTTL/LVCMOS 3.3V AC TEST PARAMETER SPECIFICATIONS (APPLICABLE TO MSIO BANK ONLY) LVTTL/LVCMOS 3.3V AC Test Parameter Specifications Symbol Parameters Conditions Min Typ Max Units Vtrip Measuring/trip point for data path -- 1.4 -- V Rent Cent Cload Resistance for enable path (tZH, tZL, tHZ, tLZ) Capacitive loading for enable path (tZH, tZL, tHZ, tLZ) Capacitive loading for data path (tDP) -- 2k -- -- 5 -- pF -- 5 -- pF TABLE 5-9: LVTTL/LVCMOS 3.3V TRANSMITTER DRIVE STRENGTH SPECIFICATIONS (APPLICABLE TO MSIO BANK1 ONLY) Output Drive Selection VOH (V) VOL (V) IOH (at VOH) mA IOL (at VOL) mA 2 mA 2.4 0.4 2 2 4 mA 2.4 0.4 4 4 8 mA 2.4 0.4 8 8 12 mA 2.4 0.4 12 12 16 mA 2.4 0.4 16 16 20 mA 2.4 0.4 18 18 Note 1: Software Configurator GUI displays the Commercial/Industrial numeric values. The actual drive capability at temperature is defined in Table 5-9. 5.6.2.2 AC Switching Characteristics Worst-case Automotive Grade 2 conditions: TJ = 125°C, VDD = 1.14V, VDDI = 3.15V 5.6.2.2.1 AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-10: LVTTL/LVCMOS 3.3 V RECEIVER CHARACTERISTICS FOR MSIO I/O BANKS (INPUT BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 3.15V LVTTL/LVCMOS 3.3V (for MSIO I/O Bank) On-Die Termination (ODT) in None Speed Grade 1 tPY 2.416 tPYS 2.443 Units ns 5.6.2.2.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-11: LVTTL/LVCMOS 3.3V TRANSMITTER CHARACTERISTICS FOR MSIO I/O BANK (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 3.15V Speed Grade 1 Output Drive Selection 2 mA Slew Control tDP slow 3.515 tZL 3.826 tZH 3.242 tHZ 2.024 tLZ 3.636 Units ns 4 mA slow 2.565 2.948 2.774 3.339 4.896 ns 8 mA slow 2.349 2.568 2.528 5.013 5.329 ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 23 TABLE 5-11: 12 mA 16 mA 20 mA LVTTL/LVCMOS 3.3V TRANSMITTER CHARACTERISTICS FOR MSIO I/O BANK (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 3.15V slow 2.261 2.324 2.386 6.389 6.05 ns slow 2.274 2.287 2.369 6.671 6.256 ns slow 2.372 2.206 2.306 6.976 6.541 ns 5.6.3 2.5V LVCMOS LVCMOS 2.5V is a general standard for 2.5V applications and is supported in IGLOO 2 FPGA and SmartFusion 2 SoC FPGAs in compliance to the JEDEC specification JESD8-5A. 5.6.3.1 Minimum and Maximum AC/DC Input and Output Levels Specification TABLE 5-12: LVCMOS 2.5V DC VOLTAGE SPECIFICATION Symbol Parameters Min Typ LVCMOS 2.5V Recommended DC Operating Conditions VDDI Supply voltage 2.375 2.5 LVCMOS 2.5V DC Input Voltage Specification VIH (DC) DC input logic High (for MSIOD and 1.7 -- DDRIO I/O Bank) VIH (DC) DC input logic High (for MSIO I/O Bank) 1.7 -- VIL (DC) IIH (DC)1 IIL (DC)1 DC input logic Low Input current High Input current Low 0.3 -- -- -- -- -- LVCMOS 2.5V DC Output Voltage Specification VOH2 DC output logic High VOL2 DC output logic Low VDDI 0.4 -- -- -- Max 2.625 2.625 2.75 0.7 -- -- -- 0.4 Units V V V V -- -- V V 1. For more information about input current high (IIH) and input current low (IIL), see Table 5-3. 2. The VOH/VOL test points selected ensure compliance with LVCMOS 2.5V JEDEC8-5A requirements. TABLE 5-13: LVCMOS 2.5V MAXIMUM AC SWITCHING SPEEDS Symbol Parameters Conditions Min Dmax Maximum data rate AC loading: 17 pF load, -- (for DDRIO I/O Bank) maximum drive/slew Dmax Maximum data rate AC loading: 17 pF load, -- (for MSIO I/O Bank) maximum drive/slew Dmax Maximum data rate AC loading: 17 pF load, -- (for MSIOD I/O Bank) maximum drive/slew Typ Max Units -- 360 Mbps -- 360 Mbps -- 370 Mbps TABLE 5-14: LVCMOS 2.5V AC TEST PARAMETERS AND DRIVER IMPEDANCE SPECIFICATIONS Symbols Parameters Min Typ Max Units LVCMOS 2.5V Calibrated Impedance Option Rodt_cal Supported output driver calibrated -- 75, 60, 50, -- impedance 33, 25, 20 (for DDRIO I/O Bank) LVCMOS 2.5V AC Test Parameters Specifications DS50003487A-page 24 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-14: Vtrip Rent Cent Cload LVCMOS 2.5V AC TEST PARAMETERS AND DRIVER IMPEDANCE SPECIFICATIONS Measuring/trip point for data path -- 1.2 -- V Resistance for enable path (tZH, tZL, -- 2k tHZ, tLZ) Capacitive loading for enable path (tZH, -- 5 tZL, tHZ, tLZ) Capacitive loading for data path (tDP) -- 5 -- -- pF -- pF TABLE 5-15: LVCMOS 2.5V TRANSMITTER DRIVE STRENGTH SPECIFICATIONS Output Drive Selection DDRIO I/O Bank MSIO MSIOD (With Software Default I/O Bank I/O Bank Fixed Code) VOH (V) Min VOL (V) IOH (at VOH) IOL (at VOL) Max mA mA 2 mA 2 mA 2 mA 1.7 0.7 2 2 4 mA 4 mA 4 mA 1.7 0.7 4 4 6 mA 6 mA 6 mA 1.7 0.7 6 6 8 mA 8 mA 8 mA 1.7 0.7 8 8 12 mA 12 mA 12 mA 1.7 0.7 12 12 16 mA Note: N/A 16 mA 1.7 0.7 16 16 For board design considerations, output slew rates extraction, detailed output buffer resistances and I/V Curve use the corresponding IBIS models located at: https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/igloo-2-fpgas#Documentation. 5.6.3.2 5.6.3.2.1 AC Switching Characteristics AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-16: LVCMOS 2.5V AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 2.375V LVCMOS 2.5V (for DDRIO I/O Bank) On-Die Termination (ODT) in None Speed Grade 1 tPY 1.903 tPYS 2.021 Units ns LVCMOS 2.5V (for MSIO I/O Bank) None 2.689 2.698 ns LVCMOS 2.5V (for MSIOD I/O Bank) None 2.447 2.46 ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 25 5.6.3.2.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-17: LVCMOS 2.5V AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 2.375V Output Drive Selection Slew Control Speed Grade 1 tDP tZL tZH tHZ tLZ Units LVCMOS 2.5V (for DDRIO I/O Bank with Fixed Code) 2 mA slow 3.967 3.664 3.986 4.172 3.811 ns medium 3.625 3.38 3.647 3.882 3.458 ns medium_fast 3.485 3.259 3.507 3.747 3.327 ns fast 3.458 3.253 3.48 3.74 3.31 ns 4 mA slow 3.371 2.942 3.362 5.148 4.71 ns medium 3.063 2.701 3.059 4.874 4.381 ns medium_fast 2.925 2.566 2.92 4.686 4.248 ns fast 2.91 2.559 2.905 4.683 4.238 ns 6 mA slow 3.189 2.716 3.169 5.56 5.092 ns medium 2.886 2.473 2.876 5.273 4.752 ns medium_fast 2.749 2.355 2.738 5.127 4.167 ns fast 2.731 2.345 2.72 5.115 4.6 ns 8 mA slow 3.132 2.646 3.109 5.686 5.207 ns medium 2.832 2.407 2.82 5.402 4.864 ns medium_fast 2.698 2.292 2.685 5.262 4.732 ns fast 2.684 2.282 2.671 5.252 4.724 ns 12 mA slow 3.013 2.504 2.984 5.918 5.416 ns medium 2.72 2.284 2.707 5.657 5.074 ns medium_fast 2.592 2.176 2.578 5.537 4.949 ns fast 2.58 2.166 2.566 5.529 4.946 ns 16 mA slow 2.936 2.415 2.902 6.136 5.577 ns medium 2.66 2.206 2.645 5.901 5.261 ns medium_fast 2.536 2.102 2.519 5.815 5.142 ns fast 2.523 2.093 2.506 5.81 5.137 ns LVCMOS 2.5V (for MSIO I/O Bank) 2 mA slow 3.933 4.352 4.22 2.358 3.838 ns 4 mA slow 2.905 3.423 3.508 4.681 5.262 ns 6 mA slow 2.687 2.995 3.155 5.561 5.73 ns 8 mA slow 2.594 2.877 3.07 6.602 6.248 ns 12 mA slow 2.623 2.732 2.944 6.974 6.478 ns 16 mA slow 2.717 2.617 2.84 7.455 6.824 ns DS50003487A-page 26 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-17: LVCMOS 2.5V AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 2.375V (CONTINUED) Output Drive Selection Slew Control Speed Grade 1 tDP tZL tZH tHZ tLZ Units LVCMOS 2.5V (for MSIOD I/O Bank) 2 mA slow 2.403 2.922 2.89 5.397 5.202 ns 4 mA slow 1.998 2.446 2.468 5.936 5.665 ns 6 mA slow 1.861 2.329 2.375 6.391 6.068 ns 8 mA slow 1.781 2.145 2.208 6.884 6.44 ns 12 mA slow 1.804 2.039 2.108 7.23 6.685 ns 5.6.4 1.8V LVCMOS LVCMOS 1.8 is a general standard for 1.8V applications and is supported in IGLOO 2 FPGAs and SmartFusion 2 SoC FPGAs in compliance to the JEDEC specification JESD8-7A. 5.6.4.1 Minimum and Maximum AC/DC Input and Output Levels TABLE 5-18: LVCMOS 1.8V DC VOLTAGE SPECIFICATION Symbols Parameters Min Typ Max Recommended DC Operating Conditions VDDI Supply Voltage 1.710 1.8 1.89 LVCMOS 1.8V DC Input Voltage Specification VIH(DC) DC input Logic HIGH (for MSIOD and 0.65 x VDDI -- 1.89 DDRIO I/O Banks) VIH(DC) DC input Logic HIGH (for MSIO I/O 0.65 x VDDI -- 2.75 Bank) VIL(DC) IIH(DC)1 IIL(DC)1 DC input Logic LOW Input Current HIGH Input Current LOW -0.3 -- 0.35 × VDDI -- -- -- -- -- -- LVCMOS 1.8V DC Output Voltage Specification VOH DC output Logic HIGH VDDI - 0.45 -- -- VOL DC output Logic LOW -- -- 0.45 1. For more information about input current high (IIH) and input current low (IIL), see Table 5-3. Units V V V V -- -- V V TABLE 5-19: LVCMOS 1.8V MAXIMUM AC SWITCHING SPEEDS Symbols Parameters Conditions Min LVCMOS 1.8V Maximum AC Switching Speed Dmax Maximum data rate AC loading: 17 pF load, -- (for DDRIO I/O Bank) maximum drive/slew Typ Max -- 360 Units Mbps 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 27 TABLE 5-19: LVCMOS 1.8V MAXIMUM AC SWITCHING SPEEDS (CONTINUED) Dmax Maximum data rate AC loading: 17 pF load, -- (for MSIO I/O Bank) maximum drive/slew -- 260 Dmax Maximum data rate AC loading: 17 pF load, -- (for MSIOD I/O Bank) maximum drive/slew -- 360 Note: Maximum data rate applies for drive strength 8mA and above, all slews Mbps Mbps TABLE 5-20: LVCMOS 1.8V TRANSMITTER DRIVE STRENGTH SPECIFICATIONS Output Drive Selection VOH (V) VOL (V) MSIO I/O Bank MSIOD I/O Bank Min Max IOH (at VOH) mA IOL (at VOL) mA 2 mA 2 mA VDDI 0.45 0.45 2 2 4 mA 4 mA VDDI 0.45 0.45 4 4 6 mA 6 mA VDDI 0.45 0.45 6 6 8 mA 8 mA VDDI 0.45 0.45 8 8 10 mA 10 mA VDDI 0.45 0.45 10 10 12 mA N/A VDDI 0.45 0.45 12 12 TABLE 5-21: Output Drive Selection DDRIO Bank1 2 mA 4 mA 6 mA 8 mA 10 mA 12 mA 16 mA LVCMOS 1.8V TRANSMITTER DRIVE STRENGTH SPECIFICATIONS VOH (V) Min VDDI 0.45 VDDI 0.45 VDDI 0.45 VDDI 0.45 VDDI 0.45 VDDI 0.45 VDDI 0.45 VOL (V) Max 0.45 0.45 0.45 0.45 0.45 0.45 0.45 IOH (at VOH) mA IOL (at VOL) mA Notes 2 2 -- 4 4 -- 6 6 Note2 6 6 Note2 8 8 -- 10 10 -- 12 12 -- Note 1: 2: Software Configurator GUI will display the Commercial/Industrial numeric values. The actual drive capability at temperature is defined by Table 5-21. DDRIO has two 6mA drive strength settings. The setting that corresponds to Output Drive Selection value of 8mA has a shorter propagation delay. DS50003487A-page 28 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-22: LVCMOS 1.8V AC TEST PARAMETERS AND DRIVER IMPEDANCE SPECIFICATIONS LVCMOS 1.8V AC Calibrated Impedance Option Symbols Parameters Min Typ Max Units Rodt_cal Supported output driver calibrated impedance (for DDRIO I/O Bank) -- 75, 60, 50, -- 33, 25, 20 LVCMOS 1.8V AC Test Parameters Specifications Vtrip Measuring/trip point for data path -- 0.9 -- V Rent Cent Cload Resistance for enable path (tZH, tZL, tHZ, tLZ) Capacitive loading for enable path (tZH, tZL, tHZ, tLZ) Capacitive loading for data path (tDP) -- 2k -- 5 -- 5 -- -- pF -- pF 5.6.4.2 AC Switching Characteristics 5.6.4.2.1 AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-23: LVCMOS 1.8V AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.71V LVCMOS 1.8V (for DDRIO I/O Bank with Fixed Codes) ODT (On Die Termination) in None Speed Grade 1 tPY 2.071 tPYS 2.213 None 3.185 3.171 Units ns ns 50 3.394 3.397 ns 75 3.322 3.316 ns LVCMOS 1.8V (for MSIO I/O Bank) 150 None 3.252 2.827 3.239 ns 2.813 ns 50 3.043 3.053 ns 75 2.968 2.963 ns LVCMOS 1.8V (for MSIOD I/O Bank) 150 2.898 2.886 ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 29 5.6.4.2.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-24: LVCMOS 1.8V AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.71V Speed Grade 1 Output Drive Selection Slew Control tDP tZL tZH tHZ tLZ Units LVCMOS 1.8V (for DDRIO I/O Bank with Fixed Codes) 2 mA slow 4.681 4.017 4.69 5.388 4.852 ns medium 4.211 3.599 4.219 5.058 4.488 ns medium_fast 3.978 3.392 3.986 4.874 4.327 ns fast 3.953 3.373 3.961 4.858 4.316 ns 4 mA slow 4.355 3.657 4.346 5.967 5.399 ns medium 3.886 3.246 3.879 5.628 5.01 ns medium_fast 3.656 3.05 3.647 5.461 4.845 ns fast 3.635 3.033 3.626 5.447 4.838 ns 6 mA slow 4.105 3.422 4.092 6.221 5.599 ns medium 3.68 3.05 3.668 5.9 5.257 ns medium_fast 3.477 2.867 3.463 5.739 5.118 ns fast 3.451 2.849 3.437 5.72 5.104 ns 8 mA slow 4.015 3.32 3.998 6.458 5.808 ns medium 3.59 2.947 3.574 6.129 5.449 ns medium_fast 3.383 2.761 3.366 5.963 5.304 ns fast 3.357 2.746 3.34 5.954 5.289 ns 10 mA slow 3.888 3.18 3.864 6.739 6.045 ns medium 3.485 2.822 3.467 6.422 5.7 ns medium_fast 3.281 2.642 3.26 6.277 5.553 ns fast 3.258 2.627 3.238 6.27 5.546 ns 12 mA slow 3.795 3.096 3.773 6.773 6.067 ns medium 3.408 2.764 3.389 6.47 5.743 ns medium_fast 3.215 2.599 3.194 6.346 5.61 ns fast 3.196 2.584 3.175 6.335 5.604 ns 16 mA slow 3.744 3.035 3.719 6.944 6.207 ns medium 3.358 2.712 3.339 6.657 5.868 ns medium_fast 3.175 2.546 3.153 6.547 5.751 ns fast 3.156 2.531 3.133 6.541 5.747 ns LVCMOS 1.8V (for MSIO I/O Bank) 2 mA slow 4 mA slow 6 mA slow 8 mA slow 10 mA slow 12 mA slow 3.957 3.668 3.586 3.616 3.662 3.75 4.784 4.162 3.994 3.782 3.732 3.615 5.023 4.485 4.358 4.162 4.121 4.006 5.643 5.866 ns 6.543 6.382 ns 7.622 6.941 ns 7.988 7.161 ns 8.396 7.423 ns 8.576 7.543 ns LVCMOS 1.8V (for MSIOD I/O Bank) 2 mA slow 3.048 3.692 3.898 5.818 5.609 ns DS50003487A-page 30 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-24: LVCMOS 1.8V AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.71V (CONTINUED) Speed Grade 1 Output Drive Selection Slew Control 4 mA slow tDP tZL tZH 2.5 3.088 3.288 tHZ tLZ Units 6.421 6.121 ns 6 mA slow 2.225 2.747 2.937 7.18 6.753 ns 8 mA slow 2.233 2.72 2.904 7.49 6.992 ns 10 mA slow 2.263 2.577 2.759 7.851 7.253 ns 5.6.5 1.5V LVCMOS LVCMOS 1.5 is a general standard for 1.5V applications and is supported in IGLOO 2 FPGAs and SmartFusion 2 SoC FPGAs in compliance to the JEDEC specification JESD8-11A. 5.6.5.1 Minimum and Maximum AC/DC Input and Output Levels Specification TABLE 5-25: LVCMOS 1.5V MINIMUM AND MAXIMUM DC INPUT AND OUTPUT LEVELS Symbols Parameters Min Typ Max Units LVCMOS 1.5V Recommended DC Operating Conditions VDDI Supply voltage 1.425 1.5 1.575 V LVCMOS 1.5V DC Input Voltage Specification VIH (DC) DC input logic High for (MSIOD and DDRIO I/O banks) 0.65 × VDDI -- 1.575 V VIH (DC) DC input logic High (for MSIO I/O Bank) 0.65 × VDDI -- 2.75 V VIL (DC) IIH (DC)1 IIL (DC)1 DC input logic Low Input current High Input current Low 0.3 -- 0.35 × VDDI V -- ---- -- -- ---- -- LVCMOS 1.5V DC Output Voltage Specification VOH DC output logic High VDDI × 0.75 -- -- V VOL DC output logic Low -- -- VDDI × 0.25 V 1. For more information about input current high (IIH) and input current low (IIL), see Table 5-3. TABLE 5-26: LVCMOS 1.5V MAXIMUM AC SWITCHING SPEEDS Symbols Parameters Conditions Min LVCMOS 1.5V Maximum AC Switching Speed Dmax Maximum data rate AC loading: 17 pF load, -- (for DDRIO I/O Bank) maximum drive/slew Dmax Maximum data rate AC loading: 17 pF load, -- (for MSIO I/O Bank) maximum drive/slew Dmax Maximum data rate AC loading: 17 pF load, -- (for MSIOD I/O Bank) maximum drive/slew Typ Max -- 210 -- 140 -- 190 Units Mbps Mbps Mbps 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 31 TABLE 5-27: LVCMOS 1.5V AC TEST PARAMETERS AND DRIVER IMPEDANCE SPECIFICATIONS Symbols Parameters Min Typ Max LVCMOS 1.5V AC Calibrated Impedance Option Rodt_cal Supported output driver calibrated -- impedance (for DDRIO I/O Bank) 75, 60, 50, -- 40 LVCMOS 1.5V AC Test Parameters Specifications Vtrip Measuring/trip point for data path -- 0.75 -- Rent Cent Cload Resistance for enable path (tZH, tZL, -- tHZ, tLZ) Capacitive loading for enable path -- (tZH, tZL, tHZ, tLZ) Capacitive loading for data path (tDP) -- 2k -- 5 -- 5 -- Units V pF pF TABLE 5-28: LVCMOS 1.5V TRANSMITTER DRIVE STRENGTH SPECIFICATIONS Output Drive Selection VOH (V) VOL (V) DDRIO I/O Bank MSIO I/O Bank MSIOD I/O Bank (with Fixed Code) Min IOH (at VOH) IOL (at VOL) Max mA mA 2 mA 2 mA 2 mA VDDI × 0.75 VDDI × 0.25 2 2 4 mA 4 mA 4 mA VDDI × 0.75 VDDI × 0.25 4 4 6 mA 6 mA 6 mA VDDI × 0.75 VDDI × 0.25 6 6 8 mA N/A 8 mA VDDI × 0.75 VDDI × 0.25 8 8 N/A N/A 10 mA VDDI × 0.75 VDDI × 0.25 10 10 N/A N/A 12 mA VDDI × 0.75 VDDI × 0.25 12 12 5.6.5.2 5.6.5.2.1 AC Switching Characteristics AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-29: LVCMOS 1.5V AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.425V Speed Grade 1 LVCMOS 1.5V (for DDRIO I/O Bank with Fixed Codes) LVCMOS 1.5V (for MSIO I/O Bank) ODT (On Die Termination) in tPY None 2.19 None 50 75 150 3.679 4.151 3.984 3.823 tPYS 2.216 3.652 4.126 3.953 3.791 Units ns ns ns ns ns DS50003487A-page 32 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-29: LVCMOS 1.5V AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.425V None 3.262 3.229 ns 50 3.76 3.739 ns 75 3.555 3.52 ns LVCMOS 1.5V (for MSIOD I/O Bank) 150 3.395 3.359 ns 5.6.5.2.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-30: LVCMOS 1.5V AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ=125°C, VDD = 1.14V, VDDI = 1.425V Output Drive Selection Slew Control Speed Grade 1 tDP tZL tZH tHZ tLZ Units LVCMOS 1.5V (for DDRIO I/O Bank with Fixed Codes) 2 mA slow 5.712 4.796 5.735 5.814 5.138 ns medium 5.094 4.274 5.114 5.484 4.779 ns medium_fast 4.793 4.013 4.81 5.288 4.625 ns fast 4.762 3.98 4.78 5.261 4.615 ns 4 mA slow 4.966 4.133 4.956 6.763 6.05 ns medium 4.412 3.62 4.401 6.433 5.664 ns medium_fast 4.145 3.358 4.131 6.249 5.507 ns fast 4.116 3.338 4.103 6.238 5.498 ns 6 mA slow 4.744 3.869 4.728 7.173 6.383 ns medium 4.212 3.382 4.195 6.837 6.004 ns medium_fast 3.951 3.135 3.93 6.668 5.861 ns fast 3.919 3.11 3.899 6.644 5.845 ns 8 mA slow 4.603 3.691 4.585 7.397 6.553 ns medium 4.081 3.242 4.062 7.064 6.189 ns medium_fast 3.827 3.015 3.804 6.912 6.051 ns fast 3.804 2.994 3.781 6.903 6.051 ns 10 mA slow 4.519 3.612 4.499 7.578 6.676 ns medium 4.026 3.177 4.005 7.264 6.335 ns medium_fast 3.775 2.948 3.75 7.11 6.198 ns fast 3.747 2.929 3.721 7.103 6.19 ns 12 mA slow 4.456 3.562 4.433 7.704 6.795 ns medium 3.965 3.13 3.943 7.388 6.425 ns medium_fast 3.731 2.912 3.704 7.278 6.303 ns fast 3.703 2.893 3.676 7.275 6.294 ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 33 TABLE 5-30: LVCMOS 1.5V AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ=125°C, VDD = 1.14V, VDDI = 1.425V (CONTINUED) Output Drive Selection Slew Control Speed Grade 1 tDP tZL tZH tHZ tLZ Units LVCMOS 1.5V (for MSIO I/O Bank) 2 mA slow 5.118 6.263 6.53 6.524 6.388 ns 4 mA slow 4.657 5.178 5.65 8.57 7.55 ns 6 mA slow 4.693 4.89 5.389 8.928 7.766 ns 8 mA slow 4.876 4.663 5.183 9.59 8.173 ns LVCMOS 1.5V (for MSIOD I/O Bank) 2 mA slow 3.085 3.795 4.086 6.838 6.477 ns 4 mA slow 2.731 3.365 3.631 7.663 7.165 ns 6 mA slow 2.742 3.162 3.417 8.126 7.52 ns 5.6.6 1.2V LVCMOS LVCMOS 1.2 is a general standard for 1.2V applications and is supported in IGLOO 2 FPGAs and SmartFusion 2 SoC FPGAs in compliance to the JEDEC specification JESD8-12A. 5.6.6.1 Minimum and Maximum Input and Output Levels Specification TABLE 5-31: LVCMOS 1.2V MINIMUM AND MAXIMUM DC INPUT AND OUTPUT LEVELS Symbols Parameters Conditions Min Typ Max LVCMOS 1.2V Recommended DC Operating Conditions VDDI Supply voltage 1.140 1.2 1.26 LVCMOS 1.2V DC Input Voltage Specification VIH (DC) DC input logic High (for MSIOD and DDRIO I/O Banks) 0.65 × VDDI -- 1.26 VIH (DC) DC input logic High (for MSIO I/O Bank) 0.65 × VDDI -- 2.75 VIL (DC) IIH (DC)1 IIL (DC)1 DC input logic Low Input current High Input current Low 0.3 -- 0.35 × VDDI -- -- -- -- -- -- LVCMOS 1.2V DC Output Voltage Specification VOH DC output logic High VDDI × 0.75 -- -- VOL DC output logic Low -- -- VDDI × 0.25 Units V V V V -- -- V V 1. For more information about input current high (IIH) and input current low (IIL), see Table 5-3. DS50003487A-page 34 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-32: LVCMOS 1.2V MAXIMUM AC SWITCHING SPEEDS Symbols Parameters Conditions Min LVCMOS 1.2V Maximum AC Switching Speed Dmax Maximum data rate (for DDRIO I/O Bank) AC loading: 17 pF load, -- maximum drive/slew Dmax Maximum data rate (for MSIO I/O Bank) AC loading: 17 pF load, -- maximum drive/slew Dmax Maximum data rate (for MSIOD I/O Bank) AC loading: 17 pF load, -- maximum drive/slew Typ Max -- 180 -- 100 -- 140 Units Mbps Mbps Mbps TABLE 5-33: LVCMOS 1.2V AC CALIBRATED IMPEDANCE AND TEST PARAMETERS SPECIFICATIONS Symbols Parameters Conditions Min Typ Max LVCMOS 1.2V AC Calibrated Impedance Option Rodt_cal Supported output driver calibrated impedance -- 75, 60, -- (for DDRIO I/O Bank) 50, 40 LVCMOS 1.2V AC Test Parameters Specifications Vtrip Measuring/trip point for data path -- 0.6 -- Rent Resistance for enable path (tZH, tZL, tHZ, tLZ) -- Cent Capacitive loading for enable path (tZH, tZL, tHZ, tLZ) -- Cload Capacitive loading for data path (tDP) -- 2k -- 5 -- 5 -- Units V pF pF TABLE 5-34: LVCMOS 1.2 V TRANSMITTER DRIVE STRENGTH SPECIFICATIONS Output Drive Selection VOH (V) VOL (V) DDRIO I/O Bank IOH (at VOH) IOL (at VOL) MSIO I/O Bank MSIOD I/O Bank (with Fixed Code) Min Max mA mA 2 mA 2 mA 2 mA VDDI × 0.75 VDDI × 0.25 2 2 4 mA 4 mA 4 mA VDDI × 0.75 VDDI × 0.25 4 4 N/A N/A 6 mA VDDI × 0.75 VDDI × 0.25 6 6 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 35 5.6.6.2 5.6.6.2.1 AC Switching Characteristics AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-35: LVCMOS 1.2V AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ=125°C, VDD = 1.14V, VDDI = 1.14V LVCMOS 1.2V (for DDRIO I/O Bank with Fixed Codes) ODT (On Die Termination) in None Speed Grade 1 tPY 2.539 tPYS 2.556 Units ns None 4.888 4.845 ns 50 6.683 6.605 ns 75 5.923 5.847 ns LVCMOS 1.2V (for MSIO I/O Bank) 150 5.29 5.235 ns None 4.281 4.235 ns 50 6.806 6.721 ns 75 5.643 5.564 ns LVCMOS 1.2V (for MSIOD I/O Bank) 150 4.813 4.753 ns 5.6.6.2.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-36: LVCMOS 1.2V AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ=125°C, VDD = 1.14V, VDDI = 1.14V Output Drive Selection Slew Control Speed Grade 1 tDP tZL tZH tHZ tLZ Units LVCMOS 1.2V (for DDRIO I/O Bank with Fixed Code) 2 mA slow 6.938 5.599 6.948 7.568 6.612 ns medium 6.11 4.814 6.114 7.201 6.234 ns medium_fast 5.675 4.409 5.676 6.971 6.048 ns fast 5.633 4.379 5.634 6.958 6.037 ns 4 mA slow 6.328 4.892 6.316 8.339 7.306 ns medium 5.538 4.192 5.521 7.961 6.923 ns medium_fast 5.119 3.832 5.097 7.76 6.741 ns fast 5.072 3.085 5.051 7.752 6.725 ns 6 mA slow 6.092 4.681 6.075 8.685 7.589 ns medium 5.342 4.016 5.32 8.33 7.19 ns medium_fast 4.949 3.66 4.922 8.139 7.022 ns fast 4.903 3.622 4.876 8.107 7.006 ns LVCMOS 1.2V (for MSIO I/O Bank) 2 mA slow 7.051 7.856 8.541 10.387 8.768 ns DS50003487A-page 36 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-36: Output Drive Selection 4 mA LVCMOS 1.2V AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ=125°C, VDD = 1.14V, VDDI = 1.14V (CONTINUED) Speed Grade 1 Slew Control slow tDP 7.385 tZL 7.027 tZH 7.815 tHZ 11.547 tLZ 9.444 Units ns LVCMOS 1.2V (for MSIOD I/O Bank) 2 mA slow 4.048 5.123 5.552 8.401 7.824 ns 4 mA slow 3.941 4.406 4.814 9.422 8.656 ns 5.6.7 3.3V PCI/PCIX Peripheral Component Interface (PCI) for 3.3V standards specify support for 33 MHz and 66 MHz PCI bus applications. 5.6.7.1 Minimum and Maximum Input and Output Levels Specification TABLE 5-37: PCI/PCI-X DC VOLTAGE SPECIFICATION (APPLICABLE TO MSIO BANK ONLY) Symbols Parameters Conditions Min Typ Max Units PCI/PCIX Recommended DC Operating Conditions VDDI Supply voltage 3.15 3.3 3.45 V PCI/PCIX DC Input Voltage Specification VI IIH(DC)1 IIL(DC)1 DC input voltage Input current High Input current Low 0 -- -- -- -- -- 3.45 V PCI/PCIX DC Output Voltage Specification VOH DC output logic High Per PCI Specification V VOL DC output logic Low Per PCI Specification V 1. For more information about input current high (IIH) and input current low (IIL), see Table 5-3. 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 37 TABLE 5-38: PCI/PCI-X AC SPECIFICATIONS (APPLICABLE TO MSIO BANK ONLY) Symbols Parameters Conditions Min Typ Max PCI/PCI-X AC Specifications Dmax Maximum data rate (MSIO I/O AC Loading: per JEDEC -- -- 560 Bank) specifications PCI/PCI-X AC Test Parameters Specifications Vtrip Measuring/trip point for data path (falling edge) -- 0.615 × VDDI -- Vtrip Measuring/trip point for data path (rising edge) -- 0.285 × VDDI -- Rtt_test Resistance for data test path -- 25 -- Rent Resistance for enable path (tZH, tZL, tHZ, tLZ) -- 2k -- Cent Capacitive loading for enable path (tZH, tZL, tHZ, tLZ) -- 5 -- Cload Capacitive loading for data path (tDP) -- 10 -- Units Mbps V V pF pF 5.6.7.2 5.6.7.2.1 AC Switching Characteristics AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-39: PCI/PCIX AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 3.15V PCI/PCIX (for MSIO I/O Bank) ODT (On Die Termination) in None Speed Grade 1 tPY 2.379 tPYS 2.387 Units ns 5.6.7.2.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-40: PCI/PCIX AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI= 3.15V Speed Grade 1 PCI/PCIX (for MSIO I/O Bank) tDP 2.394 tZL 2.274 tZH 2.316 tHZ 6.876 tLZ 6.242 Units ns 5.7 Memory Interface and Voltage Referenced I/O Standards 5.7.1 HIGH-SPEED TRANSCEIVER LOGIC (HSTL) The High-Speed Transceiver Logic (HSTL) standard is a general purpose high-speed bus standard sponsored by IBM (EIA/JESD8-6). IGLOO 2 FPGA and SmartFusion 2 SoC FPGA devices support two classes of the 1.5V HSTL. These differential versions of the standard require a differential amplifier input buffer and a push-pull output buffer. DS50003487A-page 38 2023 Microchip Technology Inc. and its subsidiaries 5.7.1.1 Minimum and Maximum Input and Output Levels Specification TABLE 5-41: HSTL DC VOLTAGE SPECIFICATION (APPLICABLE TO DDRIO I/O BANK ONLY) Symbols Parameters Conditions Min Typ Max Units HSTL Recommended DC Operating Conditions VDDI Supply voltage 1.425 1.5 1.575 V VTT Termination voltage 0.698 0.750 0.803 V VREF Input reference voltage 0.698 0.750 0.803 V HSTL DC Input Voltage Specification VIH (DC) DC input logic High VREF + 0.1 -- 1.575 V VIL (DC) IIH (DC)1 IIL (DC)1 DC input logic Low Input current High Input current Low 0.3 -- VREF 0.1 V -- ---- -- -- ---- -- HSTL DC Output Voltage Specification HSTL Class I VOH DC output logic High VDDI 0.4 -- -- V VOL DC output logic Low -- -- 0.4 V IOH at VOH Output minimum source DC current 7.0 ---- mA IOL at VOL Output minimum sink current 7.0 ---- mA HSTL Class II VOH DC output logic High VDDI 0.4 -- -- V VOL DC output logic Low -- -- 0.4 V IOH at VOH Output minimum source DC current 15.0 ---- mA IOL at VOL Output minimum sink current 15.0 ---- mA HSTL DC Differential Voltage Specifications VID (DC) DC input differential voltage 0.2 ---- V 1. For more information about input current high (IIH) and input current low (IIL), see Table 5-3. 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 39 TABLE 5-42: HSTL AC SPECIFICATIONS (APPLICABLE TO DDRIO BANK ONLY) Symbols Parameters Conditions Min Typ Max HSTL AC Differential Voltage Specifications VDIFF AC input differential voltage 0.4 -- -- Vx AC differential cross point voltage 0.68 -- 0.9 HSTL Maximum AC Switching Speed Dmax Maximum data rate AC loading: per JEDEC -- specifications -- 360 HSTL Impedance Specification Rref Supported output driver calibrated Reference resistance = 191 -- impedance (for DDRIO I/O Bank) 25.5, -- 47.8 RTT Effective impedance value (ODT for Reference resistance = 191 -- DDRIO I/O Bank only) 47.8 -- HSTL AC Test Parameters Specification Vtrip Measuring/trip point for data path -- 0.75 -- Rent Resistance for enable path (tZH, tZL, tHZ, tLZ) -- Cent Capacitive loading for enable path (tZH, tZL, tHZ, tLZ) -- Rtt_test Reference resistance for data test path for HSTL15 Class I (tDP) -- Rtt_test Reference resistance for data test path for HSTL15 Class II (tDP) -- Cload Capacitive loading for data path (tDP) -- 2k -- 5 -- 50 -- 25 -- 5 -- Units V V Mbps V pF pF 5.7.1.2 5.7.1.2.1 AC Switching Characteristics AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-43: HSTL15 AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.425V ODT (On Die Termination) in tPY Speed Grade 1 Units HSTL (for DDRIO I/O Bank with Fixed Code) Pseudo-Differential None 1.673 ns True-Differential None 1.693 ns DS50003487A-page 40 2023 Microchip Technology Inc. and its subsidiaries 5.7.1.2.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-44: HSTL 15 AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.425V Speed Grade 1 tDP tZL tZH tHZ tLZ Units HSTL Class I (for DDRIO I/O Bank) Single Ended 2.922 2.91 2.904 3.225 3.218 ns Differential 2.907 2.757 2.755 2.662 2.66 ns HSTL Class II (for DDRIO I/O Bank) Single Ended 2.817 2.735 2.735 2.644 2.644 ns Differential 2.827 2.81 2.803 3.205 3.197 ns 5.7.2 STUB-SERIES TERMINATED LOGIC Stub-Series Terminated Logic (SSTL) for 2.5V (SSTL2), 1.8V (SSTL18), and 1.5V (SSTL15) is supported in IGLOO 2 and SmartFusion 2 SoC FPGAs. SSTL2 is defined by JEDEC standard JESD8-9B and SSTL18 is defined by JEDEC standard JESD8-15. IGLOO 2 SSTL I/O configurations are designed to meet double data rate standards DDR/2/3 for general purpose memory buses. Double data rate standards are designed to meet their JEDEC specifications as defined by JEDEC standard JESD79F for DDR, JEDEC standard JESD79-2F for DDR, JEDEC standard JESD79-3D for DDR3, and JEDEC standard JESD209A for LPDDR. 5.7.3 STUB-SERIES TERMINATED LOGIC 2.5V (SSTL2) SSTL2 Class I and Class II are supported in IGLOO 2 and SmartFusion 2 SoC FPGAs and also comply with reduced and full drive of double data rate (DDR) standards. IGLOO 2 and SmartFusion 2 SoC FPGA I/Os supports both standards for single-ended signaling and differential signaling for SSTL2. This standard requires a differential amplifier input buffer and a push-pull output buffer. 5.7.3.1 Minimum and Maximum DC Input and Output Levels Specification TABLE 5-45: DDR1/SSTL2 MINIMUM AND MAXIMUM DC INPUT AND OUTPUT LEVELS Symbols Parameters Min Typ Max Recommended DC Operating Conditions VDDI Supply voltage 2.375 2.5 2.625 VTT Termination voltage 1.164 1.250 1.339 VREF Input reference voltage 1.164 1.250 1.339 SSTL2 DC Input Voltage Specification VIH (DC) DC input logic High VREF + 0.15 -- 2.625 VIL (DC) DC input logic Low 0.3 IIH (DC)1 Input current High -- IIL (DC)1 Input current Low -- -- VREF 0.15 -- -- -- -- SSTL2 DC Output Voltage Specification SSTL2 Class I (DDR Reduced Drive) VOH DC output logic High VTT + 0.608 -- -- VOL DC output logic Low -- -- VTT 0.608 Units V V V V V -- -- V V 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 41 TABLE 5-45: DDR1/SSTL2 MINIMUM AND MAXIMUM DC INPUT AND OUTPUT LEVELS Symbols Parameters Min Typ Max IOH at VOH Output minimum source DC 8.1 current -- -- IOL at VOL Output minimum sink current 8.1 -- -- SSTL2 Class II (DDR Full Drive) Applicable to MSIO and DDRIO I/O Banks Only VOH DC output logic High VTT + 0.81 -- -- VOL DC output logic Low -- -- VTT 0.81 IOH at VOH Output minimum source DC 16.2 current -- -- IOL at VOL Output minimum sink current 16.2 -- -- SSTL2 DC Differential Voltage Specification VID (DC) DC input differential voltage 0.3 -- -- 1. For more information about input current high (IIH) and input current low (IIL), see Table 5-3. Units mA mA V V mA mA V TABLE 5-46: DDR1/SSTL2 AC SPECIFICATIONS Symbols Parameters Conditions Min Typ Max Units SSTL2 Maximum AC Switching Speeds Dmax Maximum data rate (for AC loading: per JEDEC -- DDRIO I/O Bank) specifications -- 360 Mbps Dmax Maximum data rate (for AC loading: 17pF load -- MSIO I/O Bank) -- 450 Mbps Dmax Maximum data rate (for AC loading: 17pF load -- MSIOD I/O Bank) -- 480 Mbps SSTL2 AC Differential Voltage Specifications VDIFF AC Input Differential -- Voltage 0.7 -- -- V Vx AC Differential Cross -- Point Voltage 0.5 × VDDI - 0.2 -- 0.5 × VDDI + 0.2 V SSTL2 Impedance Specifications Supported output driver Reference resistor -- 20, 42 -- calibrated impedance (for = 150 DDRIO I/O Bank) SSTL2 AC Test Parameters Specifications Vtrip Measuring/trip point for data path -- 1.25 -- V Rent Resistance for enable path (tZH, tZL, tHZ, tLZ) -- 2k -- Cent Capacitive loading for enable path (tZH, tZL, tHZ, tLZ) -- 5 -- pF Rtt_test Reference resistance for data test path for SSTL2 -- 50 -- Class I (tDP) Rtt_test Reference resistance for data test path for SSTL2 -- 25 -- Class II (tDP) Cload Capacitive loading for data path (tDP) -- 5 -- pF 5.7.3.2 AC Switching Characteristics DS50003487A-page 42 2023 Microchip Technology Inc. and its subsidiaries 5.7.3.2.1 AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-47: DDR1/SSTL2 AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 2.375V Speed Grade 1 SSTL2 (DDRIO I/O Bank) ODT (On Die Termination) in tPY Units Pseudo-Differential None 1.613 ns True-Differential None 1.647 ns SSTL2 (MSIO I/O Bank) Pseudo-Differential None 3.083 ns True-Differential None 3.028 ns SSTL2 (MSIOD I/O Bank) Pseudo-Differential None 2.721 ns True-Differential None 2.71 ns TABLE 5-48: DDR1/SSTL2 AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI= 2.375V Speed Grade 1 SSTL2 Class I tDP tZL tZH tHZ tLZ Units DDRIO I/O Bank Single Ended 2.457 2.145 2.137 2.302 2.293 ns Differential 2.454 2.38 2.375 2.589 2.584 ns MSIO I/O Bank Single Ended 2.283 2.255 2.243 2.286 2.273 ns Differential 2.434 2.702 2.691 2.39 2.381 ns MSIOD I/O Bank Single Ended 1.646 1.59 1.589 1.82 1.818 ns Differential 1.774 1.93 1.926 2.012 2.007 ns SSTL2 Class II DDRIO I/O Bank Single Ended 2.317 2.06 2.053 2.229 2.221 ns Differential 2.32 2.213 2.21 2.57 2.565 ns MSIO I/O Bank Single Ended 2.563 2.208 2.19 2.205 2.187 ns Differential 2.703 2.566 2.555 2.363 2.353 ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 43 5.7.4 STUB-SERIES TERMINATED LOGIC 1.8V (SSTL18) SSTL18 Class I and Class II are supported in IGLOO 2 and SmartFusion 2 SoC FPGAs, and also comply with the reduced and full drive double date rate (DDR2) standard. IGLOO 2 and SmartFusion 2 SoC FPGA I/Os support both standards for single-ended signaling and differential signaling for SSTL18. This standard requires a differential amplifier input buffer and a push-pull output buffer. 5.7.4.1 Minimum and Maximum Input and Output Levels Specification TABLE 5-49: DDR2/SSTL18 AC/DC MINIMUM AND MAXIMUM INPUT AND OUTPUT LEVELS SPECIFICATION Symbols Parameters Min Typ Max Units Recommended DC Operating Conditions VDDI Supply voltage 1.71 1.8 1.89 V VTT Termination voltage 0.838 0.900 0.964 V VREF Input reference voltage 0.838 0.900 0.964 V SSTL18 DC Input Voltage Specification VIH (DC) DC input logic High VREF + 0.125 -- 1.89 V VIL (DC) IIH (DC)1 IIL (DC)1 DC input logic Low Input current High Input current Low 0.3 -- VREF 0.125 V -- -- -- -- -- -- -- -- SSTL18 DC Output Voltage Specification SSTL18 Class I (DDR2 Reduced Drive) VOH DC output logic High VTT + 0.603 -- -- V VOL DC output logic Low -- -- VTT 0.603 V IOH at VOH Output minimum source DC current 6.0 -- -- mA (DDRIO I/O Bank only) IOL at VOL Output minimum sink current 6.0 -- -- mA (DDRIO I/O Bank only) SSTL18 Class II (DDR2 Full Drive)2 VOH DC output logic High VTT + 0.603 -- -- V VOL DC output logic Low -- -- VTT 0.603 V IOH at VOH Output minimum source DC current 12.0 -- -- mA (DDRIO I/O Bank only) IOL at VOL Output minimum sink current 12.0 -- -- mA (DDRIO I/O Bank only) SSTL18 DC Differential Voltage Specification VID (DC) DC input differential voltage 0.3 -- -- V Note 1: For more information about input current high (IIH) and input current low (IIL), see Table 5-3. 2: To meet JEDEC Electrical Compliance, use DDR2 Full Drive Transmitter. DS50003487A-page 44 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-50: DDR2/SSTL18 AC SPECIFICATIONS (APPLICABLE TO DDRIO BANK ONLY) Symbols Parameters Conditions Min Typ Max Units SSTL18 AC Differential Voltage Specification VDIFF (AC) AC input differential voltage 0.5 -- -- V Vx (AC) AC differential cross point voltage 0.5 × VDDI 0.175 -- 0.5 × VDDI + 0.175 V SSTL18 Maximum AC Switching Speed Dmax Maximum data rate (for AC loading: per -- DDRIO I/O Bank) JEDEC specification -- 600 Mbps SSTL18 Impedance Specifications Rref Supported output driver Reference resistor -- 20, 42 -- calibrated impedance = 150 (for DDRIO I/O Bank) RTT Effective impedance Reference resistor -- value (ODT) = 150 50, 75, -- 150 SSTL18 AC Test Parameters Specifications Vtrip Measuring/trip point for data path -- 0.9 -- V Rent Cent Rtt_test Rtt_test Cload Resistance for enable path (tZH, tZL, tHZ, tLZ) -- Capacitive loading for enable path (tZH, tZL, -- tHZ, tLZ) Reference resistance for data test path for -- SSTL18 Class I (tDP) Reference resistance for data test path for -- SSTL18 Class II (tDP) Capacitive loading for data path (tDP) -- 2k -- 5 -- pF 50 -- 25 -- 5 -- pF 5.7.4.2 5.7.4.2.1 AC Switching Characteristics AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-51: DDR2/SSTL18 AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.71V Speed Grade 1 On-Die Termination (ODT) in tPY SSTL18 (for DDRIO I/O Bank with Fixed Codes) Units Pseudo differential None 1.633 ns True differential None 1.65 ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 45 5.7.4.2.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-52: DDR2/SSTL18 AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.71V Speed Grade 1 tDP tZL tZH tHZ tLZ Units SSTL18 Class I (for DDRIO I/O Bank) Single Ended 2.67 3.078 3.072 2.489 2.484 ns Differential 2.645 2.431 2.434 2.396 2.398 ns SSTL18 Class II (for DDRIO I/O Bank Single Ended 2.564 2.973 2.965 2.45 2.444 ns Differential 2.532 2.401 2.398 2.368 2.365 ns 5.7.5 STUB-SERIES TERMINATED LOGIC 1.5V (SSTL15) SSTL15 Class I and Class II are supported in IGLOO 2 FPGAs and SmartFusion 2 SoC FPGAs, and also comply with the reduced and full drive double data rate (DDR3) standard. IGLOO 2 FPGA and SmartFusion 2 SoC FPGA I/Os supports both standards for single-ended signaling and differential signaling for SSTL18. This standard requires a differential amplifier input buffer and a push-pull output buffer. 5.7.5.1 Minimum and Maximum AC/DC Input and Output Levels Specification TABLE 5-53: DDR3/SSTL15 DC VOLTAGE SPECIFICATION (FOR DDRIO I/O BANK ONLY) Symbols Parameters Conditions Min Typ Max Units Recommended DC Operating Conditions VDDI Supply voltage 1.425 1.5 1.575 V VTT Termination voltage 0.698 0.750 0.803 V VREF Input reference voltage 0.698 0.750 0.803 V SSTL15 DC Input Voltage Specification VIH(DC) DC input logic High VREF + 0.1 -- 1.575 V VIL(DC) IIH (DC)1 IIL (DC)1 DC input logic Low Input current High Input current Low 0.3 -- VREF 0.1 V -- -- -- -- -- -- -- -- SSTL15 DC Output Voltage Specification DDR3/SSTL15 Class I (DDR3 Reduced Drive) VOH DC output logic High 0.8 x VDDI -- V VOL DC output logic Low -- -- 0.2 x VDDI V IOH at VOH Output minimum source DC current 6.5 -- -- mA IOL at VOL Output minimum sink current SSTL15 Class II (DDR3 Full Drive)2 6.5 -- -- mA VOH DC output logic High 0.8 × VDDI -- -- V VOL DC output logic Low -- -- 0.2 x VDDI V DS50003487A-page 46 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-53: DDR3/SSTL15 DC VOLTAGE SPECIFICATION (FOR DDRIO I/O BANK ONLY) Symbols Parameters Conditions Min Typ Max Units IOH at VOH Output minimum source DC current 7.6 -- -- mA IOL at VOL Output minimum sink current 7.6 -- -- mA SSTL15 Differential Voltage Specification VID DC input differential voltage 0.2 -- -- V Note 1: For more information about input current high (IIH) and input current low (IIL), see Table 5-3. 2: To meet JEDEC Electrical Compliance, use DDR3 Full Drive Transmitter. TABLE 5-54: DDR3/SSTL15 AC SPECIFICATIONS Symbols Parameters Conditions Min SSTL15 AC Differential Voltage Specification VDIFF AC input differential voltage 0.3 Vx AC differential cross point voltage 0.5 × VDDI 0.150 SSTL15 Maximum AC Switching Speed (for DDRIO I/O Banks Only) Dmax Maximum data rate AC loading: per -- JEDEC specifications SSTL15 AC Calibrated Impedance Option Rref Supported output driver Reference resistor -- calibrated impedance = 240 RTT Effective impedance value Reference resistor -- (ODT) = 240 SSTL15 AC Test Parameters Specifications Vtrip Measuring/trip point for data path -- Rent Cent Rtt_test Rtt_test Cload Resistance for enable path (tZH, tZL, tHZ, tLZ) -- Capacitive loading for enable path (tZH, tZL, tHZ, tLZ) -- Reference resistance for data test path for SSTL15 -- Class I (tDP) Reference resistance for data test path for SSTL15 -- Class II (tDP) Capacitive loading for data path (tDP) -- Typ Max Units -- -- V -- 0.5 × VDDI + V 0.150 -- 600 Mbps 34, 40 -- 20, 30, 40, -- 60, 120 0.75 -- V 2k -- 5 -- pF 50 -- 25 -- 5 -- pF 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 47 5.7.5.2 5.7.5.2.1 AC Switching Characteristics AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-55: DDR3/STTL15 AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.425V Speed Grade 1 ODT (On Die Termination) in tPY DDR3/SSTL15 (for DDRIO I/O Bank) Calibration Mode Only Units Pseudo-Differential None 1.672 ns True-Differential None 1.694 ns 5.7.5.2.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-56: DDR3/SSTL15 AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.425V Speed Grade 1 tDP tZL tZH tHZ tLZ Units DDR3 Reduced Drive/SSTL15 Class I (for DDRIO I/O Bank) Single Ended 2.832 2.766 2.767 2.658 2.659 ns Differential 2.848 3.401 3.393 3.173 3.166 ns DDR3 Full Drive/SSTL15 Class II (for DDRIO I/O Bank) Single Ended 2.832 2.76 2.759 2.655 2.655 ns Differential 2.845 3.397 3.387 3.179 3.171 ns 5.7.6 LOW POWER DOUBLE DATA RATE (LPDDR) LPDDR reduced and full drive low power double data rate standards are supported in IGLOO 2 FPGA and SmartFusion 2 SoC FPGA I/Os. This standard requires a differential amplifier input buffer and a push-pull output buffer. This I/O standard is supported in DDRIO I/O Bank only. 5.7.6.1 Minimum and Maximum AC/DC Input and Output Levels Specification TABLE 5-57: LPDDR AC/DC SPECIFICATIONS (FOR DDRIO I/O BANK ONLY) Symbols Parameters Min Typ Max Recommended DC Operating Conditions VDDI Supply voltage 1.71 1.8 1.89 VTT Termination voltage 0.838 0.900 0.964 VREF Input reference voltage 0.838 0.900 0.964 LPDDR DC Input Voltage Specification VIH (DC) DC input logic High 0.7 × VDDI -- 1.89 VIL (DC) DC input logic Low 0.3 -- 0.3 × VDDI IIH (DC) Input current High -- -- 10 IIL (DC) Input current Low -- -- 10 Units V V V V V µA µA Notes -- -- -- -- -- -- -- DS50003487A-page 48 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-57: LPDDR AC/DC SPECIFICATIONS (FOR DDRIO I/O BANK ONLY) Symbols Parameters Min Typ Max LPDDR DC Output Voltage Specification LPDDR Reduced Drive VOH DC output logic High 0.9 × VDDI -- -- VOL DC output logic Low -- -- 0.1 × VDDI IOH at VOH Output minimum source DC 0.1 current -- -- IOL at VOL Output minimum sink 0.1 current -- -- LPDDR Full Drive VOH DC output logic High 0.9 × VDDI -- -- VOL DC output logic Low -- -- 0.1 × VDDI IOH at VOH Output minimum source DC 0.1 current -- -- IOL at VOL Output minimum sink 0.1 current -- -- LPDDR DC Differential Voltage Specification VID (DC) DC input differential voltage 0.4 × VDDI -- -- Note: To meet JEDEC Electrical Compliance, use LPDDR Full Drive Transmitter. Units V V mA mA V V mA mA V Notes -- -- -- -- 1 -- -- -- -- -- TABLE 5-58: LPDDR MAXIMUM AC SWITCHING SPEEDS (FOR DDRIO I/O BANK ONLY) Symbols Parameters Conditions Min Typ Max Units Dmax Maximum data rate AC loading: per JEDEC specifications -- -- 360 Mbps TABLE 5-59: LPDDR AC SPECIFICATIONS (FOR DDRIO I/O BANK ONLY) Symbols Parameters Conditions Min Typ Max Units LPDDR AC Differential Voltage Specification VDIFF (AC) AC Input differential voltage -- 0.6 × VDDI -- -- V Vx (AC) AC Differential Cross Point Voltage -- 0.4 × VDDI -- 0.6 × VDDI V LPDDR Impedance Specifications Rref Supported Output Driver Calibrated Reference Resistor -- Impedance = 150 20,42 -- RTT Effective impedance Value - ODT Reference Resistor -- = 150 50, 75, -- 150 LPDDR AC Test Parameters Specifications Vtrip Measuring/Trip Point for Data Path -- -- 0.9 -- V Rent Resistance for Enable Path (tZH, tZL, -- tHZ, tLZ) -- 2k -- 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 49 TABLE 5-59: LPDDR AC SPECIFICATIONS (FOR DDRIO I/O BANK ONLY) Cent Rtt_test Cload Capacitive Loading for Enable Path -- (tZH, tZL, tHZ, tLZ) Reference resistance for Data Test -- Path for LPDDR (tDP) Capacitive Loading for Data Path -- (tDP) -- 5 -- pF -- 50 -- -- 5 -- pF 5.7.6.2 AC Switching Characteristics TABLE 5-60: LPDDR AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ=125°C, VDD=1.14V, VDDI= 1.71V Speed Grade 1 ODT (On Die Termination) in tPY LPDDR (for DDRIO I/O Bank with Fixed Codes) Units Pseudo-Differential None 1.633 ns True-Differential None 1.65 ns 5.7.6.2.1 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-61: LPDDR AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.71V Speed Grade 1 tDP tZL tZH tHZ tLZ Units LPDDR Reduced Drive (for DDRIO I/O Bank) Single Ended 2.645 2.431 2.434 2.396 2.398 ns Differential 2.652 3.044 3.038 2.46 2.455 ns LPDDR Full Drive (for DDRIO I/O Bank) Single Ended 2.532 2.401 2.398 2.368 2.365 ns Differential 2.546 2.509 2.503 2.852 2.845 ns DS50003487A-page 50 2023 Microchip Technology Inc. and its subsidiaries 5.7.6.3 Minimum and Maximum AC/DC Input and Output Levels Specification using LPDDR-LVCMOS 1.8V Mode TABLE 5-62: LPDDR-LVCMOS 1.8V MODE, MINIMUM AND MAXIMUM DC INPUT AND OUTPUT LEVELS (APPLICABLE TO DDRIO I/O BANK ONLY) Symbols Parameters Conditions Min Typ Max Units LPDDR-LVCMOS 1.8V Recommended DC Operating Conditions VDDI Supply Voltage -- 1.710 1.8 1.89 V LPDDR-LVCMOS 1.8V Mode DC Input Voltage Specification VIH(DC) DC input Logic HIGH for (MSIOD -- and DDRIO I/O Banks) 0.65 x VDDI -- 1.89 V VIH(DC) DC input Logic HIGH (for MSIO -- I/O Bank) 0.65 x VDDI -- 3.45 V VIL(DC) DC input Logic LOW -- IIH(DC)1 Input current HIGH -- IIL(DC)1 Input current LOW -- -0.3 -- 0.35 x VDDI V -- -- -- -- -- -- -- -- LPDDR-LVCMOS 1.8 V Mode DC Output Voltage Specification VOH DC output Logic HIGH -- VDDI - 0.45 -- -- V VOL DC output Logic LOW -- -- -- 0.45 V 1. For more information about input current high (IIH) and input current low (IIL), see Table 5-3. TABLE 5-63: LPDDR-LVCMOS 1.8V MAXIMUM AC SWITCHING SPEEDS (APPLICABLE TO DDRIO I/O BANK ONLY) Symbols Parameters Conditions Min Typ Max Units Dmax Maximum Data Rate (for DDRIO I/O Bank) AC Loading: 17 pF Load, 8 -- mA Drive and Above/All Slew -- 360 Mbps 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 51 TABLE 5-64: LPDDR-LVCMOS 1.8V AC TEST PARAMETERS AND DRIVER IMPEDANCE SPECIFICATIONS (APPLICABLE TO DDRIO I/O BANK ONLY) Symbols Parameters Conditions Min Typ Max LPDDR - LVCMOS 1.8V Calibrated Impedance Option Rodt_cal Supported Output Driver -- Calibrated Impedance (for DDRIO I/O Bank) -- 75, 60, 50, -- 33, 25, 20 LPDDR- LVCMOS 1.8V AC Test Parameters Specifications Vtrip Measuring/Trip Point for Data Path -- -- 0.9 -- Rent Cent Cload Resistance for Enable Path (tZH, -- tZL, tHZ, tLZ) Capacitive Loading for Enable -- Path (tZH, tZL, tHZ, tLZ) Capacitive Loading for Data Path -- (tDP) -- 2k -- -- 5 -- -- 5 -- Units V pF pF TABLE 5-65: LPDDR-LVCMOS 1.8V MODE TRANSMITTER DRIVE STRENGTH SPECIFICATION (APPLICABLE TO DDRIO I/O BANK ONLY) Output Drive Selection VOH (V) Min VOL (V) Max IOH (at VOH) IOL (at VOL) mA mA Notes 2 mA VDDI 0.45 0.45 2 2 -- 4 mA VDDI 0.45 0.45 4 4 -- 6 mA VDDI 0.45 0.45 6 6 -- 8 mA VDDI 0.45 0.45 8 8 -- 10 mA VDDI 0.45 0.45 10 10 -- 12 mA VDDI 0.45 0.45 12 12 -- 16 mA VDDI 0.45 0.45 16 16 1 Note 1: 16 mA Drive Strengths, All Slews, meet LPDDR JEDEC electrical compliance. DS50003487A-page 52 2023 Microchip Technology Inc. and its subsidiaries 5.7.6.4 AC Switching Characteristics TABLE 5-66: LPPDR - LVCMOS 1.8 V AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.71V LPDDR-LVCMOS 1.8 mode (for DDRIO I/O Bank with Fixed Codes) ODT (On Die Termination) in None Speed Grade 1 tPY 2.071 tPYS 2.213 Units ns 5.7.6.4.1 AC Switching Characteristics for Transmitter (Output and Tristate Buffers TABLE 5-67: Output Drive Selection 2 mA 4 mA 6 mA 8 mA 10 mA 12 mA LPDDR - LVCMOS 1.8 V AC SWITCHING CHARACTERISTICS FOR TRANSMITTER DDRIO I/O BANK (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.71V Speed Grade 1 Slew Control slow tDP tZL 4.681 4.017 tZH 4.69 tHZ 5.388 tLZ 4.852 Units ns medium 4.211 3.599 4.219 5.058 4.488 ns medium_fast 3.978 3.392 3.986 4.874 4.327 ns fast 3.953 3.373 3.961 4.858 4.316 ns slow 4.355 3.657 4.346 5.967 5.399 ns medium 3.886 3.246 3.879 5.628 5.01 ns medium_fast 3.656 3.05 3.647 5.461 4.845 ns fast 3.635 3.033 3.626 5.447 4.838 ns slow 4.105 3.422 4.092 6.221 5.599 ns medium 3.68 3.05 3.668 5.9 5.257 ns medium_fast 3.477 2.867 3.463 5.739 5.118 ns fast 3.451 2.849 3.437 5.72 5.104 ns slow 4.015 3.32 3.998 6.458 5.808 ns medium 3.59 2.947 3.574 6.129 5.449 ns medium_fast 3.383 2.761 3.366 5.963 5.304 ns fast 3.357 2.746 3.34 5.954 5.289 ns slow 3.888 3.18 3.864 6.739 6.045 ns medium 3.485 2.822 3.467 6.422 5.7 ns medium_fast 3.281 2.642 3.26 6.277 5.553 ns fast 3.258 2.627 3.238 6.27 5.546 ns slow 3.795 3.096 3.773 6.773 6.067 ns medium 3.408 2.764 3.389 6.47 5.743 ns medium_fast 3.215 2.599 3.194 6.346 5.61 ns fast 3.196 2.584 3.175 6.335 5.604 ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 53 TABLE 5-67: 16 mA LPDDR - LVCMOS 1.8 V AC SWITCHING CHARACTERISTICS FOR TRANSMITTER DDRIO I/O BANK (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 1.71V slow 3.744 3.035 3.719 6.944 6.207 ns medium 3.358 2.712 3.339 6.657 5.868 ns medium_fast 3.175 2.546 3.153 6.547 5.751 ns fast 3.156 2.531 3.133 6.541 5.747 ns 5.8 Differential I/O Standards Configuration of the I/O modules as a differential pair is handled by Microchip's Libero® System-on-Chip (SoC) software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input register (InReg), Output register (OutReg), Enable register (EnReg), and Double Data Rate registers (DDR). 5.8.1 LVDS Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. 5.8.1.1 Minimum and Maximum Input and Output Levels TABLE 5-68: LVDS DC VOLTAGE SPECIFICATION Symbols Parameters Conditions Min Typ Max Units LVDS Recommended DC Operating Conditions VDDI Supply voltage 2.5 V range 2.375 2.5 2.625 V VDDI Supply voltage 3.3 V range 3.15 3.3 3.45 V LVDS DC Input Voltage Specification VI DC Input voltage 2.5 V range 0 -- 2.925 V VI IIH (DC)1 IIL (DC)1 DC input voltage Input current High Input current Low 3.3 V range 0 -- 3.45 V -- -- -- -- LVDS DC Output Voltage Specification VOH DC output logic High 1.25 1.425 1.6 V VOL DC output logic Low 0.9 1.075 1.25 V LVDS Differential Voltage Specification VOD Differential output voltage swing 250 350 450 mV VOCM Output common mode voltage 1.125 1.25 1.375 V VICM VID2 Input common mode voltage Input differential voltage 0.05 1.25 2.35 V 100 350 600 mV 1. For more information about input current high (IIH) and input current low (IIL), see Table 5-3. 2. When VID is < 300 mV, the input signal is delayed by up to an additional 450 ps for LVDS25 and 280 ps for LVDS33. This delay is not accounted in the timing model. Clock insertion delays, propagation delays, and I/O to FF delays are marginally affected. Adding a parallel termination resistor of 200 ±5% across the receiver pins can mitigate this additional delay when VID is < 300 mV. DS50003487A-page 54 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-69: LVDS AC SPECIFICATIONS Symbols Parameters Conditions LVDS Maximum AC Switching Speed Dmax Maximum data rate (for MSIO I/O Bank) AC loading: 12 pF/100 differential load Dmax Maximum data rate (for MSIOD I/O Bank) AC loading: 10 pF/100 differential load LVDS Impedance Specification Rt Termination resistance -- LVDS AC Test Parameters Specifications Vtrip Measuring/trip point for data path Rent Cent Resistance for enable path (tZH, tZL, tHZ, tLZ) Capacitive loading for enable path (tZH, tZL, tHZ, tLZ) Min Typ ---- ---- Max Units 480 Mbps 480 Mbps -- 100 -- -- Cross point -- V -- 2k -- --5 -- pF 5.8.1.2 5.8.1.2.1 LVDS25 AC Switching Characteristics AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-70: LVDS25 RECEIVER CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 2.375V Speed Grade 1 On-Die Termination (ODT) in None tPY 3.061 Units ns LVDS (for MSIO I/O Bank) 100 3.057 ns None 2.792 ns LVDS (for MSIOD I/O Bank) 100 2.787 ns 5.8.1.2.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-71: LVDS25 TRANSMITTER CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 2.375V Speed Grade 1 LVDS (for MSIO I/O Bank) tDP 2.299 tZL 2.602 tZH 2.589 tHZ 2.305 tLZ 2.32 Units ns LVDS (for MSIOD I/O Bank) No pre-emphasis 1.656 1.845 1.838 1.992 1.969 ns Min pre-emphasis 1.583 1.868 1.866 2.018 1.998 ns Med pre-emphasis 1.559 1.893 1.886 2.045 2.021 ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 55 5.8.1.3 5.8.1.3.1 LVDS33 AC Switching Characteristics AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-72: LVDS33 RECEIVER CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 3.15V Speed Grade 1 On Die Termination (ODT) in None tPY 2.763 Units ns LVDS33 (for MSIO I/O Bank) 100 2.76 ns 5.8.1.3.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-73: LVDS33 TRANSMITTER CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 3.15V Speed Grade 1 LVDS33 (for MSIO I/O Bank) tDP 2.069 tZL 2.112 tZH 2.106 tHZ 2.078 tLZ 2.09 Units ns 5.8.2 B-LVDS Bus LVDS (B-LVDS) specifications extend the existing LVDS standard to high-performance multi-point bus applications. Multi-drop and multi-point bus configurations may contain any combination of drivers, receivers, and transceivers. 5.8.2.1 Minimum and Maximum AC/DC Input and Output Levels Specification TABLE 5-74: B-LVDS DC VOLTAGE SPECIFICATION Symbols Parameters Conditions Min Typ Max Bus-LVDS Recommended DC Operating Conditions VDDI Supply voltage 2.375 2.5 2.625 Bus-LVDS DC Input Voltage Specification VI IIH (DC)1 IIL (DC)1 DC input voltage Input current High Input current Low 0 -- 2.925 -- -- -- -- -- -- Bus-LVDS DC Output Voltage Specification (for MSIO I/O Bank only) VOH DC output logic High 1.25 1.425 1.6 VOL DC output logic Low 0.9 1.075 1.25 Bus-LVDS Differential Voltage Specification VOD Differential output voltage swing (for MSIO I/O Bank only) 65 -- 460 VOCM Output common mode voltage (for MSIO I/O Bank only) 1.1 -- 1.5 VICM Input common mode voltage 0.05 -- 2.4 VID Input differential voltage 0.1 -- VDDI 1. For more information about input current high (IIH) and input current low (IIL), see Table 5-3. Units V V -- -- V V mV V V V DS50003487A-page 56 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-75: B-LVDS AC SPECIFICATIONS Symbols Parameters Conditions Bus-LVDS Maximum AC Switching Speed Dmax Maximum data rate (for MSIO I/O Bank) AC loading: 2 pF / 100 differential load Bus-LVDS Impedance Specifications Rt Termination resistance Bus-LVDS AC Test Parameters Specifications Vtrip Measuring/trip point for data path Rent Cent Resistance for enable path (tZH, tZL, tHZ, tLZ) Capacitive loading for enable path (tZH, tZL, tHZ, tLZ) Min Typ Max -- -- 450 -- 27 -- -- Cross point -- -- 2k -- -- 5 -- 5.8.2.2 5.8.2.2.1 AC Switching Characteristics AC Switching Characteristics for Receiver (Input Buffers) Units Mbps V pF TABLE 5-76: B-LVDS AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 2.375V Speed Grade 1 On-Die Termination (ODT) in None tPY 3.011 Units ns Bus-LVDS (for MSIO I/O Bank) 100 3.006 ns None 2.722 ns Bus-LVDS (for MSIOD I/O Bank) 100 2.725 ns 5.8.2.2.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-77: B-LVDS AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 2.375V Speed Grade 1 Bus-LVDS (for MSIO I/O Bank) tDP 2.78 tZL 2.632 tZH 2.617 tHZ 2.448 tLZ 2.436 Units ns 5.8.3 M-LVDS M-LVDS specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. 5.8.3.1 Minimum and Maximum Input and Output Levels TABLE 5-78: M-LVDS DC VOLTAGE SPECIFICATION Symbols Parameters Conditions M-LVDS Recommended DC Operating Conditions VDDI1 Supply voltage Min Typ Max Units 2.375 2.5 2.625 V 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 57 TABLE 5-78: M-LVDS DC VOLTAGE SPECIFICATION (CONTINUED) M-LVDS DC Input Voltage Specification VI IIH (DC)2 IIL (DC)2 DC input voltage Input current High Input current Low 0 -- 2.925 V -- -- -- -- -- -- -- -- M-LVDS DC Output Voltage Specification (for MSIO I/O Bank Only) VOH DC output logic High 1.25 1.425 1.6 V VOL DC output logic Low 0.9 1.075 1.25 V M-LVDS Differential Voltage Specification VOD Differential output voltage Swing (for MSIO I/O Bank only) 300 -- 650 mV VOCM Output common mode voltage (for MSIO I/O Bank only) 0.3 -- 2.1 V VICM Input common mode voltage 0.3 -- 1.2 V VID Input differential voltage 50 -- 2400 mV 1. Only M-LVDS TYPE I is supported. 2. For more information about input current high (IIH) and input current low (IIL), see Table 5-3. TABLE 5-79: M-LVDS AC SPECIFICATIONS Symbols Parameters Conditions M-LVDS Maximum AC Switching Speeds Dmax Maximum data rate (for MSIO I/O Bank) AC loading: 2 pF/100 differential load M-LVDS Impedance Specification Rt Termination resistance M-LVDS AC Test Parameters Specifications VTrip Measuring/trip point for data path Rent Cent Resistance for enable path (tZH, tZL, tHZ, tLZ) Capacitive loading for enable path (tZH, tZL, tHZ, tLZ) Min Typ Max Units -- -- 450 Mbps -- 50 -- -- Cross -- V point -- 2k -- -- 5 -- pF 5.8.3.2 5.8.3.2.1 AC Switching Characteristics AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-80: M-LVDS AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI= 2.375V Speed Grade 1 On-Die Termination (ODT) in None tPY 3.011 Units ns M-LVDS (for MSIO I/O Bank) 100 3.006 ns None 2.722 ns M-LVDS (for MSIOD I/O Bank) 100 2.725 ns DS50003487A-page 58 2023 Microchip Technology Inc. and its subsidiaries 5.8.3.2.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-81: M-LVDS AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI= 2.375V Speed Grade 1 M-LVDS (for MSIO I/O Bank) tDP 2.78 tZL 2.632 tZH 2.616 tHZ 2.447 tLZ 2.436 Units ns 5.8.4 MINI-LVDS Mini-LVDS is an unidirectional interface from the timing controller to the column drivers and is designed to the Texas Instruments Standard SLDA007A. 5.8.4.1 Mini-LVDS Minimum and Maximum Input and Output Levels TABLE 5-82: MINI-LVDS DC VOLTAGE SPECIFICATION Symbols Parameters Conditions Recommended DC Operating Conditions VDDI Supply voltage Mini-LVDS DC Input Voltage Specification VI DC Input voltage Mini-LVDS DC Output Voltage Specification VOH DC output logic High VOL DC output logic Low Mini-LVDS Differential Voltage Specification VOD Differential output voltage swing VOCM Output common mode voltage VICM Input common mode voltage VID Input differential voltage Min Typ Max Units 2.375 2.5 2.625 V 0 -- 2.925 V 1.25 1.425 1.6 V 0.9 1.075 1.25 V 300 -- 1 -- 0.3 -- 100 -- 600 mV 1.4 V 1.2 V 600 mV TABLE 5-83: MINI-LVDS AC SPECIFICATIONS Symbols Parameters Conditions Mini-LVDS Maximum AC Switching Speed Dmax Maximum data rate (MSIO I/O Bank) AC loading: 2 pF/100 differential load Dmax Maximum data rate (MSIOD I/O Bank) AC loading: 10 pF/100 differential load Mini-LVDS Impedance Specification Rt Termination resistance Min Typ Max Units -- -- 460 Mbps -- -- 480 Mbps -- 100 -- 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 59 TABLE 5-83: MINI-LVDS AC SPECIFICATIONS Mini-LVDS AC Test Parameters Specifications VTrip Measuring/trip point for data path Rent Cent 5.8.4.2 5.8.4.2.1 Resistance for enable path (tZH, tZL, tHZ, tLZ) Capacitive loading for enable path (tZH, tZL, tHZ, tLZ) AC Switching Characteristics AC Switching Characteristics for Receiver (Input Buffers) -- Cross -- V point -- 2k -- -- 5 -- pF TABLE 5-84: MINI-LVDS AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI= 2.375V Speed Grade 1 On-Die Termination (ODT) in None tPY 3.112 Units ns Mini-LVDS (for MSIO I/O Bank) 100 2.995 ns None 2.612 ns Mini-LVDS (for MSIOD I/O Bank) 100 2.612 ns 5.8.4.2.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-85: MINI-LVDS AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 2.375V Speed Grade 1 Mini-LVDS (for MSIO I/O Bank) tDP tZL tZH tHZ tLZ Units 2.3 2.602 2.59 2.306 2.32 ns Mini-LVDS (for MSIOD I/O Bank) No pre-emphasis 1.652 1.84 1.833 1.988 1.965 ns Min pre-emphasis 1.652 1.84 1.833 1.988 1.965 ns Med pre-emphasis 1.577 1.868 1.86 2.02 1.994 ns Max pre-emphasis 1.555 1.894 1.883 2.048 2.019 ns DS50003487A-page 60 2023 Microchip Technology Inc. and its subsidiaries 5.8.5 RSDS Reduced Swing Differential Signaling (RSDS) is similar to an LVDS high-speed interface using differential signaling. RSDS has a similar implementation to LVDS devices and is only intended for point-to-point applications. 5.8.5.1 Minimum and Maximum Input and Output Levels TABLE 5-86: RSDS DC VOLTAGE SPECIFICATION Symbols Parameters Conditions Recommended DC Operating Conditions VDDI Supply voltage RSDS DC Input Voltage Specification VI DC input voltage RSDS DC Output Voltage Specification VOH DC output logic High VOL DC output logic Low RSDS Differential Voltage Specification VOD Differential output voltage swing VOCM Output common mode voltage VICM Input common mode voltage VID Input differential voltage Min Typ Max 2.375 2.5 2.625 0 -- 2.925 1.25 1.425 1.6 0.9 1.075 1.25 100 -- 600 0.5 -- 1.5 0.3 -- 1.5 100 -- 600 Units V V V V mV V V mV TABLE 5-87: RSDS AC SPECIFICATIONS Symbols Parameters Conditions RSDS Maximum AC Switching Speed Dmax Maximum data rate (for MSIO I/O Bank) AC loading: 2 pF/100 differential load Dmax Maximum data rate (for MSIOD I/O Bank) AC loading: 10 pF/100 differential load RSDS Impedance Specification Rt Termination resistance RSDS AC Test Parameters Specifications VTrip Measuring/trip point for data path Rent Cent Resistance for enable path (tZH, tZL, tHZ, tLZ) Capacitive loading for enable path (tZH, tZL, tHZ, tLZ) Min Typ Max -- -- 460 -- -- 480 -- 100 -- -- Cross -- point -- 2k -- -- 5 -- Units Mbps Mbps V pF 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 61 5.8.5.2 5.8.5.2.1 AC Switching Characteristics AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-88: RSDS AC SWITCHING CHARACTERISTICS FOR RECEIVER (INPUT BUFFERS)-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 2.375V Speed Grade 1 On-Die Termination (ODT) in None tPY 3.112 Units ns RSDS (for MSIO I/O Bank) 100 3.108 ns None 2.832 ns RSDS (for MSIOD I/O Bank) 100 2.821 ns 5.8.5.2.2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) TABLE 5-89: RSDS AC SWITCHING CHARACTERISTICS FOR TRANSMITTER (OUTPUT AND TRISTATE BUFFERS)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 2.375V Speed Grade 1 Units RSDS (for MSIO I/O Bank) tDP tZL tZH tHZ tLZ 2.256 2.484 2.472 2.111 2.096 ns RSDS (for MSIOD I/O Bank) No pre-emphasis 1.661 1.648 1.645 1.675 1.665 ns Min pre-emphasis 1.651 1.84 1.833 1.988 1.964 ns Med pre-emphasis 1.577 1.868 1.859 2.019 1.993 ns Max pre-emphasis 1.555 1.894 1.883 2.047 2.018 ns 5.8.6 LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Similar to LVDS, two pins are needed. It also requires external resistor termination. IGLOO 2 and SmartFusion 2 SoC FPGAs support only LVPECL receivers and do not support LVPECL transmitters. DS50003487A-page 62 2023 Microchip Technology Inc. and its subsidiaries 5.8.6.1 Minimum and Maximum Input and Output Levels TABLE 5-90: LVPECL DC VOLTAGE SPECIFICATION (APPLICABLE TO MSIO I/O BANKS ONLY) Symbols Parameters Conditions Min Typ Max Units Recommended DC Operating Conditions VDDI Supply voltage 3.15 3.3 3.45 V LVPECL DC Input Voltage Specification VI DC input voltage 0 -- 3.45 V LVPECL Differential Voltage Specification VICM Input common mode voltage 0.3 2.8 V VIDIFF Input differential voltage 100 300 1,000 mV TABLE 5-91: LVPECL MAXIMUM AC SWITCHING SPEEDS (APPLICABLE TO MSIO I/O BANKS ONLY) Symbols Parameters Conditions Min Typ Max Units LVPECL AC Specifications Fmax Maximum data rate (for MSIO I/O Bank) -- -- 810 Mbps 5.8.6.2 5.8.6.2.1 AC Switching Characteristics AC Switching Characteristics for Receiver (Input Buffers) TABLE 5-92: LVPECL RECEIVER CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V, VDDI = 3.15V tPY On-Die Termination (ODT) in Speed Grade 1 Units None 2.71 ns LVPECL (for MSIO I/O Bank) 100 2.71 ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 63 5.9 I/O Register Specifications 5.9.1 INPUT REGISTER FIGURE 5-4: TIMING MODEL FOR INPUT REGISTER F DA D EN B EN Q Input I/O Buffer ALn C ALn ADn SLn D ADn SLn SLE SD SD LAT E CLK LAT CLK G Q FIGURE 5-5: I/O REGISTER INPUT TIMING DIAGRAM CLK tICKMPWL tICKMPWH tISUD tIHD D 1 2 3 4 5 6 7 8 9 10 11 ADn SD SLn ALn tISUE tIHE tIRECALn EN tIALn2Q tICLKQ Q 1 3 tIWALn tISUSLn tIREMALn tIHSLn 5 7 DS50003487A-page 64 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-93: INPUT DATA REGISTER PROPAGATION DELAYS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125C, VDD = 1.14 V Parameter tIBYP tICLKQ tISUD tIHD tISUE tIHE tISUSL tIHSL tIALn2Q Description Bypass Delay of the Input Register Clock-to-Q of the Input Register Data Setup Time for the Input Register Data Hold Time for the Input Register Enable Setup Time for the Input Register Enable Hold Time for the Input Register Synchronous Load Setup Time for the Input Register Synchronous Load Hold Time for the Input Register Asynchronous Clear-to-Q of the Input Register (ADn=1) Asynchronous Preset-to-Q of the Input Register (ADn=0) Measuring Speed Nodes Grade (from, to)1 1 F,G Note 1 E,G 0.13 A,E Note 1 A,E Note 1 B,E 0.821 B,E 0.016 D,E 1.726 D,E 0.062 C,G 0.502 C,G 0.459 Units ns ns ns ns ns ns ns ns ns ns tIREMALn Asynchronous Load Removal Time for the Input Register C,E 0.127 ns tIRECALn Asynchronous Load Recovery Time for the Input Register C,E 0.213 ns tIWALn Asynchronous Load Minimum Pulse Width for the Input Register C,C 0.444 ns tICKMPWH Clock Minimum Pulse Width High for the Input Register E,E 0.101 ns tICKMPWL Clock Minimum Pulse Width Low for the Input Register E,E 0.223 ns 1. These timing parameters are dependent on die and I/O location. Use SmartTime tool in Libero for accurate timing data. 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 65 5.9.2 OUTPUT/ENABLE REGISTER FIGURE 5-6: TIMING MODEL FOR OUTPUT/ENABLE REGISTER A D B EN C ALn ADn D SLn SD LAT CLK E D2 J F D EN Q ALn ADn SLn SLE SD LAT CLK H D EN Q ALn ADn SLE SLn SD LAT CLK Output/Enable Registers G I Output I/O Buffer with Enable Control DS50003487A-page 66 2023 Microchip Technology Inc. and its subsidiaries FIGURE 5-7: I/O REGISTER OUTPUT TIMING DIAGRAM Clk tOSUE D tOHDE tOSUD tOHD 1 tOCKMPWL tOCKMPWH 2 3 ADn SD SLn EN ALn Out tORECALn tOALn2Q tOCLKQ 1 tOSUSLn ` 2 4 tOHDSLn 5 tOREMALn 4 TABLE 5-94: OUTPUT/ENABLE DATA REGISTER PROPAGATION DELAYS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Parameter tOBYP tOCLKQ tOSUD tOHD tOSUE tOHE tOSUSL tOHSL tOALn2Q tOREMALn tORECALn Description Measuring Nodes (from, to)* Bypass Delay of the Output/Enable Register F,G or H,I Clock-to-Q of the Output/Enable Register E,G or E,I Data Setup Time for the Output/Enable Register A,E or J,E Data Hold Time for the Output/Enable Register A,E or J,E Enable Setup Time for the Output/Enable Register B,E Enable Hold Time for the Output/Enable Register B,E Synchronous Load Setup Time for the Output/Enable Register D,E Synchronous Load Hold Time for the Output/Enable Register D,E Asynchronous Clear-to-Q of the Output/Enable Register (ADn=1) C,G or C,I Asynchronous Preset-to-Q of the Output/Enable Register (ADn=0) C,G or C,I Asynchronous Load Removal Time for the Output/Enable C,E Register Asynchronous Load Recovery Time for the Output/Enable C,E Register Speed Grade 1 0.342 0.254 0.268 0.037 0.821 0.029 1.824 0.062 0.558 0.526 0.134 0.236 Units ns ns ns ns ns ns ns ns ns ns ns ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 67 TABLE 5-94: OUTPUT/ENABLE DATA REGISTER PROPAGATION DELAYS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V (CONTINUED) Parameter tOWALn tOCKMPWH tOCKMPWL Description Asynchronous Load Minimum Pulse Width for the Output/Enable Register Clock Minimum Pulse Width High for the Output/Enable Register Clock Minimum Pulse Width Low for the Output/Enable Register Measuring Nodes (from, to)* C,C Speed Grade 1 0.444 E,E 0.101 E,E 0.223 Units ns ns ns 5.10 DDR Module Specification 5.10.1 INPUT DDR MODULE FIGURE 5-8: INPUT DDR MODULE A D E EN ALn F ADn G SLn SD LAT CLK B D EN ALn ADn SLn SLE SD LAT CLK C Q QR D Q ALn ADn Latch CLK D EN ALn ADn SLE SLn SD LAT CLK D Q QF DDR_IN DS50003487A-page 68 2023 Microchip Technology Inc. and its subsidiaries 5.10.1.1 Input DDR Timing Diagram FIGURE 5-9: INPUT DDR TIMING DIAGRAM CLK tDDRICKMPWL tDDRICKMPWH tDDRISUD tDDRIHD D 1 2 3 4 5 6 7 8 9 10 11 ADn SD SLn tDDRIWAL ALn tDDRIHE tDDRISUE EN tDDRIAL2Q1 QR 1 tDDRIAL2Q2 QF tDDRIRECAL tDDRICLKQ1 3 tDDRICLKQ2 2 tDDRISUSLn tDDRIREMAL tDDRIHSLn 5 7 4 6 5.10.2 TIMING CHARACTERISTICS TABLE 5-95: Parameter tDDRICLKQ1 tDDRICLKQ2 tDDRISUD tDDRIHD tDDRISUE tDDRIHE tDDRISUSLn tDDRIHSLn tDDRIAL2Q1 tDDRIAL2Q2 INPUT DDR PROPAGATION DELAYS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Description Measuring Nodes (from, to) Speed Grade 1 Units Clock-to-Out Out_QR for Input DDR B,C 0.13 ns Clock-to-Out Out_QF for Input DDR B,D Data Setup for Input DDR A,B 0.131 ns Note 1 ns Data Hold for Input DDR A,B Note 1 ns Enable Setup for Input DDR E,B 0.821 ns Enable Hold for Input DDR E,B 0.016 ns Synchronous Load Setup for Input DDR G,B 1.726 ns Synchronous Load Hold for Input DDR G,B 0.062 ns Asynchronous Load-to-Out QR for Input DDR F,C 0.459 ns Asynchronous Load-to-Out QF for Input DDR F,D 0.416 ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 69 TABLE 5-95: tDDRIREMAL INPUT DDR PROPAGATION DELAYS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Asynchronous Load Removal time for Input F,B DDR 0.127 ns tDDRIRECAL Asynchronous Load Recovery time for Input F,B DDR 0.213 ns tDDRIWAL Asynchronous Load Minimum Pulse Width for F,F Input DDR 0.444 ns tDDRICKMPWH Clock Minimum Pulse Width High for Input B,B DDR 0.101 ns tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR B,B 0.223 ns 1. These timing parameters are dependent on die and I/O location. Use SmartTime tool in Libero for accurate timing data. DS50003487A-page 70 2023 Microchip Technology Inc. and its subsidiaries 5.10.3 OUTPUT DDR MODULE FIGURE 5-10: OUTPUT DDR MODULE A DR B EN ALn C ADn SLn D SD LAT CLK E DF F D EN ALn ADn SLn SLE SD LAT CLK Q QR 1 G Q D QF EN Q ALn ADn SLE SLn SD 0 LAT CLK DDR_ OUT 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 71 FIGURE 5-11: OUTPUT DDR TIMING DIAGRAM tDDROSUE tDDROCKMPWL tDDROCKMPWH Clk tDDROHDE tDDROSUDR tDDROHDR DR 1 2 3 tDDROSUDF tDDROHDF DF 6 7 8 4 9 ADn SD SLn EN tDDROWAL ALn tDDRORECAL tDDROAL2Q tDDROCLKQ Out 1 6 tDDROSUSLn tDDROHDSLn ` 2 7 5 10 11 tDDROREMAL 4 9 5.10.4 TIMING CHARACTERISTICS TABLE 5-96: Parameter tDDROCLKQ tDDROSUDF tDDROSUDR tDDROHDF tDDROHDR tDDROSUE tDDROHE tDDROSUSLn tDDROHSLn tDDROAL2Q OUTPUT DDR PROPAGATION DELAYS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Description Measuring Nodes (from, to) Speed Grade 1 Units Clock-to-Out of DDR for Output DDR E,G 0.258 ns DF Data Setup for Output DDR F,E 0.278 ns DR Data Setup for Output DDR A,E 0.288 ns DF Data Hold for Output DDR F,E 0.088 ns DR Data Hold for Output DDR A,E 0.077 ns Enable Setup for Output DDR B,E 0.829 ns Enable Hold for Output DDR B,E 0.031 ns Synchronous Load Setup for Output DDR D,E 1.831 ns Synchronous Load Hold for Output DDR D,E 0.042 ns Asynchronous Load-to-Out for Output DDR C,G 0.549 ns DS50003487A-page 72 2023 Microchip Technology Inc. and its subsidiaries TABLE 5-96: tDDROREMAL tDDRORECAL tDDROWAL tDDROCKMPWH tDDROCKMPWL OUTPUT DDR PROPAGATION DELAYS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Asynchronous Load Removal time for Output C,E DDR 0.134 ns Asynchronous Load Recovery time for Output C,E DDR 0.238 ns Asynchronous Load Minimum Pulse Width for C,C Output DDR 0.377 ns Clock Minimum Pulse Width High for the E,E Output DDR 0.101 ns Clock Minimum Pulse Width Low for the Output E,E DDR 0.223 ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 73 6.0 LOGIC ELEMENT SPECIFICATIONS 6.1 4-input LUT (LUT-4) The IGLOO 2 and SmartFusion 2 SoC FPGAs offer a fully permutable 4-input LUT. In this section, timing characteristics are presented for a sample of the library. For more details, see the SmartFusion 2 and IGLOO 2 Macro Library Guide. FIGURE 6-1: LUT-4 PAD PAD PAD PAD A B C D/S (where applicable) tPD AND4 OR Any Y Combinational Logic PAD A, B, C, D, S VDD 50% 50% tPD = Max(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for the particular combinatorial cell GND VDD OUT GND VDD OUT 50% tPD (RR) tPD (RF) 50% tPD (FF) 50% tPD (FR) GND 50% DS50003487A-page 74 2023 Microchip Technology Inc. and its subsidiaries 6.1.1 TIMING CHARACTERISTICS TABLE 6-1: COMBINATORIAL CELL PROPAGATION DELAYS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Combinatorial Cell Equation Parameter Speed Grade 1 Units INV AND2 NAND2 OR2 NOR2 XOR2 XOR3 AND3 AND4 Y = !A Y = A · B Y = !(A · B) Y = A + B Y = !(A + B) Y = A B Y = A B C Y = A · B · C Y=A· B · C · D tPD 0.104 ns tPD 0.17 ns tPD 0.152 ns tPD 0.17 ns tPD 0.152 ns tPD 0.17 ns tPD 0.233 ns tPD 0.217 ns tPD 0.298 ns 6.2 Sequential Module IGLOO 2 and SmartFusion 2 SoC FPGAs offer a separate flip-flop which can be used independently from the LUT. The flip-flop can be configured as a register or a latch and has a data input and optional enable, synchronous load (clear or preset), and asynchronous load (clear or preset). FIGURE 6-2: SEQUENTIAL MODULE D EN Q ALn ADn SLE SLn SD LAT CLK The following figure shows a configuration with SD = 0 (synchronous clear) and ADn = 1 (asynchronous clear) for a flipflop (LAT = 0). 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 75 FIGURE 6-3: CLK D SD ADn SEQUENTIAL MODULE TIMING DIAGRAM 50% 1 50% tSUD tHD 50% 0 50% 50% 1 50% 1 tCKMPWH tCKMPWL 50% 50% 50% 0 E SL ALn Q 50% tSUE tHE 50% tCLKQ tSUSL 50% tHSL 50% 50% 50% tALn2Q 50% tRECALn tWALn 50% tREMALn 50% 6.2.1 TIMING CHARACTERISTICS TABLE 6-2: Parameter tCLKQ tSUD tHD tSUE tHE tSUSL tHSL tALn2Q tREMALn tRECALn tWALn tCKMPWH tCKMPWL REGISTER DELAYS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Description Speed Grade 1 Units Clock-to-Q of the Core Register 0.114 ns Data Setup Time for the Core Register 0.262 ns Data Hold Time for the Core Register 0 ns Enable Setup Time for the Core Register 0.318 ns Enable Hold Time for the Core Register 0 ns Synchronous Load Setup Time for the Core Register 0.565 ns Synchronous Load Hold Time for the Core Register 0 ns Asynchronous Clear-to-Q of the Core Register (ADn=1) 0.495 ns Asynchronous Preset-to-Q of the Core Register (ADn=0) 0.47 ns Asynchronous Load Removal Time for the Core Register 0 ns Asynchronous Load Recovery Time for the Core Register 0.366 ns Asynchronous Load Minimum Pulse Width for the Core Register 0.266 ns Clock Minimum Pulse Width High for the Core Register 0.065 ns Clock Minimum Pulse Width Low for the Core Register 0.139 ns DS50003487A-page 76 2023 Microchip Technology Inc. and its subsidiaries 7.0 SWITCHING CHARACTERISTICS 7.1 Global Resource Characteristics The IGLOO 2 and SmartFusion 2 SoC FPGA devices offer a powerful, low skew global routing network which provides an effective clock distribution throughout the FPGA fabric. See the IGLOO 2 FPGA and SmartFusion 2 SoC FPGA Fabric User Guide for the positions of various global routing resources. TABLE 7-1: Parameter tRCKL tRCKH tRCKSW M2S090T DEVICE GLOBAL RESOURCE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Input Low Delay for Global Clock 0.793 0.847 ns Input High Delay for Global Clock 1.412 1.498 ns Maximum Skew for Global Clock -- 0.086 ns TABLE 7-2: Parameter tRCKL tRCKH tRCKSW M2S025T DEVICE GLOBAL RESOURCE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Input Low Delay for Global Clock 0.713 0.762 ns Input High Delay for Global Clock 1.306 1.391 ns Maximum Skew for Global Clock -- 0.085 ns TABLE 7-3: Parameter tRCKL tRCKH tRCKSW M2S010T DEVICE GLOBAL RESOURCE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Input Low Delay for Global Clock 0.598 0.639 ns Input High Delay for Global Clock 1.116 1.192 ns Maximum Skew for Global Clock -- 0.076 ns TABLE 7-4: Parameter tRCKL tRCKH tRCKSW M2S005T DEVICE GLOBAL RESOURCE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Input Low Delay for Global Clock 0.736 0.789 ns Input High Delay for Global Clock 0.927 0.995 ns Maximum Skew for Global Clock -- 0.068 ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 77 7.2 FPGA Fabric SRAM See the IGLOO 2 FPGA and SmartFusion 2 SoC FPGA Fabric User Guide for more information. 7.2.1 FPGA FABRIC LARGE SRAM (LSRAM) TABLE 7-5: Parameter tCY tCLKMPWH tCLKMPWL tPLCY tPLCLKMPWH tPLCLKMPWL tCLK2Q RAM1K18 DUAL-PORT MODE FOR DEPTH × WIDTH CONFIGURATION 1KX18-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Clock Period 3.333 -- ns Clock Minimum Pulse Width High 1.5 -- ns Clock Minimum pulse Width Low 1.5 -- ns Pipelined Clock Period 3.333 -- ns Pipelined Clock Minimum Pulse Width High 1.5 -- ns Pipelined Clock Minimum pulse Width Low 1.5 -- ns Read Access Time with Pipeline Register -- 0.346 ns Read Access Time without Pipeline Register -- 2.346 ns Access Time with Feed-Through Write Timing -- 2.346 ns tADDRSU tADDRHD tDSU tDHD tBLKSU tBLKHD tBLK2Q tBLKMPW tRDESU tRDEHD tRDPLESU tRDPLEHD tR2Q tRSTREM tRSTREC tRSTMPW tPLRSTREM tPLRSTREC tPLRSTMPW tSRSTSU Address Setup Time Address Hold Time Data Setup Time Data Hold Time Block Select Setup Time Block Select Hold Time Block Select to Out Disable Time (when Pipe-Lined Registered is Disabled) Block Select Minimum Pulse Width Read Enable Setup Time Read Enable Hold Time Pipelined Read Enable Setup Time (A_DOUT_EN, B_DOUT_EN) Pipelined Read Enable Hold Time (A_DOUT_EN, B_DOUT_EN) Asynchronous Reset to Output Propagation Delay Asynchronous Reset Removal Time Asynchronous Reset Recovery Time Asynchronous Reset Minimum Pulse Width Pipelined Register Asynchronous Reset Removal Time Pipelined Register Asynchronous Reset Recovery Time Pipelined Register Asynchronous Reset Minimum Pulse Width Synchronous Reset Setup Time 0.455 -- ns 0.282 -- ns 0.352 -- ns 0.11 -- ns 0.214 -- ns 0.223 -- ns -- 1.578 ns 0.218 -- ns 0.463 -- ns 0.173 -- ns 0.256 -- ns 0.106 -- ns -- 1.561 ns 0.522 -- ns 0.005 -- ns 0.352 -- ns -0.288 -- ns 0.338 -- ns 0.33 -- ns 0.233 -- ns DS50003487A-page 78 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-5: Parameter tSRSTHD tWESU tWEHD Fmax TABLE 7-6: Parameter tCY tCLKMPWH tCLKMPWL tPLCY tPLCLKMPWH tPLCLKMPWL tCLK2Q RAM1K18 DUAL-PORT MODE FOR DEPTH × WIDTH CONFIGURATION 1KX18-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Synchronous Reset Hold Time 0.037 -- ns Write Enable Setup Time 0.402 -- ns Write Enable Hold Time 0.25 -- ns Maximum Frequency -- 300 MHz RAM1K18 DUAL-PORT MODE FOR DEPTH × WIDTH CONFIGURATION 2KX9-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Clock Period 3.333 -- ns Clock Minimum Pulse Width High 1.5 -- ns Clock Minimum pulse Width Low 1.5 -- ns Pipelined Clock Period 3.333 -- ns Pipelined Clock Minimum Pulse Width High 1.5 -- ns Pipelined Clock Minimum pulse Width Low 1.5 -- ns Read Access Time with Pipeline Register -- 0.346 ns Read Access Time without Pipeline Register -- 2.346 ns Access Time with Feed-Through Write Timing -- 2.346 ns tADDRSU tADDRHD tDSU tDHD tBLKSU tBLKHD tBLK2Q tBLKMPW tRDESU tRDEHD tRDPLESU tRDPLEHD tR2Q tRSTREM Address Setup Time 0.49 -- ns Address Hold Time 0.282 -- ns Data Setup Time 0.346 -- ns Data Hold Time 0.084 -- ns Block Select Setup Time 0.214 -- ns Block Select Hold Time 0.223 -- ns Block Select to Out Disable Time (when Pipe-Lined Registered -- is Disabled) 1.578 ns Block Select Minimum Pulse Width 0.218 -- ns Read Enable Setup Time 0.5 -- ns Read Enable Hold Time 0.073 -- ns Pipelined Read Enable Setup Time (A_DOUT_EN, B_DOUT_EN) 0.256 -- ns Pipelined Read Enable Hold Time (A_DOUT_EN, B_DOUT_EN) 0.106 -- ns Asynchronous Reset to Output Propagation Delay -- 1.569 ns Asynchronous Reset Removal Time 0.522 -- ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 79 TABLE 7-6: Parameter tRSTREC tRSTMPW tPLRSTREM tPLRSTREC tPLRSTMPW tSRSTSU tSRSTHD tWESU tWEHD Fmax TABLE 7-7: Parameter tCY tCLKMPWH tCLKMPWL tPLCY tPLCLKMPWH tPLCLKMPWL tCLK2Q RAM1K18 DUAL-PORT MODE FOR DEPTH × WIDTH CONFIGURATION 2KX9-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Asynchronous Reset Recovery Time 0.005 -- ns Asynchronous Reset Minimum Pulse Width 0.352 -- ns Pipelined Register Asynchronous Reset Removal Time -0.288 -- ns Pipelined Register Asynchronous Reset Recovery Time 0.338 -- ns Pipelined Register Asynchronous Reset Minimum Pulse Width 0.33 -- ns Synchronous Reset Setup Time 0.233 -- ns Synchronous Reset Hold Time 0.037 -- ns Write Enable Setup Time 0.428 -- ns Write Enable Hold Time 0.05 -- ns Maximum Frequency -- 300 MHz RAM1K18 DUAL-PORT MODE FOR DEPTH × WIDTH CONFIGURATION 4KX4-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Clock Period 3.333 -- ns Clock Minimum Pulse Width High 1.5 -- ns Clock Minimum pulse Width Low 1.5 -- ns Pipelined Clock Period 3.333 -- ns Pipelined Clock Minimum Pulse Width High 1.5 -- ns Pipelined Clock Minimum pulse Width Low 1.5 -- ns Read Access Time with Pipeline Register -- 0.334 ns Read Access Time without Pipeline Register -- 2.346 ns Access Time with Feed-Through Write Timing -- 2.346 ns tADDRSU tADDRHD tDSU tDHD tBLKSU tBLKHD tBLK2Q tBLKMPW tRDESU Address Setup Time 0.56 -- ns Address Hold Time 0.282 -- ns Data Setup Time 0.345 -- ns Data Hold Time 0.084 -- ns Block Select Setup Time 0.214 -- ns Block Select Hold Time 0.223 -- ns Block Select to Out Disable Time (when Pipe-Lined Registered -- is Disabled) 1.56 ns Block Select Minimum Pulse Width 0.218 -- ns Read Enable Setup Time 0.532 -- ns DS50003487A-page 80 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-7: Parameter tRDEHD tRDPLESU tRDPLEHD tR2Q tRSTREM tRSTREC tRSTMPW tPLRSTREM tPLRSTREC tPLRSTMPW tSRSTSU tSRSTHD tWESU tWEHD Fmax TABLE 7-8: Parameter tCY tCLKMPWH tCLKMPWL tPLCY tPLCLKMPWH tPLCLKMPWL tCLK2Q RAM1K18 DUAL-PORT MODE FOR DEPTH × WIDTH CONFIGURATION 4KX4-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Read Enable Hold Time 0.073 -- ns Pipelined Read Enable Setup Time (A_DOUT_EN, B_DOUT_EN) 0.256 -- ns Pipelined Read Enable Hold Time (A_DOUT_EN, B_DOUT_EN) 0.106 -- ns Asynchronous Reset to Output Propagation Delay -- 1.562 ns Asynchronous Reset Removal Time 0.522 -- ns Asynchronous Reset Recovery Time 0.005 -- ns Asynchronous Reset Minimum Pulse Width 0.352 -- ns Pipelined Register Asynchronous Reset Removal Time -0.288 -- ns Pipelined Register Asynchronous Reset Recovery Time 0.338 -- ns Pipelined Register Asynchronous Reset Minimum Pulse Width 0.33 -- ns Synchronous Reset Setup Time 0.233 -- ns Synchronous Reset Hold Time 0.037 -- ns Write Enable Setup Time 0.473 -- ns Write Enable Hold Time 0.05 -- ns Maximum Frequency -- 300 MHz RAM1K18 DUAL-PORT MODE FOR DEPTH × WIDTH CONFIGURATION 8KX2-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Clock Period 3.333 -- ns Clock Minimum Pulse Width High 1.5 -- ns Clock Minimum pulse Width Low 1.5 -- ns Pipelined Clock Period 3.333 -- ns Pipelined Clock Minimum Pulse Width High 1.5 -- ns Pipelined Clock Minimum pulse Width Low 1.5 -- ns Read Access Time with Pipeline Register -- 0.332 ns Read Access Time without Pipeline Register -- 2.346 ns Access Time with Feed-Through Write Timing -- 2.346 ns tADDRSU tADDRHD tDSU Address Setup Time Address Hold Time Data Setup Time 0.631 -- ns 0.282 -- ns 0.34 -- ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 81 TABLE 7-8: Parameter tDHD tBLKSU tBLKHD tBLK2Q tBLKMPW tRDESU tRDEHD tRDPLESU tRDPLEHD tR2Q tRSTREM tRSTREC tRSTMPW tPLRSTREM tPLRSTREC tPLRSTMPW tSRSTSU tSRSTHD tWESU tWEHD Fmax TABLE 7-9: Parameter tCY tCLKMPWH tCLKMPWL tPLCY tPLCLKMPWH tPLCLKMPWL RAM1K18 DUAL-PORT MODE FOR DEPTH × WIDTH CONFIGURATION 8KX2-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Data Hold Time 0.084 -- ns Block Select Setup Time 0.214 -- ns Block Select Hold Time 0.223 -- ns Block Select to Out Disable Time (when Pipe-Lined Registered -- is Disabled) 1.56 ns Block Select Minimum Pulse Width 0.218 -- ns Read Enable Setup Time 0.546 -- ns Read Enable Hold Time 0.073 -- ns Pipelined Read Enable Setup Time (A_DOUT_EN, B_DOUT_EN) 0.256 -- ns Pipelined Read Enable Hold Time (A_DOUT_EN, B_DOUT_EN) 0.106 -- ns Asynchronous Reset to Output Propagation Delay -- 1.583 ns Asynchronous Reset Removal Time 0.522 -- ns Asynchronous Reset Recovery Time 0.005 -- ns Asynchronous Reset Minimum Pulse Width 0.352 -- ns Pipelined Register Asynchronous Reset Removal Time -0.288 -- ns Pipelined Register Asynchronous Reset Recovery Time 0.338 -- ns Pipelined Register Asynchronous Reset Minimum Pulse Width 0.33 -- ns Synchronous Reset Setup Time 0.233 -- ns Synchronous Reset Hold Time 0.037 -- ns Write Enable Setup Time 0.504 -- ns Write Enable Hold Time 0.05 -- ns Maximum Frequency -- 300 MHz RAM1K18 DUAL-PORT MODE FOR DEPTH × WIDTH CONFIGURATION 16KX1-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Clock Period 3.333 -- ns Clock Minimum Pulse Width High 1.5 -- ns Clock Minimum pulse Width Low 1.5 -- ns Pipelined Clock Period 3.333 -- ns Pipelined Clock Minimum Pulse Width High 1.5 -- ns Pipelined Clock Minimum pulse Width Low 1.5 -- ns DS50003487A-page 82 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-9: Parameter tCLK2Q RAM1K18 DUAL-PORT MODE FOR DEPTH × WIDTH CONFIGURATION 16KX1-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Read Access Time with Pipeline Register -- 0.332 ns Read Access Time without Pipeline Register -- 2.342 ns Access Time with Feed-Through Write Timing -- 2.342 ns tADDRSU tADDRHD tDSU tDHD tBLKSU tBLKHD tBLK2Q tBLKMPW tRDESU tRDEHD tRDPLESU tRDPLEHD tR2Q tRSTREM tRSTREC tRSTMPW tPLRSTREM tPLRSTREC tPLRSTMPW tSRSTSU tSRSTHD tWESU tWEHD Fmax Address Setup Time 0.646 -- Address Hold Time 0.282 -- Data Setup Time 0.332 -- Data Hold Time 0.084 -- Block Select Setup Time 0.214 -- Block Select Hold Time 0.223 -- Block Select to Out Disable Time (when Pipe-Lined Registered is -- Disabled) 1.559 Block Select Minimum Pulse Width 0.218 -- Read Enable Setup Time 0.547 -- Read Enable Hold Time 0.073 -- Pipelined Read Enable Setup Time (A_DOUT_EN, B_DOUT_EN) 0.256 -- Pipelined Read Enable Hold Time (A_DOUT_EN, B_DOUT_EN) 0.106 -- Asynchronous Reset to Output Propagation Delay -- 1.603 Asynchronous Reset Removal Time 0.522 -- Asynchronous Reset Recovery Time 0.005 -- Asynchronous Reset Minimum Pulse Width 0.352 -- Pipelined Register Asynchronous Reset Removal Time -0.288 -- Pipelined Register Asynchronous Reset Recovery Time 0.338 -- Pipelined Register Asynchronous Reset Minimum Pulse Width 0.33 -- Synchronous Reset Setup Time 0.233 -- Synchronous Reset Hold Time 0.037 -- Write Enable Setup Time 0.468 -- Write Enable Hold Time 0.05 -- Maximum Frequency -- 300 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 83 TABLE 7-10: Parameter tCY tCLKMPWH tCLKMPWL tPLCY tPLCLKMPWH tPLCLKMPWL tCLK2Q tADDRSU tADDRHD tDSU tDHD tBLKSU tBLKHD tBLK2Q tBLKMPW tRDESU tRDEHD tRDPLESU tRDPLEHD tR2Q tRSTREM tRSTREC tRSTMPW tPLRSTREM tPLRSTREC tPLRSTMPW tSRSTSU tSRSTHD tWESU tWEHD Fmax RAM1K18 TWO-PORT MODE FOR DEPTH × WIDTH CONFIGURATION 512X36-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Units Description Min Max Clock Period 3.333 -- ns Clock Minimum Pulse Width High 1.5 -- ns Clock Minimum pulse Width Low 1.5 -- ns Pipelined Clock Period 3.333 -- ns Pipelined Clock Minimum Pulse Width High 1.5 -- ns Pipelined Clock Minimum pulse Width Low 1.5 -- ns Read Access Time with Pipeline Register -- 0.346 ns Read Access Time without Pipeline Register -- 2.322 ns Address Setup Time 0.323 -- ns Address Hold Time 0.282 -- ns Data Setup Time 0.348 -- ns Data Hold Time 0.114 -- ns Block Select Setup Time 0.214 -- ns Block Select Hold Time 0.208 -- ns Block Select to Out Disable Time (when Pipe-Lined Registered -- is Disabled) 2.322 ns Block Select Minimum Pulse Width 0.218 -- ns Read Enable Setup Time 0.463 -- ns Read Enable Hold Time 0.173 -- ns Pipelined Read Enable Setup Time (A_DOUT_EN, B_DOUT_EN) 0.256 -- ns Pipelined Read Enable Hold Time (A_DOUT_EN, B_DOUT_EN) 0.106 -- ns Asynchronous Reset to Output Propagation Delay -- 1.561 ns Asynchronous Reset Removal Time 0.522 -- ns Asynchronous Reset Recovery Time 0.005 -- ns Asynchronous Reset Minimum Pulse Width 0.352 -- ns Pipelined Register Asynchronous Reset Removal Time -0.288 -- ns Pipelined Register Asynchronous Reset Recovery Time 0.338 -- ns Pipelined Register Asynchronous Reset Minimum Pulse Width 0.33 -- ns Synchronous Reset Setup Time 0.233 -- ns Synchronous Reset Hold Time 0.037 -- ns Write Enable Setup Time 0.402 -- ns Write Enable Hold Time 0.25 -- ns Maximum Frequency -- 300 MHz DS50003487A-page 84 2023 Microchip Technology Inc. and its subsidiaries 7.2.2 FPGA FABRIC MICRO SRAM (USRAM) TABLE 7-11: Parameter tCY tCLKMPWH tCLKMPWL tPLCY tPLCLKMPWH tPLCLKMPWL tCLK2Q tADDRSU tADDRHD tRDENSU tRDENHD tBLKSU tBLKHD tBLK2Q tRSTREM tRSTREC tR2Q tSRSTSU tSRSTHD tCCY tCCLKMPWH tCCLKMPWL tBLKCSU tBLKCHD tDINCSU USRAM (RAM64X18) IN 64X18 MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Read Clock Period 4 -- ns Read Clock Minimum Pulse Width High 1.8 -- ns Read Clock Minimum pulse Width Low 1.8 -- ns Read Pipe-line clock period 4 -- ns Read Pipe-line clock Minimum Pulse Width High 1.8 -- ns Read Pipe-line clock Minimum Pulse Width Low 1.8 -- ns Read Access Time with Pipeline Register -- 0.276 ns Read Access Time without Pipeline Register -- 1.738 ns Read Address Setup Time in Synchronous Mode 0.311 -- ns Read Address Setup Time in Asynchronous Mode 1.916 -- ns Read Address Hold Time in Synchronous Mode 0.094 -- ns Read Address Hold Time in Asynchronous Mode -0.803 -- ns Read Enable Setup Time 0.287 -- ns Read Enable Hold Time 0.059 -- ns Read Block Select Setup Time 1.898 -- ns Read Block Select Hold Time -0.671 -- ns Read Block Select to Out Disable Time (when Pipe-Lined Registered is Disabled) -- 2.102 ns Read Asynchronous Reset Removal Time (Pipelined Clock) -0.15 -- ns Read Asynchronous Reset Removal Time (Non-Pipelined 0.047 -- ns Clock) Read Asynchronous Reset Recovery Time (Pipelined Clock) 0.524 -- ns Read Asynchronous Reset Recovery Time (Non-Pipelined 0.244 -- ns Clock) Read Asynchronous Reset to Output Propagation Delay (with -- Pipe-Line Register Enabled) 0.869 ns Read Synchronous Reset Setup Time 0.279 -- ns Read Synchronous Reset Hold Time 0.062 -- ns Write Clock Period 4 -- ns Write Clock Minimum Pulse Width High 1.8 -- ns Write Clock Minimum Pulse Width Low 1.8 -- ns Write Block Setup Time 0.417 -- ns Write Block Hold Time 0.007 -- ns Write Input Data setup Time 0.119 -- ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 85 TABLE 7-11: Parameter tDINCHD tADDRCSU tADDRCHD tWECSU tWECHD Fmax USRAM (RAM64X18) IN 64X18 MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V (CONTINUED) Speed Grade 1 Description Min Max Units Write Input Data hold Time 0.155 -- ns Write Address Setup Time 0.091 -- ns Write Address Hold Time 0.132 -- ns Write Enable Setup Time 0.41 -- ns Write Enable Hold Time -0.027 -- ns Maximum Frequency -- 250 MHz TABLE 7-12: Parameter tCY tCLKMPWH tCLKMPWL tPLCY tPLCLKMPWH tPLCLKMPWL tCLK2Q tADDRSU tADDRHD tRDENSU tRDENHD tBLKSU tBLKHD tBLK2Q tRSTREM tRSTREC USRAM (RAM64X16) IN 64X16 MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Read Clock Period 4 -- ns Read Clock Minimum Pulse Width High 1.8 -- ns Read Clock Minimum pulse Width Low 1.8 -- ns Read Pipe-line clock period 4 -- ns Read Pipe-line clock Minimum Pulse Width High 1.8 -- ns Read Pipe-line clock Minimum Pulse Width Low 1.8 -- ns Read Access Time with Pipeline Register -- 0.276 ns Read Access Time without Pipeline Register -- 1.738 ns Read Address Setup Time in Synchronous Mode 0.311 -- ns Read Address Setup Time in Asynchronous Mode 1.916 -- ns Read Address Hold Time in Synchronous Mode 0.094 -- ns Read Address Hold Time in Asynchronous Mode -0.803 -- ns Read Enable Setup Time 0.287 -- ns Read Enable Hold Time 0.059 -- ns Read Block Select Setup Time 1.898 -- ns Read Block Select Hold Time -0.671 -- ns Read Block Select to Out Disable Time (when Pipe-Lined Registered is Disabled) -- 2.102 ns Read Asynchronous Reset Removal Time (Pipelined Clock) -0.15 -- ns Read Asynchronous Reset Removal Time (Non-Pipelined Clock) 0.047 -- ns Read Asynchronous Reset Recovery Time (Pipelined Clock) 0.524 -- ns Read Asynchronous Reset Recovery Time (Non-Pipelined 0.244 -- ns Clock) DS50003487A-page 86 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-12: Parameter tR2Q tSRSTSU tSRSTHD tCCY tCCLKMPWH tCCLKMPWL tBLKCSU tBLKCHD tDINCSU tDINCHD tADDRCSU tADDRCHD tWECSU tWECHD Fmax USRAM (RAM64X16) IN 64X16 MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V (CONTINUED) Speed Grade 1 Description Min Max Units Read Asynchronous Reset to Output Propagation Delay (With -- Pipe-Line Register Enabled) 0.866 ns Read Synchronous Reset Setup Time 0.279 -- ns Read Synchronous Reset Hold Time 0.062 -- ns Write Clock Period 4 -- ns Write Clock Minimum Pulse Width High 1.8 -- ns Write Clock Minimum Pulse Width Low 1.8 -- ns Write Block Setup Time 0.417 -- ns Write Block Hold Time 0.007 -- ns Write Input Data setup Time 0.119 -- ns Write Input Data hold Time 0.155 -- ns Write Address Setup Time 0.091 -- ns Write Address Hold Time 0.132 -- ns Write Enable Setup Time 0.41 -- ns Write Enable Hold Time -0.027 -- ns Maximum Frequency -- 250 MHz TABLE 7-13: Parameter tCY tCLKMPWH tCLKMPWL tPLCY tPLCLKMPWH tPLCLKMPWL tCLK2Q tADDRSU tADDRHD tRDENSU tRDENHD USRAM (RAM128X9) IN 128X9 MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Read Clock Period 4 -- ns Read Clock Minimum Pulse Width High 1.8 -- ns Read Clock Minimum pulse Width Low 1.8 -- ns Read Pipe-line clock period 4 -- ns Read Pipe-line clock Minimum Pulse Width High 1.8 -- ns Read Pipe-line clock Minimum Pulse Width Low 1.8 -- ns Read Access Time with Pipeline Register -- 0.276 ns Read Access Time without Pipeline Register -- 1.776 ns Read Address Setup Time in Synchronous Mode 0.311 -- ns Read Address Setup Time in Asynchronous Mode 1.959 -- ns Read Address Hold Time in Synchronous Mode 0.125 -- ns Read Address Hold Time in Asynchronous Mode -0.704 -- ns Read Enable Setup Time 0.287 -- ns Read Enable Hold Time 0.059 -- ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 87 TABLE 7-13: Parameter tBLKSU tBLKHD tBLK2Q tRSTREM tRSTREC tR2Q tSRSTSU tSRSTHD tCCY tCCLKMPWH tCCLKMPWL tBLKCSU tBLKCHD tDINCSU tDINCHD tADDRCSU tADDRCHD tWECSU tWECHD Fmax USRAM (RAM128X9) IN 128X9 MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V (CONTINUED) Speed Grade 1 Description Min Max Units Read Block Select Setup Time 1.898 -- ns Read Block Select Hold Time -0.671 -- ns Read Block Select to Out Disable Time (when Pipe-Lined Registered is Disabled) -- 2.14 ns Read Asynchronous Reset Removal Time (Pipelined Clock) -0.15 -- ns Read Asynchronous Reset Removal Time (Non-Pipelined Clock) 0.047 -- ns Read Asynchronous Reset Recovery Time (Pipelined Clock) 0.524 -- ns Read Asynchronous Reset Recovery Time (Non-Pipelined 0.244 -- ns Clock) Read Asynchronous Reset to Output Propagation Delay (with -- Pipe-Line Register Enabled) 0.865 ns Read Synchronous Reset Setup Time 0.279 -- ns Read Synchronous Reset Hold Time 0.062 -- ns Write Clock Period 4 -- ns Write Clock Minimum Pulse Width High 1.8 -- ns Write Clock Minimum Pulse Width Low 1.8 -- ns Write Block Setup Time 0.417 -- ns Write Block Hold Time 0.007 -- ns Write Input Data setup Time 0.104 -- ns Write Input Data hold Time 0.142 -- ns Write Address Setup Time 0.091 -- ns Write Address Hold Time 0.24 -- ns Write Enable Setup Time 0.41 -- ns Write Enable Hold Time -0.027 -- ns Maximum Frequency -- 250 MHz DS50003487A-page 88 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-14: Parameter tCY tCLKMPWH tCLKMPWL tPLCY tPLCLKMPWH tPLCLKMPWL tCLK2Q tADDRSU tADDRHD tRDENSU tRDENHD tBLKSU tBLKHD tBLK2Q tRSTREM tRSTREC tR2Q tSRSTSU tSRSTHD tCCY tCCLKMPWH tCCLKMPWL tBLKCSU tBLKCHD tDINCSU tDINCHD tADDRCSU USRAM (RAM128X8) IN 128X8 MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Read Clock Period 4 -- ns Read Clock Minimum Pulse Width High 1.8 -- ns Read Clock Minimum pulse Width Low 1.8 -- ns Read Pipe-line clock period 4 -- ns Read Pipe-line clock Minimum Pulse Width High 1.8 -- ns Read Pipe-line clock Minimum Pulse Width Low 1.8 -- ns Read Access Time with Pipeline Register -- 0.276 ns Read Access Time without Pipeline Register -- 1.776 ns Read Address Setup Time in Synchronous Mode 0.311 -- ns Read Address Setup Time in Asynchronous Mode 1.959 -- ns Read Address Hold Time in Synchronous Mode 0.125 -- ns Read Address Hold Time in Asynchronous Mode -0.704 -- ns Read Enable Setup Time 0.287 -- ns Read Enable Hold Time 0.059 -- ns Read Block Select Setup Time 1.898 -- ns Read Block Select Hold Time -0.671 -- ns Read Block Select to Out Disable Time (when Pipe-Lined Registered is Disabled) -- 2.14 ns Read Asynchronous Reset Removal Time (Pipelined Clock) -0.15 -- ns Read Asynchronous Reset Removal Time (Non-Pipelined Clock) 0.047 -- ns Read Asynchronous Reset Recovery Time (Pipelined Clock) 0.524 -- ns Read Asynchronous Reset Recovery Time (Non-Pipelined 0.244 -- ns Clock) Read Asynchronous Reset to Output Propagation Delay (With -- Pipe-Line Register Enabled) 0.865 ns Read Synchronous Reset Setup Time 0.279 -- ns Read Synchronous Reset Hold Time 0.062 -- ns Write Clock Period 4 -- ns Write Clock Minimum Pulse Width High 1.8 -- ns Write Clock Minimum Pulse Width Low 1.8 -- ns Write Block Setup Time 0.417 -- ns Write Block Hold Time 0.007 -- ns Write Input Data setup Time 0.104 -- ns Write Input Data hold Time 0.142 -- ns Write Address Setup Time 0.091 -- ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 89 TABLE 7-14: Parameter tADDRCHD tWECSU tWECHD Fmax USRAM (RAM128X8) IN 128X8 MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V (CONTINUED) Speed Grade 1 Description Min Max Units Write Address Hold Time 0.24 -- ns Write Enable Setup Time 0.41 -- ns Write Enable Hold Time -0.027 -- ns Maximum Frequency -- 250 MHz TABLE 7-15: Parameter tCY tCLKMPWH tCLKMPWL tPLCY tPLCLKMPWH tPLCLKMPWL tCLK2Q tADDRSU tADDRHD tRDENSU tRDENHD tBLKSU tBLKHD tBLK2Q tRSTREM tRSTREC tR2Q tSRSTSU USRAM (RAM256X4) IN 256X4 MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Read Clock Period 4 -- ns Read Clock Minimum Pulse Width High 1.8 -- ns Read Clock Minimum pulse Width Low 1.8 -- ns Read Pipe-line clock period 4 -- ns Read Pipe-line clock Minimum Pulse Width High 1.8 -- ns Read Pipe-line clock Minimum Pulse Width Low 1.8 -- ns Read Access Time with Pipeline Register -- 0.276 ns Read Access Time without Pipeline Register -- 1.812 ns Read Address Setup Time in Synchronous Mode 0.311 -- ns Read Address Setup Time in Asynchronous Mode 1.993 -- ns Read Address Hold Time in Synchronous Mode 0.125 -- ns Read Address Hold Time in Asynchronous Mode -0.669 -- ns Read Enable Setup Time 0.287 -- ns Read Enable Hold Time 0.059 -- ns Read Block Select Setup Time 1.898 -- ns Read Block Select Hold Time -0.671 -- ns Read Block Select to Out Disable Time (when Pipe-Lined Registered is Disabled) -- 2.166 ns Read Asynchronous Reset Removal Time (Pipelined Clock) -0.15 -- ns Read Asynchronous Reset Removal Time (Non-Pipelined Clock) 0.047 -- ns Read Asynchronous Reset Recovery Time (Pipelined Clock) 0.524 -- ns Read Asynchronous Reset Recovery Time (Non-Pipelined 0.244 -- ns Clock) Read Asynchronous Reset to Output Propagation Delay (With -- Pipe-Line Register Enabled) 0.863 ns Read Synchronous Reset Setup Time 0.279 -- ns DS50003487A-page 90 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-15: Parameter tSRSTHD tCCY tCCLKMPWH tCCLKMPWL tBLKCSU tBLKCHD tDINCSU tDINCHD tADDRCSU tADDRCHD tWECSU tWECHD Fmax USRAM (RAM256X4) IN 256X4 MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V (CONTINUED) Description Speed Grade 1 Min Max Units Read Synchronous Reset Hold Time 0.062 -- ns Write Clock Period 4 -- ns Write Clock Minimum Pulse Width High 1.8 -- ns Write Clock Minimum Pulse Width Low 1.8 -- ns Write Block Setup Time 0.417 -- ns Write Block Hold Time 0.007 -- ns Write Input Data setup Time 0.104 -- ns Write Input Data hold Time 0.142 -- ns Write Address Setup Time 0.091 -- ns Write Address Hold Time 0.253 -- ns Write Enable Setup Time 0.41 -- ns Write Enable Hold Time -0.027 -- ns Maximum Frequency -- 250 MHz TABLE 7-16: Parameter tCY tCLKMPWH tCLKMPWL tPLCY tPLCLKMPWH tPLCLKMPWL tCLK2Q tADDRSU tADDRHD tRDENSU tRDENHD tBLKSU tBLKHD USRAM (RAM512X2) IN 512X2 MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Description Min Max Units Read Clock Period 4 -- ns Read Clock Minimum Pulse Width High 1.8 -- ns Read Clock Minimum pulse Width Low 1.8 -- ns Read Pipe-line clock period 4 -- ns Read Pipe-line clock Minimum Pulse Width High 1.8 -- ns Read Pipe-line clock Minimum Pulse Width Low 1.8 -- ns Read Access Time with Pipeline Register -- 0.276 ns Read Access Time without Pipeline Register -- 1.824 ns Read Address Setup Time in Synchronous Mode 0.311 -- ns Read Address Setup Time in Asynchronous Mode 2.023 -- ns Read Address Hold Time in Synchronous Mode 0.141 -- ns Read Address Hold Time in Asynchronous Mode -0.599 -- ns Read Enable Setup Time 0.287 -- ns Read Enable Hold Time 0.059 -- ns Read Block Select Setup Time 1.898 -- ns Read Block Select Hold Time -0.671 -- ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 91 TABLE 7-16: Parameter tBLK2Q tRSTREM tRSTREC tR2Q tSRSTSU tSRSTHD tCCY tCCLKMPWH tCCLKMPWL tBLKCSU tBLKCHD tDINCSU tDINCHD tADDRCSU tADDRCHD tWECSU tWECHD Fmax USRAM (RAM512X2) IN 512X2 MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V (CONTINUED) Speed Grade 1 Description Min Max Units Read Block Select to Out Disable Time (when Pipe-Lined -- 2.219 ns Registered is Disabled) Read Asynchronous Reset Removal Time (Pipelined Clock) -0.15 -- ns Read Asynchronous Reset Removal Time (Non-Pipelined Clock) 0.047 -- ns Read Asynchronous Reset Recovery Time (Pipelined Clock) 0.524 -- ns Read Asynchronous Reset Recovery Time (Non-Pipelined 0.244 -- ns Clock) Read Asynchronous Reset to Output Propagation Delay (With -- Pipe-Line Register Enabled) 0.862 ns Read Synchronous Reset Setup Time 0.279 -- ns Read Synchronous Reset Hold Time 0.062 -- ns Write Clock Period 4 -- ns Write Clock Minimum Pulse Width High 1.8 -- ns Write Clock Minimum Pulse Width Low 1.8 -- ns Write Block Setup Time 0.417 -- ns Write Block Hold Time 0.007 -- ns Write Input Data setup Time 0.104 -- ns Write Input Data hold Time 0.142 -- ns Write Address Setup Time 0.091 -- ns Write Address Hold Time 0.255 -- ns Write Enable Setup Time 0.41 -- ns Write Enable Hold Time -0.027 -- ns Maximum Frequency -- 250 MHz TABLE 7-17: Parameter tCY tCLKMPWH tCLKMPWL tPLCY tPLCLKMPWH tPLCLKMPWL USRAM (RAM1024X1) IN 1024X1 MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Units Description Min Max Read Clock Period 4 -- ns Read Clock Minimum Pulse Width High 1.8 -- ns Read Clock Minimum pulse Width Low 1.8 -- ns Read Pipe-line clock period 4 -- ns Read Pipe-line clock Minimum Pulse Width High 1.8 -- ns Read Pipe-line clock Minimum Pulse Width Low 1.8 -- ns DS50003487A-page 92 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-17: Parameter tCLK2Q tADDRSU tADDRHD tRDENSU tRDENHD tBLKSU tBLKHD tBLK2Q tRSTREM tRSTREC tR2Q tSRSTSU tSRSTHD tCCY tCCLKMPWH tCCLKMPWL tBLKCSU tBLKCHD tDINCSU tDINCHD tADDRCSU tADDRCHD tWECSU tWECHD Fmax USRAM (RAM1024X1) IN 1024X1 MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V (CONTINUED) Speed Grade 1 Units Description Min Max Read Access Time with Pipeline Register -- 0.274 ns Read Access Time without Pipeline Register -- 1.839 ns Read Address Setup Time in Synchronous Mode 0.311 -- ns Read Address Setup Time in Asynchronous Mode 2.041 -- ns Read Address Hold Time in Synchronous Mode 0.141 -- ns Read Address Hold Time in Asynchronous Mode -0.623 -- ns Read Enable Setup Time 0.287 -- ns Read Enable Hold Time 0.059 -- ns Read Block Select Setup Time 1.898 -- ns Read Block Select Hold Time -0.671 -- ns Read Block Select to Out Disable Time (when Pipe-Lined Registered is Disabled) -- 2.236 ns Read Asynchronous Reset Removal Time (Pipelined Clock) -0.15 -- ns Read Asynchronous Reset Removal Time (Non-Pipelined Clock) 0.047 -- ns Read Asynchronous Reset Recovery Time (Pipelined Clock) 0.524 -- ns Read Asynchronous Reset Recovery Time (Non-Pipelined 0.244 -- ns Clock) Read Asynchronous Reset to Output Propagation Delay (With -- Pipe-Line Register Enabled) 0.862 ns Read Synchronous Reset Setup Time 0.279 -- ns Read Synchronous Reset Hold Time 0.062 -- ns Write Clock Period 4 -- ns Write Clock Minimum Pulse Width High 1.8 -- ns Write Clock Minimum Pulse Width Low 1.8 -- ns Write Block Setup Time 0.417 -- ns Write Block Hold Time 0.007 -- ns Write Input Data setup Time 0.003 -- ns Write Input Data hold Time 0.142 -- ns Write Address Setup Time 0.091 -- ns Write Address Hold Time 0.255 -- ns Write Enable Setup Time 0.41 -- ns Write Enable Hold Time -0.027 -- ns Maximum Frequency -- 250 MHz 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 93 7.3 Embedded NVM (eNVM) Characteristics TABLE 7-18: ENVM READ PERFORMANCE--WORST-CASE CONDITIONS: VDD = 1.14V, VPPNVM = VPP = 2.375V Symbol Description Operating Temperature Range Unit TJ Junction Temperature Range Speed grade -55°C to 125°C -40°C to 100°C 0°C to 85°C °C -1 Std -1 Std -1 Std -- FMAXREAD eNVM Maximum Read Frequency 25 25 25 25 25 25 MHz TABLE 7-19: ENVM PAGE PROGRAMMING--WORST-CASE CONDITIONS: VDD = 1.14V, VPPNVM = VPP = 2.375V Symbol Description Operating Temperature Range Unit TJ Junction Temperature Range Speed grade -55°C to 125°C -40°C to 100°C 0°C to 85°C °C -1 Std -1 Std -1 Std -- tPAGEPGM eNVM Page Programming Time 40 40 40 40 40 40 ms 7.4 Crystal Oscillator The following table lists the electrical characteristics of the crystal oscillator in the IGLOO2 FPGA and SmartFusion2 SoC FPGAs. TABLE 7-20: Parameter FXTAL ACCXTAL CYCXTAL JITPERXTAL JITCYCXTAL IDYNXTAL VIHXTAL VILXTAL SUXTAL ELECTRICAL CHARACTERISTICS OF THE CRYSTAL OSCILLATOR HIGH GAIN MODE (20 MHZ)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Description Min Typ Max Units Operating frequency -- 20 -- MHz Accuracy -- -- 0.006 % Output duty cycle -- 49-51 47-53 % Output Period Jitter (peak to peak) -- 200 300 ps Output Cycle to Cycle Jitter (peak to -- peak) 200 550 ps Operating current -- 1.5 -- mA Input logic level High 0.9 × VPP -- -- V Input logic level Low -- -- 0.1 × VPP V Startup time (with regard to stable -- -- 1 ms oscillator output) DS50003487A-page 94 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-21: Parameter FXTAL ACCXTAL CYCXTAL JITPERXTAL JITCYCXTAL IDYNXTAL VIHXTAL VILXTAL SUXTAL ELECTRICAL CHARACTERISTICS OF THE CRYSTAL OSCILLATOR MEDIUM GAIN MODE (2 MHZ)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14 V Description Min Typ Max Units Operating frequency 2 MHz Accuracy 0.003 % Output duty cycle 4951 4753 % Output Period Jitter (peak to peak) 1 5 ns Output Cycle to Cycle Jitter (peak to peak) 1 5 ns Operating current 0.3 mA Input logic level High 0.9 × VPP V Input logic level Low 0.1 × VPP V Startup time (with regard to stable oscillator output) 4.5 ms TABLE 7-22: Parameter FXTAL ACCXTAL CYCXTAL JITPERXTAL JITCYCXTAL IDYNXTAL VIHXTAL VILXTAL SUXTAL ELECTRICAL CHARACTERISTICS OF THE CRYSTAL OSCILLATOR LOW GAIN MODE (32 KHZ)--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14 V Description Min Typ Max Units Operating frequency 32 kHz Accuracy 0.006 % Output duty cycle 4951 45.554.5 % Output Period Jitter (peak to peak) 150 300 ns Output Cycle to Cycle Jitter (peak to peak) 150 300 ns Operating current 0.044 mA Input logic level High 0.9 × VPP V Input logic level Low 0.1 × VPP V Startup time (with regard to stable oscillator output) 120 ms 7.5 Clock Conditioning Circuits (CCC) TABLE 7-23: Parameter IGLOO® 2 AND SMARTFUSION® 2 SOC FPGAS CCC/PLL SPECIFICATION-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Conditions Min Typ Max Units Notes Clock conditioning circuitry input frequency fIN_CCC All CCC 32 kHz Capable CCC 1 0.032 -- 200 -- 200 MHz -- MHz -- Clock conditioning circuitry -- output frequency fOUT_CCC PLL VCO frequency -- 0.078 500 -- 400 -- 1000 MHz 1 MHz 2 Delay increments in -- programmable delay blocks -- 75 100 ps -- 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 95 TABLE 7-23: IGLOO® 2 AND SMARTFUSION® 2 SOC FPGAS CCC/PLL SPECIFICATION-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Number of programmable -- values in each programmable delay block -- -- 64 ---- Acquisition time fIN 1 MHz -- fIN = 32kHz -- Input Duty Cycle (Reference Internal Feedback Clock) 70 100 1 16 µs -- ms -- 1 MHz fIN_CCC 25 MHz 10 -- 90 25 MHz fIN_CCC 100 MHz 25 -- 75 100 MHz fIN_CCC 150 MHz 35 -- 65 150 MHz fIN_CCC 200 MHz 45 -- 55 External Feedback (CCC, FPGA, Off-chip) %-- %-- %-- %-- Output duty cycle 1 MHz fIN_CCC 25 MHz 25 25 MHz fIN_CCC 35 MHz 35 35 MHz fIN_CCC 50 MHz 45 005, 010, and 025 Devices 46 060 and 090 Devices 44 Spread Spectrum Characteristics -- 75 -- 65 -- 55 -- 52 -- 52 %-- %-- %-- %-- %-- Modulation frequency range -- Modulation depth range -- Modulation depth control -- 25 35 50 kHz -- 0 -- 1.5 %-- -- 0.5 -- %-- Note 1: 2: The minimum output clock frequency is limited by the PLL. For more information refer to the SmartFusion 2 and IGLOO 2 Clocking Resources User Guide. The PLL is used in conjunction with the Clock Conditioning Circuitry. Performance will be limited by the CCC output frequency. TABLE 7-24: IGLOO® 2 AND SMARTFUSION® 2 SOC FPGAS CCC/PLL JITTER SPECIFICATIONS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Parameter Conditions/Package Combinations Units Notes CCC Output Peak-toPeak Period Jitter fOUT_CCC 010 FGG484 Packages -- SSO = 0 -- -- -- -- ---- 0 < SSO SSO SSO SSO <= 2 <= 4 <= 8 <= 16 -- Note1 20 MHz to 100 MHz Max(110, ± 1% x (1/fOUT_CCC)) Max(150, ± 1% x (1/fOUT_CCC)) ps -- 100 MHz to 400 MHz 120 150 170 ps -- DS50003487A-page 96 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-24: IGLOO® 2 AND SMARTFUSION® 2 SOC FPGAS CCC/PLL JITTER SPECIFICATIONS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V (CONTINUED) Parameter 025 FGG484 Package Conditions/Package Combinations 0 < SSO <=16 Units Notes Note1 20 MHz to 74 MHz ± 1% x (1/fOUT_CCC) ps -- 74 MHz to 400 MHz 005 FGG484 Package 210 0 < SSO <=16 ps -- Note1 20 MHz to 53 MHz ± 1% x (1/fOUT_CCC) ps -- 53 MHz to 400 MHz 090 FGG484 and FGG676 270 0 < SSO <=16 ps -- Note1 20 MHz to 100 MHz ± 1% x (1/fOUT_CCC) ps -- 100 MHz to 400 MHz 150 Note 1: SSO Data is based on LVCMOS 2.5V MSIO and/or MSIOD Bank I/Os. ps -- 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 97 TABLE 7-25: PROGRAMMING VDD = 1.2V1 TIME--TYPICAL AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 25°C, Auto Progra mming Auto Update Progra mming Recove ry JTAG 2 Step IAP MSS/Cortex-M3 ISP (SmartFusion 2 Only) SPI CLK = 100 KHz SPI CLK = 12.5 MHz SPI CLK = 12.5 MHz Device Image Size Bytes Program Verify Authenticate Program Verify Authenticate Program Verify Program Program Program Units Fabric Only eNVM Only M2S010/ 568,784 28 18 7 23 12 10 26 14 77 35 35 sec M2GL010 M2S025/ 1,223,504 51 26 14 33 23 21 39 29 150 41 41 sec M2GL025 M2S060/ 2,418,896 77 54 39 61 50 44 65 54 291 82 82 sec M2GL060 M2S090/ 3,645,968 113 126 60 84 73 66 90 79 427 108 108 sec M2GL090 M2S010/ 274,816 78 9 4 76 11 4 82 7 86 87 87 sec M2GL010 M2S025/ 274,816 78 9 4 78 10 4 82 8 87 86 86 sec M2GL025 M2S060/ 268,480 76 8 5 76 22 6 80 8 78 86 86 sec M2GL060 M2S090/ 544,496 154 15 10 152 43 10 157 15 154 162 162 sec M2GL090 M2S010/ 842,688 107 20 11 100 21 15 107 21 161 113 113 sec M2GL010 M2S025/ 1,497,408 120 35 19 113 32 26 121 35 229 121 121 sec M2GL025 M2S060/ 2,686,464 158 70 43 137 70 48 143 60 368 158 158 sec M2GL060 M2S090/ 4,190,208 266 147 68 236 115 75 244 91 582 260 260 sec M2GL090 1. External SPI flash part# AT25DF641-s3H was used during this measurement. Fabric + eNVM DS50003487A-page 98 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-26: PROGRAMMING TIME--WORST-CASE 100°C, VDD = 1.14V1 CONDITIONS GRADE 2 CONDITIONS: TJ = Auto Progra mming Auto Update Progra mming Recove ry JTAG 2 Step IAP MSS/Cortex-M3 ISP (SmartFusion 2 Only) SPI CLK = 100 KHz SPI CLK = 12.5 MHz SPI CLK = 12.5 MHz Device Image Size Bytes Program Verify Authenticate Program Verify Authenticate Program Verify Program Program Program Units Fabric Only eNVM Only M2S010/ 568,784 50 18 7 45 12 10 48 14 99 57 57 sec M2GL010 M2S025/ 1,223,504 73 26 14 55 23 21 61 29 150 63 63 sec M2GL025 M2S060/ 2,418,896 99 54 39 83 50 44 87 54 313 104 104 sec M2GL060 M2S090/ 3,645,968 135 126 60 106 73 66 112 79 449 130 130 sec M2GL090 M2S010/ 274,816 100 9 4 98 11 4 104 7 108 109 109 sec M2GL010 M2S025/ 274,816 100 9 4 100 10 4 104 8 109 108 108 sec M2GL025 M2S060/ 268,480 98 8 5 98 22 6 102 8 100 108 108 sec M2GL060 M2S090/ 544,496 176 15 10 174 43 10 179 15 176 184 184 sec M2GL090 M2S010/ 842,688 129 20 11 122 21 15 129 21 183 135 135 sec M2GL010 M2S025/ 1,497,408 142 35 19 135 32 26 143 35 251 143 143 sec M2GL025 M2S060/ 2,686,464 180 70 43 159 70 48 165 60 390 180 180 sec M2GL060 M2S090/ 4,190,208 288 147 68 258 115 75 266 91 604 282 282 sec M2GL090 1. External SPI flash part# AT25DF641-s3H was used during this measurement. Fabric + eNVM 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 99 7.6 JTAG TABLE 7-27: JTAG 1532--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V -1 Speed Grade Parameter Description 005 010 025 060 090 Units tTCK2Q tRSTB2Q tDISU tDIHD tTMSSU tTMDHD tTRSTREM tTRSTREC FTCKMAX Clock to Q (data out) 7.71 Reset to Q (data out) 7.91 Test Data Input Setup Time -1.07 Test Data Input Hold Time 2.43 Test Mode Select Setup Time -0.75 Test Mode Select Hold Time 1.41 ResetB Removal Time -0.81 ResetB Recovery Time -0.81 TCK Maximum frequency 25 7.91 6.54 -0.70 2.38 -0.86 1.48 -1.1 -1.1 25 7.95 6.27 -0.70 2.47 -1.13 1.98 -1.38 -1.38 25 8.54 8.70 -1.20 2.55 -0.99 1.71 -1.24 -1.23 25 9.21 7.94 -1.33 2.71 -1.03 1.69 -0.8 -0.8 25 ns ns ns ns ns ns ns ns MHz 7.7 Power-up to Functional Times This section describes the maximum power-up to functional time in worst-case automotive Grade 2 conditions, TJ = 125 °C, VDD = 1.14V. TABLE 7-28: MAXIMUM POWER-UP TO FUNCTIONAL TIME WHEN MSS/HPMS IS USED (US) Parameter From To Description 005 010 025 060 090 TPOR2OUT POWER_ON_ Output available at I/O Fabric to output RESET_N 647 500 531 474 524 TPOR2MSSRST POWER_ON_ MSS_RESET_N_M2F Fabric to MSS RESET_N 644 497 528 468 518 TMSSRST2OUT MSS_RESET_ Output available at I/O MSS to output N_M2F 3.6 3.6 3.6 4.9 4.8 TVDD2OUT VDD Output available at I/O VDD at its minimum 3096 2975 3012 2869 2992 threshold level to output TVDD2POR VDD POWER_ON_RESET_ VDD at its minimum 2476 2487 2496 2406 2563 N threshold level to Fabric TVDD2MSSRST VDD MSS_RESET_N_M2F VDD at its minimum 3093 2972 3008 2864 2987 threshold level to MSS TVDD2WPU VDD DDRIO Inbuf Weak Pull VDD to Inbuf Weak 2500 2487 2509 2507 2519 Pull VDD MSIO Inbuf Weak Pull VDD to Inbuf Weak 2504 2491 2510 2517 2525 Pull VDD MSIOD Inbuf Weak Pull VDD to Inbuf Weak 2479 2468 2493 2486 2499 Pull DS50003487A-page 100 2023 Microchip Technology Inc. and its subsidiaries FIGURE 7-1: POWER-UP TO FUNCTIONAL TIMING DIAGRAM WHEN MSS/HPMS IS USED DEVRST_N VPP/VDDIx VDD RCOSC_50MHz INBUF INBUF WEAK PULL (MSIO/MSIOD/DDRIO) POWER_ON_RESET_N MSS_RESET_N_M2F OUTBUF Tri-state High-Z Tri-state High-Z TVDD2WPU TVDD2POR TVDD2MSSRST TVDD2OUT TPOR2MSSRST TMSSRST2OUT TPOR2OUT TABLE 7-29: MAXIMUM POWER-UP TO FUNCTIONAL TIME WHEN MSS/HPMS IS NOT USED (US) Parameter From To Description 005 010 025 060 090 TPOR2OUT POWER_ON_ Output available at I/O Fabric to output RESET_N 114 114 114 114 114 TVDD2OUT VDD Output available at I/O VDD at its minimum 2587 threshold level to output 2600 2607 2591 2600 TVDD2POR VDD POWER_ON_RESET_ VDD at its minimum 2474 N threshold level to Fabric 2486 2493 2477 2486 TVDD2WPU VDD DDRIO Inbuf Weak Pull VDD to Inbuf Weak 2500 2487 2509 2507 2519 Pull MSIO Inbuf Weak Pull VDD to Inbuf Weak 2504 2491 2510 2517 2525 Pull MSIOD Inbuf Weak Pull VDD to Inbuf Weak 2479 2468 2493 2486 2499 Pull 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 101 FIGURE 7-2: POWER-UP TO FUNCTIONAL TIMING DIAGRAM WHEN MSS/HPMS IS NOT USED DEVRST_N VPP/VDDIx VDD RCOSC_50MHz INBUF INBUF WEAK PULL (MSIO/MSIOD/DDRIO) POWER_ON_RESET_N OUTBUF Tri-state High-Z Tri-state High-Z TVDD2WPU TVDD2POR TVDD2OUT TPOR2OUT 7.8 DEVRST_N Characteristics TABLE 7-30: DEVRST_N CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V All Devices/Speed Grades Symbol Description Min Typ Max Units TRAMPDEVRSTN DEVRST_N ramp time -- -- 1 µs FMAXPDEVRSTN DEVRST_N cycling rate -- -- 100 kHz Notes -- -- 7.9 DEVRST_N to Functional Times This section describes the maximum DEVRST_N to functional time in worst-case automotive Grade 2 conditions, TJ = 100 °C, VDD = 1.14V. TABLE 7-31: MAXIMUM POWER-UP TO FUNCTIONAL TIME WHEN MSS/HPMS IS USED (US) Parameter From To Description 005 010 025 060 090 TPOR2OUT POWER_ON Output available Fabric to output _RESET_N at I/O 518 501 527 422 419 TPOR2MSSRST POWER_ON MSS_RESET_N_ Fabric to MSS _RESET_N M2F 515 497 524 417 414 TMSSRST2OUT MSS_RESET Output available MSS to output _N_M2F at I/O 3.5 3.5 3.5 4.8 4.8 DS50003487A-page 102 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-31: MAXIMUM POWER-UP TO FUNCTIONAL TIME WHEN MSS/HPMS IS USED (US) TDEVRST2OUT DEVRST_N Output available VDD at its minimum at I/O threshold level to output 706 768 715 641 635 TDEVRST2POR POWER_ON_RE VDD at its minimum SET_N threshold level to Fabric 233 289 216 237 234 TDEVRST2MSS RST TDEVRST2WPU MSS_RESET_N_ VDD at its minimum M2F threshold level to MSS 702 765 712 636 630 DDRIO Inbuf Weak Pull DEVRST_N to Inbuf Weak 208 202 197 216 215 Pull MSIO Inbuf Weak DEVRST_N to Inbuf Weak 208 202 197 216 215 Pull Pull MSIOD Inbuf Weak Pull DEVRST_N to Inbuf Weak 208 202 197 216 215 Pull FIGURE 7-3: DEVRST_N TO FUNCTIONAL TIMING DIAGRAM WHEN MSS/HPMS IS USED VDD/VPP/VDDIx RCOSC_50MHz DEVRST_N INBUF INBUF WEAK PULL (MSIO/MSIOD/DDRIO) POWER_ON_RESET_N MSS_RESET_N_M2F OUTBUF Tri-state High-Z Tri-state High-Z TDEVRST2WPU TDEVRST2POR TDEVRST2MSSRST TDEVRST2OUT TPOR2MSSRST TMSSRST2OUT TPOR2OUT 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 103 TABLE 7-32: MAXIMUM POWER-UP TO FUNCTIONAL TIME WHEN MSS/HPMS IS NOT USED (US) Parameter From To Description 005 010 025 060 090 TPOR2OUT POWER_ON_ Output Fabric to output RESET_N available at I/O 114 116 113 115 115 TDEVRST2OUT DEVRST_N Output VDD at its minimum 314 353 314 343 341 available at I/O threshold level to output TDEVRST2POR POWER_ON_ VDD at its minimum 200 238 201 230 229 RESET_N threshold level to Fabric TDEVRST2WPU DDRIO Inbuf DEVRST_N to Inbuf Weak 208 202 197 216 215 Weak Pull Pull MSIO Inbuf Weak Pull DEVRST_N to Inbuf Weak 208 202 197 216 215 Pull MSIOD Inbuf DEVRST_N to Inbuf Weak 208 202 197 216 215 Weak Pull Pull FIGURE 7-4: DEVRST_N TO FUNCTIONAL TIMING DIAGRAM WHEN MSS/HPMS IS NOT USED VDD/VPP/VDDIx RCOSC_50MHz DEVRST_N INBUF Tri-state High-Z TDEVRST2WPU POWER_ON_RESET_N INBUF WEAOKUTPBUULLF (MSIO/MSIOD/DDRIO) Tri-state High-Z TDEVRST2POR TDEVRST2OUT TPOR2OUT DS50003487A-page 104 2023 Microchip Technology Inc. and its subsidiaries 7.10 System Controller SPI Characteristics TABLE 7-33: SYSTEM CONTROLLER SPI CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V All Devices/Speed Grades Units Symbol Description Conditions Min Typ Max SPIFMAX Maximum operating frequency of SPI interface 20 MHz sp1 SC_SPI_SCK minimum -- period 20 -- -- ns sp2 SC_SPI_SCK minimum -- pulse width high 10 -- -- ns sp3 sp41 SC_SPI_SCK minimum pulse width low SC_SPI_SCK, SC_SPI_SDO, SC_SPI_SS rise time (10%-90%) 1 sp51 SC_SPI_SCK, SC_SPI_SDO, SC_SPI_SS fall time (10%-90%) 1 SPI Master Configuration2 -- 10 I/O Configuration: LVTTL -- 3.3V- 20mA AC Loading: 35pF Test Conditions: Typical Voltage, 25C I/O Configuration: LVTTL -- 3.3V- 20mA AC Loading: 35pF Test Conditions: Typical Voltage, 25C -- 1.239 -- ns -- ns 1.245 -- ns SPI Master Configuration (Applicable to 005, 010, 025 Devices) sp6m SPI_[0|1]_DO setup time -- (SPI_x_CLK_period/2) -- - 8.0 -- ns sp7m SPI_[0|1]_DO hold time -- (SPI_x_CLK_period/2) -- - 2.5 -- ns sp8m SPI_[0|1]_DI setup time -- 12 -- -- ns sp9m SPI_[0|1]_DI hold time -- 2.5 -- -- ns SPI Slave Configuration (Applicable to 005, 010, 025 Devices) sp6s SPI_[0|1]_DO setup time -- (SPI_x_CLK_period/2) -- - 17.0 -- ns sp7s SPI_[0|1]_DO hold time -- (SPI_x_CLK_period/2) -- + 3.0 -- ns sp8s SPI_[0|1]_DI setup time -- 2 -- -- ns sp9s SPI_[0|1]_DI hold time -- 7 -- -- ns SPI Master Configuration (Applicable to 060, 090 Devices) sp6m SPI_[0|1]_DO setup time -- (SPI_x_CLK_period/2) -- - 7.0 -- ns sp7m SPI_[0|1]_DO hold time -- (SPI_x_CLK_period/2) -- - 9.5 -- ns sp8m SPI_[0|1]_DI setup time -- 15 -- -- ns sp9m SPI_[0|1]_DI hold time -- -2.5 -- -- ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 105 TABLE 7-33: SYSTEM CONTROLLER SPI CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V (CONTINUED) SPI Slave Configuration (Applicable to 060, 090 Devices) sp6s SPI_[0|1]_DO setup time -- (SPI_x_CLK_period/2) -- - 16.0 -- ns sp7s SPI_[0|1]_DO hold time -- (SPI_x_CLK_period/2) -- - 3.5 -- ns sp8s SPI_[0|1]_DI setup time -- 3 -- -- ns sp9s SPI_[0|1]_DI hold time -- 2.5 -- -- ns Delay on SC_SPI_SDO after SC_SPI_SS is de-asserted when using SPI slave programming3 -- 265 ns 1. For specific Rise/Fall Times, board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microchip's website: https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/igloo-2-fpgas#Documentation. Use the supported I/O Configurations for the System Controller SPI in Table 7-34. 2. For allowable pclk configurations, see the Serial Peripheral Interface Controller section in the SmartFusion 2 ARM Cortex-M3 and Microcontroller Subsystem User's Guide. 3. SC_SPI_SDO becomes tri-stated after SC_SPI_SS is de-asserted. TABLE 7-34: SUPPORTED I/O CONFIGURATIONS FOR SYSTEM CONTROLLER SPI (FOR MSIO BANK ONLY) Voltage Supply I/O Drive Configuration Units 3.3V 20 mA 2.5V 16 mA 1.8V 12 mA 1.5V 8 mA 1.2V 4 mA 7.11 Mathblock Timing Characteristics The fundamental building block in any digital signal processing algorithm is the multiply-accumulate function. Each IGLOO 2 and SmartFusion 2 SoC mathblock supports 18 x 18 signed multiplication, dot product, and built-in addition, subtraction, and accumulation units to combine multiplication results efficiently. TABLE 7-35: MATHBLOCKS WITH ALL REGISTERS USED--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Mathblock With All Registers Used Speed Grade 1 Parameter Description Min Max tMISU tMIHD tMOCDINSU tMOCDINHD tMSRSTENSU tMSRSTENHD tMARSTREM Input, Control Register Setup time Input, Control Register Hold time CDIN Input Setup time CDIN Input Hold time Synchronous Reset/Enable Setup time Synchronous Reset/Enable Hold time Asynchronous Reset Removal time 0.149 -- 0.08 -- 1.68 -- -0.419 -- 0.185 -- 0.011 -- 0 -- Units ns ns ns ns ns ns ns DS50003487A-page 106 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-35: tMARSTREC tMOCQ tMCLKMP MATHBLOCKS WITH ALL REGISTERS USED--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Asynchronous Reset Recovery time 0.088 -- ns Output Register Clock to Out delay -- 0.232 ns CLK Minimum period 2.245 -- ns TABLE 7-36: MATHBLOCK WITH INPUT BYPASSED AND OUTPUT REGISTERS USED--WORSTCASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Mathblock With Input Bypassed and Output Registers Used Speed Grade 1 Parameter Description Min Max Units tMOSU tMOHD tMOCDINSU tMOCDINHD tMSRSTENSU tMSRSTENHD tMARSTREM tMARSTREC tMOCQ tMCLKMP Output Register Setup time Output Register Hold time CDIN Input Setup time CDIN Input Hold time Synchronous Reset/Enable Setup time Synchronous Reset/Enable Hold time Asynchronous Reset Removal time Asynchronous Reset Recovery time Output Register Clock to Out delay CLK Minimum period 2.294 -- ns -0.444 -- ns 1.68 -- ns -0.419 -- ns 0.115 -- ns 0.011 -- ns 0 -- ns 0.014 -- ns -- 0.232 ns 2.179 -- ns TABLE 7-37: MATHBLOCK WITH INPUT REGISTER USED AND OUTPUT IN BYPASS MODE-- WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Mathblock With Input Register Used and Output in Bypass Mode Speed Grade 1 Parameter Description Min Max Units tMISU tMIHD tMSRSTENSU tMSRSTENHD tMARSTREM tMARSTREC tMICQ tMCDIN2Q Input Register Setup time Input Register Hold time Synchronous Reset/Enable Setup time Synchronous Reset/Enable Hold time Asynchronous Reset Removal time Asynchronous Reset Recovery time Input Register Clock to Output delay CDIN to Output delay 0.149 -- ns 0.08 -- ns 0.185 -- ns -0.012 -- ns -0.005 -- ns 0.088 -- ns -- 2.52 ns -- 1.951 ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 107 TABLE 7-38: MATHBLOCK WITH INPUT AND OUTPUT IN BYPASS MODE--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Mathblock With Input and Output in Bypass Mode Speed Grade 1 Parameter Description Min Max Units tMIQ tMCDIN2Q Input to Output delay CDIN to Output delay -- 2.568 ns -- 1.951 ns 7.12 Flash*Freeze Timing Characteristics TABLE 7-39: FLASH*FREEZE ENTRY AND EXIT TIMES--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Entry/Exit Timing Units Notes Symbols Parameters Conditions FCLK = FCLK = 100 MHz 3 MHz TFF_ENTRY Entry time eNVM and MSS/HPMS PLL = ON 160 320 s -- eNVM and MSS/HPMS PLL = OFF 215 430 s -- TFF_EXIT Exit Time with eNVM and MSS/HPMS PLL = ON during F*F 100 140 s -- respect to MSS PLL Lock eNVM = ON and MSS/HPMS PLL =OFF 136 during F*F and MSS/HPMS PLL turned back 190 s -- on at exit eNVM and MSS PLL = OFF during F*F and 200 285 s -- both are turned back on at exit eNVM = OFF and MSS PLL = ON during F*F 200 285 s -- and eNVM turned back on at exit Exit Time with eNVM and MSS/HPMS PLL = ON during F*F 1.5 1.5 ms 1 respect to Fabric PLL Lock eNVM and MSS PLL = OFF during F*F and both are turned back on at exit 1.5 1.5 ms 1 Exit Time with eNVM and MSS/HPMS PLL = ON during F*F 21 21 s -- respect to Fabric buffer output eNVM and MSS PLL =O FF during F*F and both are turned back on at exit 65 65 s -- Note 1: PLL Lock Delay set to 1024 cycles (default) 7.13 DDR Memory Interface Characteristics TABLE 7-40: Standard DDR3 DDR2 LPDDR DDR MEMORY INTERFACE CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Supported Data Rate Min Typ Max Unit 667 Mbps 667 Mbps 50 -- 400 Mbps DS50003487A-page 108 2023 Microchip Technology Inc. and its subsidiaries 7.14 SFP Transceiver Characteristics IGLOO 2 and SmartFusion 2 SerDes complies with small form-factor pluggable (SFP) requirements as specified in SFP INF-80741. The following provides the electrical characteristics. TABLE 7-41: Pin RD± TD± SFP TRANSCEIVER ELECTRICAL CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Differential Peak-Peak Voltage Direction Min Typ Max Unit Output 1600 -- 2400 mV Input 350 -- 2400 mV Note 1 2 Note 1: Based on default SERDES transmitter settings for PCIe Gen1. Lower amplitudes are available through programming changes to TX_AMP setting. 2: Based on Input Voltage Common-Mode (VICM) = 0V. Requires AC Coupling. 7.15 PCIe Electrical and Timing AC and DC Characteristics PCIe is a high-speed, packet-based, point-to-point, low pin count, serial interconnect bus. The IGLOO 2 and SmartFusion 2 SoC FPGAs has up to four hard high-speed serial interface blocks. Each SerDes block contains a PCIe system block. The PCIe system is connected to the SerDes block. TABLE 7-42: Parameter TRANSMITTER PARAMETERS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Description Min Typ Max VTX-DIFF-PP Differential swing PCIe Gen1 0.8 -- 1.2 VTX-CM-AC-P Output common mode voltage PCIe Gen1 -- -- 20 VTX-RISE-FALL Rise and fall time (20% to 80%) PCIe Gen1 0.125 -- -- ZTX-DIFF-DC LTX-SKEW Output impedance differential 80 -- Lane-to-lane TX skew within a SERDES block -- -- PCIe Gen1 120 500 ps + 2 UI RLTX-DIFF RLTX-CM TX-LOCK-RST Return loss differential mode PCIe Gen1 Return loss common mode PCIe Gen1 Transmit PLL lock time from reset 10 -- -- 6 -- -- -- -- 10 Units V mV UI ps dB dB µs 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 109 TABLE 7-43: Parameter RECEIVER PARAMETERS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Description Min Typ Max Units VRX-DIFF-PP-CC Input levels PCIe Gen1 0.175 1.2 V VRX-CM-DC-P Input common mode range (DC coupled) Note: PCIe standard mandates AC coupling NA NA NA VRX-CM-AC-P Input common mode range (AC coupled) 150 mV VRX-DIFF-PP-CC Differential input sensitivity Gen1 0.175 mV ZRX-DIFF-DC Differential input termination 80 100 120 REXT External calibration resistor 1,188 1,200 1,212 CDR-LOCK-RST CDR relock time from reset 15 µs RLRX-DIFF Return loss differential mode PCIe Gen1 10 dB RLRX-CM RX-CID1 Return loss common mode PCIe Gen1 6 dB CID limit (set by 8B/10B coding, not the receiver PLL) 200 UI VRX-IDLE-DET-DIFF-PP Signal detect limit 65 175 mV 1. AC-coupled, BER = e12. TABLE 7-44: Symbols FREFCLK TRISE TFALL TCYC Mmrefclk SSCref SERDES REFERENCE CLOCK AC SPECIFICATIONS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, WORST-CASE VDD = 1.14V Description Min Typ Max Units Reference Clock Frequency 100 160 MHz Reference Clock Rise Time 0.6 4 V/ns Reference Clock Fall Time 0.6 4 V/ns Reference Clock Duty Cycle 40 60 % Reference Clock Mismatch -300 300 ppm Reference Spread Spectrum Clock 0 5000 ppm TABLE 7-45: HCSL MINIMUM AND MAXIMUM DC INPUT LEVELS (APPLICABLE TO SERDES REFCLK ONLY) Symbols Parameters Min Typ Max Units Recommended DC Operating Conditions VDDI Supply Voltage 2.375 2.5 2.625 V HCSL DC Input Voltage Specification VI DC Input voltage 0 2.625 V HCSL Differential Voltage Specification VICM Input common mode voltage 0.05 2.4 V VIDIFF Input differential voltage 100 1100 mV DS50003487A-page 110 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-46: HCSL MAXIMUM AC SWITCHING SPEEDS (APPLICABLE TO SERDES REFCLK ONLY) Symbols Parameters Conditions Min Typ Max Units HCSL AC Specifications Fmax Maximum Data Rate (for MSIO IO Bank) 350 Mbps HCSL Impedance Specifications Rt Termination Resistance 100 7.16 SmartFusion 2 Specifications 7.16.1 MSS CLOCK FREQUENCY TABLE 7-47: Symbol M3_CLK MAXIMUM FREQUENCY FOR MSS MAIN CLOCK--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Description Speed Grade 1 Units Maximum frequency for the MSS Main Clock (FCLK) 133 MHz 7.16.2 SMARTFUSION 2 INTER-INTEGRATED CIRCUIT (I2C) CHARACTERISTICS This section describes the DC and switching of the IC interface. Unless otherwise noted, all output characteristics given are for a 100 pF load on the pins. For timing parameter definitions, see Figure 7-5 . TABLE 7-48: I2C CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Parameter Definition Conditions Min Typ Max Units Notes VIL Input low voltage See the Single-Ended I/O Standards for more 0.3 -- 0.8 V -- information. I/O standard used for illustration: MSIO bank LVTTL 8 mA low drive. VIH Input high voltage See the Single-Ended I/O Standards for more 2 -- 3.45 V -- information. I/O standard used for illustration: MSIO bank LVTTL 8 mA low drive. VHYS Hysteresis of Schmitt See Table 2-5 for more information. triggered inputs for VDDI > 2 V 0.05 x -- -- V -- VDDI IIL Input current high See the Single-Ended I/O Standards for more -- -- 10 µA -- information. IIH Input current low See the Single-Ended I/O Standards for more -- -- 10 µA -- information. Tir Input rise time Standard Mode -- -- 1000 ns -- Fast Mode -- -- 300 ns -- Tif Input fall time Standard Mode -- -- 300 ns -- Fast Mode -- -- 300 ns -- VOL Maximum output See the Single-Ended I/O Standards for more -- -- 0.4 V -- voltage low (open information. I/O standard used for illustration: drain) at 3 mA sink MSIO bank LVTTL 8 mA low drive. current for VDDI > 2 V Cin Pin capacitance VIN = 0, f = 1.0 MHz -- -- 10 pF -- 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 111 TABLE 7-48: I2C CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V (CONTINUED) Parameter Definition Conditions Min Typ Max Units Notes tOF Output fall time from VIHmin to VILMax, Cload = 400 pF VIHMin to VILMax VIHmin to VILMax, Cload = 100 pF -- 21.04 -- -- 5.556 -- ns 1 ns -- tOR Output rise time from VILMax to VIHmin, Cload = 400pF VILMax to VIHMin VILMax to VIHmin, Cload = 100pF -- 19.887 -- -- 5.218 -- ns 1 ns -- Rpull-up Output buffer -- maximum pull-down resistance -- -- 50 2, 3 Rpull- Output buffer -- down maximum pull-up resistance -- -- 131.25 2, 4 Dmax Maximum data rate Fast mode -- -- 400 Kbps -- Standard mode -- -- 100 Kbps -- tFILT Pulse width of spikes Fast mode which must be suppressed by the input filter -- 50 -- ns -- Note 1: 2: 3: 4: These values are provided for MSIO Bank - LVTTL 8 mA Low Drive at 25°C, typical conditions. For Board Design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microchip's website: https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/igloo-2fpgas#Documentation. These maximum values are provided for information only. Minimum output buffer resistance values depend on VDDIx, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microchip's website: https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/igloo-2-fpgas#Documentation. R(PULL-DOWN-MAX) = (VOLspec)/IOLspec R(PULL-UP-MAX) = (VDDImax VOHspec)/IOHspec TABLE 7-49: I2C SWITCHING CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Speed Grade 1 Parameter Definition Conditions Min Max Units tLOW Low period of I2C_x_SCL -- tHIGH High period of I2C_x_SCL -- tHD;STA START hold time -- tSU;STA START setup time -- tHD;DAT DATA hold time -- tSU;DAT DATA setup time -- tSU;STO STOP setup time -- 1 -- pclk cycles 1 -- pclk cycles 1 -- pclk cycles 1 -- pclk cycles 1 -- pclk cycles 1 -- pclk cycles 1 -- pclk cycles DS50003487A-page 112 2023 Microchip Technology Inc. and its subsidiaries FIGURE 7-5: I2C TIMING PARAMETER DEFINITION SDA SCL TRISE tLOW tSU;STA S tHD;STA tHIGH TFALL tHD;DAT tSU;DAT tSU;STO P 7.16.3 SERIAL PERIPHERAL INTERFACE (SPI) CHARACTERISTICS This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output characteristics given are for a 35 pF load on the pins and all sequential timing characteristics are related to SPI_x_CLK. For timing parameter definitions, see Figure 7-6 . TABLE 7-50: SPI CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V All Devices/Speed Grades Symbol Description Min Typ Max Unit Notes sp1 SPI_[0|1]_CLK minimum period SPI_[0|1]_CLK = PCLK/2 12 -- -- ns -- SPI_[0|1]_CLK = PCLK/4 24.1 -- -- ns -- SPI_[0|1]_CLK = PCLK/8 48.2 -- -- ns -- SPI_[0|1]_CLK = PCLK/16 0.1 -- -- µs -- SPI_[0|1]_CLK = PCLK/32 0.19 -- -- µs -- SPI_[0|1]_CLK = PCLK/64 0.39 -- -- µs -- SPI_[0|1]_CLK = PCLK/128 0.77 -- -- µs -- sp2 SPI_[0|1]_CLK minimum pulse width high SPI_[0|1]_CLK = PCLK/2 6 -- -- ns -- SPI_[0|1]_CLK = PCLK/4 12.05 -- -- ns -- SPI_[0|1]_CLK = PCLK/8 24.1 -- -- ns -- SPI_[0|1]_CLK = PCLK/16 0.05 -- -- µs -- SPI_[0|1]_CLK = PCLK/32 0.095 -- -- µs -- SPI_[0|1]_CLK = PCLK/64 0.195 -- -- µs -- SPI_[0|1]_CLK = PCLK/128 0.385 -- -- µs -- Note 1: 2: For specific Rise/Fall Times board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microchip's website: https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/igloo-2-fpgas#Documentation. For allowable pclk configurations, see the Serial Peripheral Interface Controller section in the SmartFusion 2 Microcontroller Subsystem User Guide. 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 113 TABLE 7-50: SPI CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V (CONTINUED) All Devices/Speed Grades Symbol Description Min Typ Max Unit Notes sp3 SPI_[0|1]_CLK minimum pulse width low SPI_[0|1]_CLK = PCLK/2 6 -- -- ns -- SPI_[0|1]_CLK = PCLK/4 12.05 -- -- ns -- SPI_[0|1]_CLK = PCLK/8 24.1 -- -- ns -- SPI_[0|1]_CLK = PCLK/16 0.05 -- -- µs -- SPI_[0|1]_CLK = PCLK/32 0.095 -- -- µs -- SPI_[0|1]_CLK = PCLK/64 0.195 -- -- µs -- SPI_[0|1]_CLK = PCLK/128 0.385 -- -- µs -- sp4 SPI_[0|1]_CLK, SPI_[0|1]_DO, -- SPI_[0|1]_SS rise time (10%- 90%) 2.77 -- ns 1 sp5 SPI_[0|1]_CLK, SPI_[0|1]_DO, -- SPI_[0|1]_SS fall time (10%-90%) 2.906 -- ns 1 SPI Master Configuration sp6m SPI_[0|1]_DO setup time (SPI_x_CLK_period/2) 3.0 -- -- ns 2 sp7m SPI_[0|1]_DO hold time (SPI_x_CLK_period/2) 2.5 -- -- ns 2 sp8m SPI_[0|1]_DI setup time 8 -- -- ns 2 sp9m SPI_[0|1]_DI hold time 2.5 -- -- ns 2 SPI Slave Configuration sp6s SPI_[0|1]_DO setup time (SPI_x_CLK_period/2) 12.0 -- -- ns 2 sp7s SPI_[0|1]_DO hold time (SPI_x_CLK_period/2) + 3.0 -- -- ns 2 sp8s SPI_[0|1]_DI setup time 2 -- -- ns 2 sp9s SPI_[0|1]_DI hold time 3 -- -- ns 2 Note 1: 2: For specific Rise/Fall Times board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microchip's website: https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/igloo-2-fpgas#Documentation. For allowable pclk configurations, see the Serial Peripheral Interface Controller section in the SmartFusion 2 Microcontroller Subsystem User Guide. DS50003487A-page 114 2023 Microchip Technology Inc. and its subsidiaries FIGURE 7-6: SPI_0_CLK SPO = 0 SPI TIMING FOR A SINGLE FRAME TRANSFER IN MOTOROLA MODE (SPH = 1) SP1 SP2 SP3 50% 50% 50% SP4 SP5 90% 10% 10% SPI_0_CLK SPO = 1 90% SPI_0_SS 1 0% SP5 SP6 SP7 SPI_0_DO SPI_0_DI 5 0% MSB 5 0% SP8 SP9 50% MSB 50% 9 0% 10% SP5 10% 90% SP4 90% 10% SP4 7.17 SRAM PUF This section describes the SRAM PUF in worst-case automotive Grade 2 conditions, TJ = 125 °C, VDD = 1.14V. For more about on-static random-access memory (SRAM) physical unclonable functions (PUF) services, see Using SRAM PUF System Service in SmartFusion 2 Application Note. TABLE 7-51: SRAM PUF PUF OFF PUFF ON Service Type Maximum Type Maximum Units Create Activation Code 709.1 770.8 796.0 865.3 ms Delete Activation Code 1329.3 1444.9 1303.0 1416.3 ms Create Intrinsic KeyCode 656.6 713.7 643.6 699.5 ms Create Extrinsic KeyCode 656.6 713.7 643.6 699.5 ms Get Number of Keys 1.3 1.5 1.3 1.4 ms Export (KC0, KC1) 998.0 1084.8 978.2 1063.3 ms Export 2 KeyCodes 2020.2 2195.9 1980.2 2152.4 ms Export 4 KeyCodes 3065.7 3332.2 3005.0 3266.3 ms Export 8 KeyCodes 5101.0 5544.6 5000.0 5434.8 ms Export 16 KeyCodes 9212.1 10013.2 9029.7 9814.9 ms Import (KC0, KC1) 39.7 43.1 38.9 42.3 ms Import 2 KeyCodes 50.1 54.5 49.1 53.4 ms Import 4 KeyCodes 60.6 65.9 59.4 64.6 ms Import 8 KeyCodes 80.9 87.9 79.3 86.2 ms Import 16 KeyCodes 123.8 134.6 121.4 131.9 ms Delete KeyCode 552.5 600.6 541.6 588.7 ms 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 115 TABLE 7-51: SRAM PUF (CONTINUED) PUF OFF Service Type Maximum Fetch Key 31.4 34.1 Fetch ECC Key 20.0 21.7 Get Seed 2.0 2.2 PUFF ON Type 11.5 1.9 0.9 Maximum 12.5 2.1 1.0 Units ms ms ms 7.18 Non-Deterministic Random Bit Generator Characteristics This section describes the NRBG characteristics in worst-case automotive Grade 2 conditions, VDD = 1.14V. For more information about NRBG, see Using NRBG Services in SmartFusion 2 aTnJ d= 125 °C, IGLOO 2 Devices Application Note. TABLE 7-52: NON-DETERMINISTIC RANDOM BIT GENERATOR CHARACTERISTICS Conditions Service Prediction Resistance Additional Input Timing Units Notes Instantiate OFF X Generate OFF 0 (after Instantiate) OFF 64 OFF 128 85 ms 4.5 ms + (7 us/byte x No. of Bytes) -- 1 6.0 ms + (7 us/byte x No. of Bytes) -- 7.0 ms + (7 us/byte x No. of Bytes) -- ON X 47 ms 1 Generate OFF 0 (subsequent) OFF 64 0.5 ms + (7 us/byte x No. of Bytes) -- 2.0 ms + (7 us/byte x No. of Bytes) -- OFF 128 3.0 ms + (7 us/byte x No. of Bytes) -- -- ON X 43 ms -- Reseed -- 40 ms -- Uninstantiate -- 0.16 ms -- Reset -- 0.10 ms -- Self Test First time after power up 20 ms -- Subsequent 6 ms -- 1. If PUF_OFF, generate would incur additional PUF Delay time for consecutive service calls. 7.19 Cryptographic Block Characteristics This section describes the Cryptographic block characteristics in worst-case automotive Grade 2 conditions, TUJsi=ng12A5E°SC,SVyDstDem= 1.14V. For more information about Cryptographic Services in SmartFusion 2 and IGLOO 2 Devices block and associated Application Note and services, see Using SHA-256 System Services in SmartFusion 2 and IGLOO 2 Devices Application Note. TABLE 7-53: CRYPTOGRAPHIC BLOCK CHARACTERISTICS Service Conditions Timing Units Any Service First certificate check penalty at boot 11.5 AES128/256 (Encoding / Decoding)1 Up to 100 blocks 200 ms kbps 100 blocks up to 64k blocks 650 kbps DS50003487A-page 116 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-53: CRYPTOGRAPHIC BLOCK CHARACTERISTICS Service Conditions SHA256 512 bits 1024 bits 2048 bits 24 kbits HMAC 512 bytes 1024 bytes 2048 bytes 24 kbytes KeyTree -- Challenge-Response PUF = OFF PUF = ON ECC Point Multiplication -- ECC Point Addition -- 1. Using Cypher Block Chaining (CBC) mode. Timing 530 770 940 1130 810 880 920 970 1.6 23 6.6 590 8 Units kbps kbps kbps kbps kbps kbps kbps kbps ms ms ms ms ms 7.20 CAN Controller Characteristics TABLE 7-54: Parameter CAN CONTROLLER CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Description Min Typ Max Units Notes FCANREFCLK Internally Sourced CAN Reference Clock Frequency -- -- 128 MHz 1 BAUDCAN CAN Performance Baud Rate 0.05 -- 1 Mbps -- Note 1: PCLK to CAN controller must be a multiple of 8 MHz. 7.21 USB Characteristics TABLE 7-55: USB CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Parameter Description Min Typ Max Units FUSBREFCLK Internally Sourced USB Reference Clock Frequency -- -- 133 MHz TUSBCLK USB Clock Period -- -- 16.66 ns TUSBPD Clock to USB Data Propagation Delay -- -- 9.0 ns TUSBSU Setup Time for USB Data -- -- 6.0 ns TUSBHD Hold Time for USB Data 0 -- -- ns 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 117 7.22 SerDes Protocol Compliance TABLE 7-56: SERDES PROTOCOL COMPLIANCE Protocol Maximum Data Rate (Gbps) PCIe Gen 1 2.5 Gbps XAUI 3.125 Gbps Generic EPCS 2.5 Gbps Speed Grade -1 Yes Yes Yes 7.23 MMUART Characteristics This section describes the characteristics of MMUART in worst-Case automotive grade 2 conditions, TJ = 125°C, VDD = 1.14V. TABLE 7-57: MMUART CHARACTERISTICS Parameter Descriptions Speed Grade - 1 Units FMMUART_REF_CLK Internally Sourced MMUART Reference Clock 133 Frequency MHz BAUDMMUARTTx Maximum Transmit Baud Rate 8.3125 Mbps BAUDMMUARTRx Maximum Receive Baud Rate 8.3125 Mbps 7.24 IGLOO 2 Specifications 7.24.1 HPMS CLOCK FREQUENCY TABLE 7-58: Symbol HPMS_CLK MAXIMUM FREQUENCY FOR HPMS MAIN CLOCK--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V Description Speed Grade 1 Units Maximum Frequency for the HPMS Main Clock (FCLK) 133 MHz 7.24.2 IGLOO 2 SERIAL PERIPHERAL INTERFACE (SPI) CHARACTERISTICS This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output characteristics given are for a 35 pF load on the pins and all sequential timing characteristics are related to SPI_0_CLK. For timing parameter definitions, refer to Figure 7-7 . TABLE 7-59: SPI CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V All Devices/Speed Grades Symbol Description Min Typ Max Unit Notes sp1 SPI_[0|1]_CLK minimum period SPI_[0|1]_CLK = PCLK/2 12 -- -- ns -- SPI_[0|1]_CLK = PCLK/4 24.1 -- -- ns -- SPI_[0|1]_CLK = PCLK/8 48.2 -- -- ns -- SPI_[0|1]_CLK = PCLK/16 0.1 -- -- µs -- SPI_[0|1]_CLK = PCLK/32 0.19 -- -- µs -- SPI_[0|1]_CLK = PCLK/64 0.39 -- -- µs -- SPI_[0|1]_CLK = PCLK/128 0.77 -- -- µs -- DS50003487A-page 118 2023 Microchip Technology Inc. and its subsidiaries TABLE 7-59: SPI CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V (CONTINUED) All Devices/Speed Grades Symbol Description Min Typ Max Unit Notes sp2 SPI_[0|1]_CLK minimum pulse width high SPI_[0|1]_CLK = PCLK/2 6 -- -- ns -- SPI_[0|1]_CLK = PCLK/4 12.05 -- -- ns -- SPI_[0|1]_CLK = PCLK/8 24.1 -- -- ns -- SPI_[0|1]_CLK = PCLK/16 0.05 -- -- µs -- SPI_[0|1]_CLK = PCLK/32 0.095 -- -- µs -- SPI_[0|1]_CLK = PCLK/64 0.195 -- -- µs -- SPI_[0|1]_CLK = PCLK/128 0.385 -- -- µs -- sp3 SPI_[0|1]_CLK minimum pulse width low SPI_[0|1]_CLK = PCLK/2 6 -- -- ns -- SPI_[0|1]_CLK = PCLK/4 12.05 -- -- ns -- SPI_[0|1]_CLK = PCLK/8 24.1 -- -- ns -- SPI_[0|1]_CLK = PCLK/16 0.05 -- -- µs -- SPI_[0|1]_CLK = PCLK/32 0.095 -- -- µs -- SPI_[0|1]_CLK = PCLK/64 0.195 -- -- µs -- SPI_[0|1]_CLK = PCLK/128 0.385 -- -- µs -- sp4 SPI_[0|1]_CLK, SPI_[0|1]_DO, -- SPI_[0|1]_SS rise time (10%- 90%) 2.77 -- ns 1 sp5 SPI_[0|1]_CLK, SPI_[0|1]_DO, -- SPI_[0|1]_SS fall time (10%- 90%) SPI Master Configuration sp6m SPI_[0|1]_DO setup time sp7m SPI_[0|1]_DO hold time sp8m SPI_[0|1]_DI setup time sp9m SPI_[0|1]_DI hold time SPI Slave Configuration sp6s SPI_[0|1]_DO setup time sp7s SPI_[0|1]_DO hold time (SPI_x_CLK_period/2) 3.0 (SPI_x_CLK_period/2) 2.5 8 2.5 (SPI_x_CLK_period/2) 12.0 (SPI_x_CLK_period/2) + 3.0 2.906 -- ns 1 -- -- ns 2 -- -- ns 2 -- -- ns 2 -- -- ns 2 -- -- ns 2 -- -- ns 2 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 119 TABLE 7-59: SPI CHARACTERISTICS--WORST-CASE AUTOMOTIVE GRADE 2 CONDITIONS: TJ = 125°C, VDD = 1.14V (CONTINUED) All Devices/Speed Grades Symbol Description Min Typ Max Unit Notes sp8s SPI_[0|1]_DI setup time 2 -- -- ns 2 sp9s SPI_[0|1]_DI hold time 3 -- -- ns 2 Note 1: 2: For specific Rise/Fall Times board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microchip website: https://www.microchip.com/en-us/products/fpgas-and-plds/system-on-chip-fpgas/smartfusion-2-fpgas#ibis. For allowable pclk configurations, see the Serial Peripheral Interface Controller section in the UG0331: SmartFusion 2 Microcontroller Subsystem User Guide. FIGURE 7-7: SPI TIMING FOR A SINGLE FRAME TRANSFER IN MOTOROLA MODE (SPH = 1) SPI_0_CLK SPO = 0 SP1 SP2 SP3 50% 50% 50% SP4 SP5 90% 10% 10% SPI_0_CLK SPO = 1 90% SPI_0_SS 1 0% SP5 SP6 SP7 SPI_0_DO SPI_0_DI 5 0% MSB 5 0% SP8 SP9 50% MSB 50% 9 0% 10% SP5 10% 90% SP4 90% 10% SP4 DS50003487A-page 120 2023 Microchip Technology Inc. and its subsidiaries APPENDIX A: LIST OF CHANGES The following table shows important changes made in this document for each revision. A.1 Revision A--March 2023 The following is a list changes made in this revision. · Migrated this data sheet into Microchip's template. · Updated the hyperlinks as in the Microchip's website. · Updated the values in Table 7-25 and Table 7-26. · Updated the value of "Access Time with Feed-Through Write Timing" in Table 7-5, Table 7-6, Table 7-7, Table 7-8, and Table 7-9. For more information about this change, see the SmartFusion 2 IGLOO 2 FPGA LSRAM WriteFeedthrough Timing document. A.2 Revision 4--September 2018 The following information was updated in revision 4.0 of this document. · Information about VDDIx in recommended operational conditions table was updated. See Table 1-2. · Information about VOH and VOL were updated. See Table 5-12. · Information about DEVRSTN ramp time was updated. See Table 7-30. · Information about RX-CID was updated. See Table 7-43. The following information was added in revision 4.0 of this document. · A note about VID was added to LVDS differential voltage specification. See Table 5-68. A.3 Revision 3--May 2018 The following information was updated in revision 3.0 of this document. · 060 device status is changed to production. See Table 1. · Currents during power cycle, verify cycle, and inrush current at power-up was updated. See Table 2-4, Table 2-5, and Table 2-6. · Junction temperature. See Table 1-1. · High temperature data retention. See Table 1-6 and Figure 1-1. · Input capacitance and leakage current. See Table 5-3. · DC input voltage. See Table 5-86. · Speed grade -1. See Table 5-93, Table 5-94, Table 5-95, and Table 5-96. · Acquisition time in CCC/PLL specification. See Table 7-23. · SPI characteristics. See Table 7-33. · F*F exit and entry timings. See Table 7-39. · 060 device was added to VPP. See Table 1-2. · Digest temperature and digest cycle. See Table 1-3. · Quiescent Supply Current characteristics of 060 device was added. See Table 2-2 and Table 2-3. · Programming timing in typical and worse-case conditions. See Table 7-25 and Table 7-26. · 060 device was added in JTAG. See Table 7-27. · Power-up. See Section 7.7, Power-up to Functional Times. · DEVRST_N. See Section 7.9, DEVRST_N to Functional Times. · SRAM PUF. See Table 7-51. · Non-deterministic Random Bit Generator (NRBG) Characteristics. See Table 7-52. · Cryptographic block characteristics. See Table 7-53. · SerDes protocol compliance. See Table 7-56. · MMUART. See Table 7-57. 2023 Microchip Technology Inc. and its subsidiaries Microchip Technology Inc. DS50003487A-page 121 A.4 Revision 2--September 2015 The following was a list changes made in this revision. · Updated Table 2-2 for typical process values. · Updated Table 2-3: for worst-case process values. · Updated Table 7-24 for FGG. A.5 Revision 1--June 2015 Initial release. DS50003487A-page 122 2023 Microchip Technology Inc. and its subsidiaries THE MICROCHIP WEBSITE Microchip provides online support via our WWW site at www.microchip.com. This website is used as a means to make files and information easily available to customers. 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DS50003487A-page 123 Note the following details of the code protection feature on Microchip products: · Microchip products meet the specifications contained in their particular Microchip Data Sheet. · Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions. · Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act. · Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable" Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. 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