Gowin SDI Encoder IP User Guide

1 About This Guide

1.1 Purpose

The purpose of Gowin SDI Encoder IP is to help you learn the features and usage of Gowin SDI Encoder IP by providing the descriptions of features, functions, ports, timing, GUI and reference design, etc. The software screenshots and the supported products listed in this manual are based on Gowin Software 1.9.11 (64-bit). As the software is subject to change without notice, some information may not remain relevant and may need to be adjusted according to the software that is in use.

1.2 Related Documents

The latest user guides are available on the GOWINSEMI website. You can find the related documents at www.gowinsemi.com:

• DS981, GW5AT series of FPGA Products Data Sheet
• DS1239, GW5AST series of FPGA Products Data Sheet
• SUG100, Gowin Software User Guide

1.3 Terminology and Abbreviations

Table 1-1 shows the abbreviations and terminology used in this manual.

1.4 Support and Feedback

Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact Gowin Semiconductor directly using the information provided below.

Website: www.gowinsemi.com

E-mail: support@gowinsemi.com

2 Overview

2.1 Overview

The Serial Digital Interface (SDI) is a member of the digital video interface family and is used for transmitting digital video signals. Gowin SDI Encoder IP can be operated under HD or 3G rate standards defined by the Society of Motion Picture and Television Engineers (SMPTE), converting video signals into SDI signals.

Table 2-1 Gowin SDI Encoder IP

Note: For the devices supported, you can click here to get the information.

2.2 Features

• Operates with 1 lane
• Supports link rates of 1.485/2.97 Gbps per lane
• Supports HD-SDI and 3G-SDI

2.3 Resource Utilization

Gowin SDI Encoder IP can be implemented by Verilog. Its performance and resource utilization may vary when the design is employed in different devices, or at different densities, speeds, or grades. Taking Gowin GW5AST series of FPGA as an instance, the resource utilization of Gowin SDI Encoder IP is as shown in Table 2-2.

Table 2-2 Gowin SDI Encoder IP Resource Utilization

3 Functional Description

3.1 System Block Diagram

Gowin SDI Encoder IP can convert video signals into SDI signals. The SDI signal is then connected into the SDI PHY IP. The block diagram of Gowin SDI Encoder IP is as shown in Figure 3-1.

Figure 3-1 Gowin SDI Encoder IP Block Diagram: Textual representation of the block diagram. It shows a 'Video_Source' input connected to the 'SDI_Encoder_IP' via signals Vs, Hs, De, and Data. The 'SDI_Encoder_IP' outputs 'SDI_PHY_Data' to the 'SDI_PHY_IP'. The 'SDI_PHY_IP' then connects to a 'Single-ended_To_Differential_Circuit' which outputs 'SDI_Data' to a 'BNC_Interface'. Input signals for the SDI_PHY_IP include SerDes_Data_P and SerDes_Data_N.

3.2 Function Modules

Figure 3-2 Gowin SDI Encoder IP Block Diagram: Textual representation of the block diagram showing 'Video_Source' inputs (Vs, Hs, De, Data) feeding into 'SDI_Encoder_IP', which then outputs to 'SDI_PHY_Data' connected to 'SDI_PHY_IP'.

As shown in the diagram above, Gowin SDI Encoder IP can convert video data into SDI data.

3.3 Supported Format

Table 3-1 shows the formats supported by Gowin SDI Encoder IP.

Table 3-1 Formats Supported by Gowin SDI Encoder IP

3.4 Port List

The IO port of Gowin SDI Encoder IP is shown in Figure 3-3.

Figure 3-3 Gowin SDI Encoder IP Port Diagram: Textual representation of the port diagram. It lists input ports such as I_rst_n, I_rate[2:0], I_hres[15:0], I_vres[15:0], I_ver_fre[20], I_interlace, I_color, I_mfactor, I_pixbit, I_pixstruc[1:0], I_clk, I_fld, I_vs, I_hs, I_de, I_data[19:0]. It also shows an output port O_data[79:0].

The IO ports vary slightly depending on the parameters.

The details of IO port of Gowin SDI Encoder IP are shown in Table 3-2.

Table 3-2 I/O List of Gowin SDI Encoder IP

3.5 Timing Description

The input interface timing diagram of Gowin SDI Encoder IP is as shown in Figure 3-4. For standard video, simply input the signals, and Gowin SDI Encoder IP will encode them. The encoded data is then output to the SDI PHY IP.

Figure 3-4 Timing Diagram of Video Input Interface: Textual representation of the Video Input Interface Timing Diagram. It shows the timing relationships between I_clk, I_fld, I_vs, I_hs, I_de, and I_data signals over a series of clock cycles (1 to 26).

4 Interface Configuration

You can use IP core generator tool in Gowin Software to call and configure Gowin SDI Encoder IP.

1. Open IP Core Generator

After creating the project, click the "Tools" tab in the upper left, click "IP Core Generator" from the drop-down list to open Gowin IP Core Generator, as shown in Figure 4-1.

Figure 4-1 Open IP Core Generator: Screenshot of the Gowin FPGA Designer showing the 'Tools' menu with 'IP Core Generator' highlighted, indicating how to access the IP core generation tool.

2. Select SDI Encoder IP

Double Click "Multimedia” and select SDI Encoder to open SDI Encoder IP configuration interface, as shown in Figure 4-2.

Figure 4-2 Select SDI Encoder IP: Screenshot of the Gowin IP Core Generator interface, showing the 'Multimedia' category expanded to reveal 'SDI Encoder' which can be selected.

3. Gowin SDI Encoder IP Configuration Interface

First configure “General” tab in the SDI Encoder IP interface as shown in Figure 4-3.

Figure 4-3 Gowin SDI Encoder IP Configuration Interface: Screenshot of the SDI Encoder IP Customization dialog. It shows the 'General' tab with fields for Device, Device Version, Part Number, Language (Verilog/VHDL), File Name, Module Name, and Create In path. Input ports are listed on the left.

• Device, Device Version, Part Number: Part number settings, determined by the current project, and the user can not set it.
• Language: Supports Verilog and VHDL; choose the language as requirements, and the default is Verilog.
• File Name, Module Name, Create In: Displays SDI file name, module name and the generated file path.

4. Click "OK"

Click "OK" directly to generate the IP.

5 Reference Design

This chapter is intended to introduce the usage and structure of the reference design of Gowin SDI Encoder IP. Please see the SDI PHY IP Reference Design for details at Gowinsemi website. This reference design takes DK_START_GW5AT-LV60PG484A_V1.1 development board as an example. For more information about DK_START_GW5AT-LV60PG484A_V1.1 development board, please refer to Gowinsemi website. The block diagram of reference design is shown in Figure 5-1.

Figure 5-1 Block Diagram of Reference Design: Textual representation of the Reference Design Block Diagram. It shows a flow starting from 'Pattern generation module' and 'RGB to YC', feeding into 'SDI Encoder IP'. This connects to 'SDI PHY IP', which then goes through 'SDI physical interface' and 'Single-ended to differential IC' to a 'SDI to HDMI device', finally leading to a 'Display'.

6 File Delivery

The file delivery for Gowin SDI Encoder IP includes the documentation, the design source code, and the reference design.

6.1 Documentation

Table 6-1 Document List

6.2 Design Source Code (Encryption)

The encrypted code folder contains encrypted RTL code for Gowin SDI Encoder IP. This code is intended for use with GUI to generate the IP core as needed.

Table 6-2 File List of Gowin SDI Encoder IP

6.3 Reference Design

The RefDesign folder contains the netlist files, user reference designs, constraints files, top-level files, and project files for Gowin SDI PHY IP, Gowin SDI Encoder IP, and Gowin SDI Decoder IP.

Table 6-3 Gowin SDI Encoder IP RefDesign Folder Content List