TPS3703 High Accuracy Overvoltage and Undervoltage Reset IC With Time Delay and Manual Reset

1 Features

• Input voltage range: 1.7 V to 5.5 V
• Undervoltage lockout (UVLO): 1.7 V
• Low quiescent current: 7 µA (Max)
• High threshold accuracy: ±0.25% (typical), ±0.7% (–40°C to +125°C)
• Fixed window threshold levels (50-mV steps from 500 mV to 1.3 V, and specific values like 1.5 V, 1.8 V, 2.5 V, 2.8 V, 2.9 V, 3.3 V, 5 V)
• Available in UV threshold only
• Window tolerance available from ±3% to ±7%
• User adjustable voltage threshold levels
• Internal glitch immunity and hysteresis
• Fixed time delay options: 50 µs, 1 ms, 5 ms, 10 ms, 20 ms, 100 ms, 200 ms
• Programmable time delay option with a single external capacitor
• Open-drain active low UV and OV monitor
• RESET voltage latching output mode

2 Applications

• Motor drives
• Factory automation and control
• Home theater and entertainment
• Grid infrastructure
• Data center and enterprise computing

3 Description

The TPS3703 is an integrated overvoltage (OV) and undervoltage (UV) monitor or reset IC in a compact 6-pin DSE package. It is designed for systems operating on low-voltage supply rails with narrow supply tolerances. The device offers high accuracy, internal glitch immunity, and noise filters to prevent false resets. It eliminates the need for external resistors for threshold setting, optimizing accuracy, cost, and solution size. The Capacitor Time (CT) pin allows for selection of fixed or programmable reset time delays. A separate SENSE input and VDD pin provide redundancy for high-reliability systems. With a low typical quiescent current of 4.5 µA, the TPS3703 is suitable for industrial applications requiring precise undervoltage and overvoltage monitoring.

Device Information

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Diagrams and Figures

Integrated Overvoltage and Undervoltage Detection: This block diagram illustrates the TPS3703 IC with its pins: SENSE (1), VDD (2), CT (3), RESET (4), GND (5), and MR (6). It shows connections to a VCORE/Processor, with optional external components like a 10kΩ resistor. The diagram depicts the core functionality of monitoring voltage levels.

Typical Overvoltage Accuracy Distribution: This histogram shows the distribution of measured overvoltage accuracy percentages. The x-axis represents the accuracy in percentage (from -0.4% to +0.4%), and the y-axis represents the frequency (count) of occurrences. The data indicates a concentration of accuracy values around 0%.

Figure 5-1. TPS3703 Device Nomenclature: This diagram breaks down the TPS3703 part number into its constituent codes: 'X' for Time Delay Option (e.g., A, B, C, D), 'X' for Tolerance Option (e.g., 3 for 3%, 4 for 4%), 'XXX' for Nominal Threshold Option (e.g., 050 for 0.50V, 500 for 5.00V), and 'XXX' for Package (e.g., DSE for WSON 6-pin).

Figure 6-1. DSE Package 6-Pin WSON Top View: This diagram shows the physical pinout of the 6-pin WSON package, labeling pins 1 through 6: SENSE, VDD, CT, RESET, GND, and MR.

Figure 7-1. Voltage Threshold and Hysteresis Accuracy: This graph illustrates the voltage thresholds (VIT+(OV) and VIT-(UV)) and their associated hysteresis bands (VHYS). It shows how accuracy varies with temperature (25°C and -40°C to 125°C) and tolerance percentages (e.g., ±0.25%, ±0.7%). The graph visually represents the ±3% to ±7% tolerance ranges.

Figure 7-2. SENSE Timing Diagram: This timing diagram depicts the relationship between VDD, VSENSE, and RESET signals over time. It shows various voltage levels like VDD(MIN), UVLO, VPOR, VIT+(OV), VIT-(UV), and their hysteresis bands. It illustrates how the RESET output (low or undefined) responds to VSENSE crossing these thresholds, including delays like tSD, tD, and tPD.

7 Specifications

7.1 Absolute Maximum Ratings

(1) Stresses beyond values listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.

7.2 ESD Ratings

(1) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

(1) CT pin connected to VDD pin requires a pullup resistor; 10 kΩ is recommended.

(2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.

(3) The maximum rating is VDD or 5.5 V, whichever is smaller.

7.4 Thermal Information

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

At 1.7 V ≤ VDD ≤ 5.5 V, CT = MR = Open, RESET Voltage (VRESET) = 10 kΩ to VDD, RESET load = 10 pF, and over the operating free-air temperature range of –40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical conditions at VDD = 3.3 V.

(1) Hysteresis is with respect of the tripoint (VIT-(UV), VIT+(OV)).

(2) VPOR is the minimum VDD voltage level for a controlled output state.

(3) RESET pin is driven low when VDD falls below UVLO.

(4) VCT voltage refers to the comparator threshold voltage that measures the voltage level of the external capacitor at CT pin.

7.6 Timing Requirements

At 1.7 V ≤ VDD ≤ 5.5 V, CT = MR = Open, RESET Voltage (VRESET) = 10 kΩ to VDD, RESET load = 10 pF, and over the operating free-air temperature range of –40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical conditions at VDD = 3.3 V.

(1) 5% Overdrive from threshold. Overdrive % = [VSENSE - VIT] / VIT; Where VIT stands for VIT-(UV) or VIT+(OV).

(2) tPD measured from threshold trip point (VIT-(UV) or VIT+(OV)) to RESET VOL voltage.

(3) Output transitions from VOL to 90% for rise times and 90% to VOL for fall times.

(4) During the power-on sequence, VDD must be at or above VDD(MIN) for at least tSD + tD before the output is in the correct state.

Timing Diagrams

Figure 7-1. Voltage Threshold and Hysteresis Accuracy: This graph displays the voltage thresholds (VIT+(OV) and VIT-(UV)) and their associated hysteresis bands (VHYS). It illustrates how accuracy percentages (e.g., ±0.25%, ±0.7%) are affected by temperature (25°C and -40°C to 125°C) and tolerance settings (e.g., ±3% to ±7%). The graph visually represents the operational window and margin for voltage monitoring.

Figure 7-2. SENSE Timing Diagram: This diagram shows the temporal relationship between VDD, VSENSE, and RESET signals. It defines key voltage levels such as VDD(MIN), UVLO, VPOR, VIT+(OV), VIT-(UV), and their hysteresis bands. The diagram illustrates how the RESET output transitions between high impedance and low states based on VSENSE crossing these thresholds, incorporating specified delays like tSD, tD, and tPD.

7.8 Typical Characteristics

The following graphs illustrate typical performance characteristics of the TPS3703 under various conditions.

Figure 7-3. Undervoltage Accuracy vs Temperature: Shows undervoltage accuracy (%) versus temperature (°C) for different VDD supply voltages (0.8 V to 5.0 V). Accuracy generally remains within ±0.2% across the temperature range.

Figure 7-4. Overvoltage Accuracy vs Temperature: Displays overvoltage accuracy (%) versus temperature (°C) for different VDD supply voltages (0.8 V to 5.0 V). Similar to undervoltage accuracy, it stays within ±0.2% across temperatures.

Figure 7-5. Undervoltage Accuracy Distribution: A histogram showing the frequency distribution of undervoltage accuracy percentages for a sample size of 100 units. The data clusters tightly around 0% accuracy.

Figure 7-6. Overvoltage Accuracy Distribution: A histogram illustrating the frequency distribution of overvoltage accuracy percentages for a sample size of 100 units. The distribution is centered closely around 0% accuracy.

Figure 7-7. Undervoltage Hysteresis Voltage Accuracy vs Temperature: Plots undervoltage hysteresis voltage accuracy (%) versus temperature (°C) for various VDD levels. The hysteresis accuracy remains relatively stable around 0.55% across temperatures.

Figure 7-8. Overvoltage Hysteresis Voltage Accuracy vs Temperature: Shows overvoltage hysteresis voltage accuracy (%) versus temperature (°C) for different VDD levels. The hysteresis accuracy is consistently around 0.55% across the temperature spectrum.

Figure 7-9. Supply Current vs Temperature (Output = High): Illustrates the supply current (µA) versus temperature (°C) when the RESET pin is high, for VDD = 1.7 V, 3.3 V, and 5.5 V. Current increases slightly with temperature.

Figure 7-10. Supply Current vs Temperature (Output = Low): Shows the supply current (µA) versus temperature (°C) when the RESET pin is low, for VDD = 1.7 V, 3.3 V, and 5.5 V. The current is higher when the output is low compared to when it is high.

Figure 7-11. SENSE Glitch Immunity (VIT-) vs Overdrive: Depicts SENSE glitch immunity (µs) versus overdrive (%) for VDD = 1.7 V at different temperatures (-40°C, 25°C, 125°C). Immunity decreases as overdrive increases.

Figure 7-12. SENSE Glitch Immunity (VIT+) vs Overdrive: Shows SENSE glitch immunity (µs) versus overdrive (%) for VDD = 1.7 V at different temperatures. Immunity decreases with increasing overdrive.

Figure 7-13. SENSE Glitch Immunity (VIT-) vs Overdrive: Illustrates SENSE glitch immunity (µs) versus overdrive (%) for VDD = 5.5 V at different temperatures. Immunity decreases as overdrive increases.

Figure 7-14. SENSE Glitch Immunity (VIT+) vs Overdrive: Displays SENSE glitch immunity (µs) versus overdrive (%) for VDD = 5.5 V at different temperatures. Immunity decreases with increasing overdrive.

Figure 7-15. Low-Level Output Voltage vs RESET current: Plots the low-level output voltage (VOL) versus RESET current (IRESET) for VDD = 1.7 V at various temperatures. VOL remains low and relatively constant as current increases.

Figure 7-16. Low-Level Output Voltage vs RESET current: Shows the low-level output voltage (VOL) versus RESET current (IRESET) for VDD = 5.5 V at various temperatures. VOL stays consistently low across different current levels.

Figure 7-17. SET Threshold vs Temperature: Illustrates the MR threshold voltage (VMR_H and VMR_L) versus temperature (°C) for VDD = 1.7 V. The thresholds show a slight decrease with increasing temperature.

Figure 7-18. SET Threshold vs Temperature: Displays the MR threshold voltage (VMR_H and VMR_L) versus temperature (°C) for VDD = 5.5 V. Thresholds decrease slightly with temperature.

Figure 7-19. CT Current vs CT value: Shows the CT pin charge current (ICT) versus CT pin voltage (VCT) for VDD = 1.7 V and 5.5 V. The current is relatively constant across the VCT range.

Figure 7-20. RESET Timeout vs CT Capacitor: Plots the reset timeout (tD) in seconds versus capacitor value (nF) for different temperatures (25°C, -40°C, 125°C). The timeout increases logarithmically with capacitor value.

Figure 7-21. Timeout vs CT Capacitor (0.1 to 10 nF): Shows the reset timeout (tD) in milliseconds versus capacitor value (nF) for different temperatures. The timeout increases with capacitor size.

Figure 7-22. Detect Propagation Delay vs Temperature: Illustrates the detect propagation delay (tPD) in microseconds versus temperature (°C) for VDD = 1.7 V, 3.3 V, and 5.5 V. The delay is relatively constant across temperatures.

8 Detailed Description

8.1 Overview

The TPS3703 family integrates two voltage comparators and a precision voltage reference for accurate overvoltage and undervoltage detection. It features highly accurate window threshold voltages (±0.7% over temperature) and multiple voltage threshold variants. Internal resistors simplify design and reduce component count. The device offers factory-programmed and user-programmable reset delay timing options via the CT pin. A Manual Reset (MR) input allows for external reset initiation. The TPS3703 asserts active-low output signals when the monitored voltage falls outside the safe window.

8.2 Functional Block Diagram

The functional block diagram shows two main versions: 'Undervoltage Only Version' and 'Window Version'. Both include a VDD input, a SENSE input, a CT pin, a RESET output, and an MR input. The 'Undervoltage Only Version' primarily uses an UV comparator, while the 'Window Version' uses both UV and OV comparators. Both incorporate a voltage reference, time delay logic, and an internal pulldown resistor for the MR pin. The CT pin controls the reset delay timing.

8.3 Feature Description

8.3.1 VDD

The TPS3703 operates from a 1.7 V to 5.5 V supply. A 0.1-µF capacitor between VDD and GND is recommended for noisy supplies. The device requires VDD to be at or above VDD(MIN) for at least the startup delay (tSD + tD) to function correctly.

8.3.2 SENSE

The SENSE pin monitors the supply voltage. It uses two comparators with a precision reference and trimmed resistors for high accuracy. Built-in hysteresis provides noise immunity. For noisy applications, a 1-nF to 10-nF bypass capacitor on the SENSE pin is recommended. If monitoring VDD, the SENSE pin can be connected directly to VDD.

8.3.3 RESET

The RESET output is an active-low, open-drain output requiring a pull-up resistor. It asserts low when the SENSE voltage exceeds the OV threshold or falls below the UV threshold. The pull-up resistor value depends on VOL, capacitive loading, and leakage current. It can be wired-OR with other open-drain signals. The output is high impedance when the SENSE voltage is within the valid window.

Figure 8-1. RESET output: This timing diagram shows the relationship between VSENSE and the RESET output. When VSENSE exceeds the OV limit (VIT+(OV)) or falls below the UV limit (VIT-(UV)), RESET is asserted low after a delay (tPD). RESET remains low until VSENSE is within the hysteresis bands (VIT+(OV) - VHYS and VIT-(UV) + VHYS), after which it deasserts after a delay (tD).

8.3.4 Capacitor Time (CT)

The CT pin offers factory-programmed and user-programmable reset delay timing. Options include leaving CT unconnected, pulling it up to VDD via a resistor (10 kΩ recommended), or connecting an external capacitor to ground. The device uses an internal state machine to determine the CT configuration, taking 450 µs to evaluate. The reset delay is re-evaluated when VSENSE enters the valid window.

8.3.5 Manual Reset (MR)

The MR pin initiates a reset. A logic low on MR asserts RESET. After MR returns high and VSENSE is within the valid window, RESET deasserts after delay tD. If not controlled externally, MR can be connected to VDD or left floating as it has an internal pull-up.

Figure 8-2. Manual Reset Timing Diagram: This diagram illustrates the timing relationship between MR and RESET. When MR is pulled low (below VMR_L), RESET asserts low. After MR returns high and VSENSE is within its valid window, RESET deasserts after time tD. It also shows the MR pin pulse width requirement (tMR_W) and propagation delay (tPD(MR)).

8.4 Device Functional Modes

8.4.1 Normal Operation (VDD > VDD(MIN)): When VDD is above VDD(MIN) for the required startup delay, the RESET output state reflects the SENSE voltage relative to the thresholds. If SENSE is outside limits, RESET is low.

8.4.2 Undervoltage Lockout (VPOR < VDD < UVLO): If VDD is below UVLO but above VPOR, RESET is held low regardless of the SENSE voltage.

8.4.3 Power-On Reset (VDD < VPOR): When VDD is below VPOR, the RESET signal is undefined and unreliable.

9 Application and Implementation

9.1 Application Information

9.1.1 Voltage Threshold Accuracy

The TPS3703's high precision (±0.7% Max) allows for wider supply voltage margins and threshold headroom, beneficial for tight tolerance applications. For example, in an MCU power supply, a ±5% tolerance on the MCU's core voltage can be managed with the TPS3703's ±4% threshold. This flexibility allows for relaxed DC/DC converter designs, potentially using smaller components, due to increased margin for voltage ripple and transients.

Figure 9-1. TPS3703 Voltage Threshold Accuracy: This diagram visually explains the benefit of high accuracy supervisors. It shows a DC/DC nominal output with margins for ripple and transients. A higher accuracy supervisor (like TPS3703) leaves more margin for system voltage and transients compared to a lower accuracy supervisor, which would consume more of the available budget and lead to a more stringent design.

9.1.2 CT Reset Time Delay

The TPS3703 offers three options for setting the reset delay (tD): connecting a capacitor to the CT pin, using a pull-up resistor to VDD, or leaving CT unconnected. An internal state machine determines the selected option by measuring the pin voltage after 450 µs. This evaluation occurs whenever VSENSE enters the valid window.

Figure 9-2. CT Charging Circuit: This schematic shows the three CT pin configurations: User Programmable Capacitor to GND, 10 kΩ Resistor to VDD, and CT Unconnected. Each configuration influences the reset delay timing.

9.1.2.2 Programmable Reset Delay-Timing

The programmable reset delay is based on the internal current source (ICT) charging an external capacitor (CCT). The minimum capacitor value is 250 pF. The typical delay time (tD) in ms can be calculated using Equation 1: tD = 3.066 × CCT + 0.5 ms, where CCT is in nF. Minimum and maximum delay times can be calculated using Equations 2 and 3, respectively.

9.1.3 RESET Latch Mode

The TPS3703 supports a voltage latch mode for the RESET pin. When the CT pin is connected to ground with a pull-down resistor (10 kΩ recommended), the RESET pin, once low, remains low irrespective of the SENSE voltage. To unlatch, a voltage greater than the CT pin comparator threshold voltage (VCT, typically > 1.15 V) must be applied to the CT pin. The RESET pin then goes high instantaneously without delay.

Figure 9-3. RESET Latch Circuit: This schematic shows the RESET latch configuration. A pull-down resistor is connected to the CT pin. To unlatch, a voltage source is applied to the CT pin, which is limited by a series resistor. To re-enter latch mode, the voltage is removed from the CT pin.

9.1.4 Adjustable Voltage Thresholds

The TPS3703's accuracy allows for adjustable voltage thresholds using external resistor dividers without significant inaccuracy. This is useful when desired monitored voltages are not directly available. TI recommends using devices with a 0.8V voltage threshold option (e.g., TPS3703B3080) for bypass mode internal resistor ladder. Equations are provided to calculate resistor values and account for internal SENSE pin resistance (RSENSE).

Figure 9-4. Adjustable Voltage Threshold with External Resistor Dividers: This circuit diagram shows how to set adjustable voltage thresholds using an external resistor divider (R1, R2) connected to the SENSE pin, along with the TPS3703 IC.

9.1.5 Immunity to SENSE Pin Voltage Transients

The TPS3703 is immune to short voltage transient spikes on its input pins. Sensitivity depends on transient duration and overdrive (amplitude). Overdrive is calculated as a percentage of the threshold, indicating how much VSENSE exceeds the specified threshold.

9.1.5.1 Hysteresis

Built-in hysteresis in the OV and UV comparators provides noise immunity and stable operation. If VSENSE falls below VIT-(UV) or rises above VIT+(OV), RESET asserts low. RESET deasserts when VSENSE is between the positive and negative threshold voltages (within the hysteresis bands), after the user-defined delay.

Figure 9-5. SENSE Pin Hysteresis: This graph visually represents the hysteresis effect. It shows the VSENSE voltage range and how the RESET output transitions based on crossing the VIT thresholds and entering/exiting the hysteresis bands (VIT+(OV) - VHYS and VIT-(UV) + VHYS).

9.2 Typical Application

9.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails

This application uses two TPS3703 devices to monitor the core and I/O voltage rails of a microcontroller. This ensures accurate reset delay and voltage supervision for critical power rails.

Figure 9-6. Two TPS3703 Monitoring Two Microcontroller Power Rails: This circuit diagram shows two TPS3703 ICs connected to monitor separate voltage rails (VCORE and V1/0) of a microcontroller. Each TPS3703 is configured with its SENSE pin connected to the respective power rail, and its RESET pin outputting a signal to the microcontroller.

Application Curves (Figures 9-7 to 9-10):

• Figure 9-7. TPS3703 SENSE Start Up Function: Waveforms showing VSENSE, VDD, and VRESET during a VSENSE startup from 0V to 1.2V.
• Figure 9-8. TPS3703 VDD Start Up Function: Waveforms showing VDD, VSENSE, and VRESET during a VDD startup from 0V to 3.3V.
• Figure 9-9. TPS3703 Overvoltage and Undervoltage Function: Waveforms showing VSENSE ramp from 0V to 1.4V and the resulting VRESET behavior, illustrating OV and UV detection.
• Figure 9-10. TPS3703 VDD Ramp Up Function: Waveforms showing VDD ramp up from 0V to 3.3V and the corresponding VRESET behavior.

9.2.2 Design 2: RESET Latch Mode

This application utilizes the TPS3703 in a RESET latch output mode. Once RESET is driven low, it remains low regardless of the sense voltage. If the RESET pin is low on startup, it also stays low until the latch is cleared.

Figure 9-11. Window Voltage Monitoring with RESET Latch: This circuit diagram shows a typical application for the TPS3703 in RESET latch mode, monitoring a 1.2-VCORE rail.

Application Curves (Figures 9-12 to 9-15):

• Figure 9-12. TPS3703 SENSE Ramp Latch Function: Waveforms illustrating VSENSE ramp and RESET latch behavior.
• Figure 9-13. TPS3703 CT Bias Unlatch Function: Waveforms showing how applying a voltage to the CT pin unlatches the RESET output.
• Figure 9-14. TPS3703 Overvoltage and Undervoltage Latch Function: Waveforms demonstrating OV/UV detection and latching behavior.
• Figure 9-15. TPS3703 VDD Ramp Latch Function: Waveforms showing VDD ramp up and the corresponding RESET latch behavior.

10 Power Supply Recommendations

10.1 Power Supply Guidelines

The TPS3703 operates from 1.7 V to 5.5 V with a 6-V absolute maximum rating on VDD. A 0.1-µF to 1-µF capacitor between VDD and GND is recommended for input supply noise filtering. Additional precautions may be needed for supplies susceptible to large voltage transients; refer to SNVA849 for details.

11 Layout

11.1 Layout Guidelines

• Place external components close to the device to prevent parasitic errors.
• Avoid long traces for the VDD supply node to prevent LC circuit ringing.
• Avoid long traces to the SENSE pin to prevent inaccurate monitoring due to parasitic inductance.
• Do not run sensitive analog traces parallel to digital traces; use perpendicular crossings only when necessary.

11.2 Layout Example

Figure 11-1. Recommended Layout: This diagram shows a recommended PCB layout for the TPS3703, including placement of external components like the VDD bypass capacitor (1 µF) and pull-up resistor (10 kΩ) for the RESET pin.

12 Device and Documentation Support

12.1 Device Nomenclature

Table 12-1 defines the device naming convention. The part number encodes options for Time Delay, Tolerance, Nominal Threshold Voltage, and Package. For example, 'TPS3703A4330DSE' indicates a specific time delay (A), tolerance (4%), nominal threshold (3.30V), and package (DSE - WSON 6-pin).

12.2 Documentation Support

An Evaluation Module (EVM) is available for performance evaluation. It can be requested via the TI website or purchased from the TI eStore.

12.3 Receiving Notification of Documentation Updates

Navigate to the device product folder on ti.com and subscribe to updates to receive notifications of documentation changes.

12.4 Support Resources

TI E2E™ support forums provide expert answers and design help. Linked content is provided "AS IS" and does not constitute TI specifications.

12.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All other trademarks are property of their respective owners.

12.6 Electrostatic Discharge Caution

Integrated circuits can be damaged by ESD. Handle with appropriate precautions to prevent performance degradation or failure. Precision ICs may be more susceptible to damage from small parametric changes.

12.7 Glossary

A glossary of TI terms, acronyms, and definitions is available.

13 Mechanical, Packaging, and Orderable Information

This section provides mechanical, packaging, and orderable information for the designated devices. This data is subject to change without notice. Detailed tables listing orderable part numbers, package types, quantities, and other specifications are available in the addendum sections.

Package Outline and Layout Examples: Diagrams are provided for the WSON package outline (DSE0006A) showing dimensions and pin identification, as well as example board layout and solder paste stencil designs for PCB implementation.

Important Notice and Disclaimer

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