Nios II Simple Socket Server on CVGT FPGA Development Kit
Date: 21 January 2016
Revision: 1.0
1. Introduction
This design example demonstrates a socket server implementation using the NicheStack TCP/IP stack, Nios II Edition, on a MicroC/OS-II operating system running on an Altera Cyclone V GT development board. The server is designed to process simple commands to control the board's LEDs via a dedicated MicroC/OS-II task.
2. Required Hardware and Software
- Altera Cyclone V GT Development Kit Rev B
- Mini USB cable for device programming
- Ethernet Cable
- PC running Windows 7 64-bit or Linux
- ACDS version 15.0
3. Block Diagram
Figure 1 shows the major IP blocks within the Simple Socket Server design. Details of the connections between these IP blocks are available in the included Qsys files for this design example.
Figure 1: Major IP blocks within the Simple Socket Server Design Example. The block diagram illustrates the major IP blocks within the Simple Socket Server design. It shows a top-level system (top.v) connecting to an Ethernet standard main system (eth_std_main_system.qsys). This main system includes two subsystems: peripheral_subsystem.qsys (containing System Timer, High-res Timer, Perf Counter, JTAG UART, PIO, and LED components) and ethernet_subsystem.qsys (containing TSE, TX SGDMA, RX SGDMA, and Descriptor memory). These subsystems interface with the Nios II processor, Flash Controller, DDR3 Controller, and PLL.
4. Demo Setup
First, ensure that the jumpers and switches on the Altera Cyclone V GT development board are set to their default configurations. For detailed information and documentation regarding the Altera Cyclone V GT development board, refer to the provided link.
4.1 Programming the Simple Socket Server Design
1. Connect the USB Blaster cable from the PC to the on-board USB Blaster II connector, as depicted in Figure 2.
Figure 2: Location of the on-board USB Blaster II connector. An image displays the Altera Cyclone V FPGA Development Kit, highlighting the location of the on-board USB Blaster II connector, used for programming the device.
2. Open the Quartus programmer and select the on-board USB-Blaster II hardware. Press "Auto Detect" and select "5CGTD9E5" when prompted by the programmer. Two devices should then appear in the scan chain, as shown in Figure 3.
Figure 3: Devices in the Scan chain. The Quartus programmer interface is shown, indicating two devices detected in the scan chain: 5CGTD9E5F35 and 5M2210Z, confirming successful hardware detection.
3. Click "Change File" and select the .sof file named "niosii_ethernet_standard_5CGTFD9E.sof" from the <project directory>/master_image folder. Then, select "Program/Configure".
4. Press "Start" and wait for the device to be successfully programmed, as illustrated in Figure 4 and confirmed in Figure 5.
Figure 4: Programming the device with the provided .sof file. The Quartus programmer screen shows the programming process in progress, with the niosii_ethernet_standard_5CGTFD9E.sof file selected for programming the device.
Figure 5: Successful programming of the device. The Quartus programmer interface confirms that the device programming is 100% successful.
4.2 Executing the Simple Socket Server Program
1. Connect the Ethernet cable from the PC's RJ45 port to the RJ45 connector on the Altera Cyclone V GT development board, as shown in Figure 6.
Figure 6: Location of the Ethernet port on Altera Cyclone V GT development board. An image of the Altera Cyclone V FPGA Development Board points out the location of the Ethernet port, which is used to connect the board to a PC.
2. Configure the PC's LAN adapter to use a static IP address for TCP/IPv4. An example configuration is shown in Figure 7, typically setting an IP address like 192.168.1.x with a subnet mask of 255.255.255.0.
Figure 7: Change the PC's LAN adapter setting to use static IP. A screenshot of the Windows TCP/IPv4 Properties dialog box illustrates how to configure a static IP address for the PC's LAN adapter, typically setting an IP address like 192.168.1.x with a subnet mask of 255.255.255.0.
3. Launch the Nios II Command Shell. On Microsoft Windows, this is typically found via Start → All Programs → Altera → Nios II EDS <version> → Nios II <version> Command Shell. On Linux, execute the command: <Nios II EDS install path>/nios2_command_shell.sh.
4. Enter the following command in the Nios II Command Shell and press Enter:
nios2-download -g <project directory>/master_image/CVGT_simple_socket_server.elf && nios2-terminal
5. The program download to the Nios processor should begin. A note is provided regarding a potential message prompting for a 9-digit serial number (Figure 8), which occurs if the board's MAC address is not readable from the CFI Flash. In such cases, a MAC address is generated, and static network settings are applied.
Figure 8: Potential message requesting for 9-digit serial number. A message from InterNiche Portable TCP/IP v3.1 is displayed, which may appear if the board's MAC address cannot be read from the flash. It prompts the user to enter a 9-digit serial number to generate a MAC address.
6. In this design example, the source code files (located in the <project directory>/software/src folder) are pre-configured to use the IP address 192.168.1.234 when no DHCP server is detected, which is the case when the board is connected directly to the PC. The Nios II Command Shell output will display the IP address and the listening port, as shown in Figure 9.
Figure 9: Note the IP address and port number used in this design example. The Nios II Command Shell output shows the system initializing, detecting the Ethernet link, and reporting the assigned IP address as 192.168.1.234 and the listening port as 30.
4.3 Running Simple MicroC/OS-II Task to Control LED
1. Launch a telnet client on your PC, such as PuTTY or the Windows Telnet Client. Establish a telnet session to the IP address 192.168.1.234 on port 30. The Telnet client display should show the menu presented in Figure 10.
Figure 10: Telnet client successfully connected to the development board. The Telnet client interface displays the Nios II Simple Socket Server menu, offering options to toggle board LEDs (0-7), initiate a 7-segment LED light show, or terminate the session.
2. Enter numbers 0 through 7 to toggle the on-board LEDs. As you do this, the Nios II command shell will display a confirmation message indicating that the value for the LED_PIO_BASE register has been modified, as shown in Figure 11.
Figure 11: The Nios II Command Shell displayed confirmation message that the request to toggle LED has been received. The Nios II Command Shell output confirms that commands received from the telnet client have modified the LED_PIO_BASE register, showing the specific values set for each LED toggle (e.g., Value for LED_PIO_BASE set to 1, 3, 7, etc.).
3. Figure 12 illustrates the physical location of LEDs 0-7 on the Altera Cyclone V GT development board.
Figure 12: Location of LED 0-7 on Altera Cyclone V GT development board. An image of the Altera Cyclone V FPGA Development Board highlights the physical location of LEDs 0 through 7 on the board.
4. Press "Q" in the telnet client to close the telnet session. Press "Ctrl - C" in the Nios II Command Shell to terminate the session.
5. Modifying the Simple Socket Server Hardware Design
Follow the instructions on the Design Store web page to install the design template. Upon successful installation, three .qsys system files will be present in the project directory: eth_std_main_system.qsys, peripheral_system.qsys, and ethernet_system.qsys. The peripheral_system.qsys and ethernet_system.qsys files are Qsys subsystems within the top-level system eth_std_main_system.qsys, as previously shown in Figure 1. You can utilize the Qsys tool within Quartus II to add, remove, or modify individual IP components in the design.
After updating the Qsys systems, remember to click "Generate HDL..." to regenerate the necessary files required by Quartus during compilation. For more information on using the Qsys tool, refer to the online tutorial linked in the document.
The top-level connection for each exported Qsys port is defined in the file top.v. If you add or remove IPs from the Qsys systems, ensure that this file is updated accordingly to reflect the changes in exported Qsys ports.
6. Modifying the Simple Socket Server Software Design
The Simple Socket Server software utilized in this design example is based on the existing Simple Socket Server template available within the Nios Software Build Tools. For more details on this template, consult pages 1-16 of the document "Using the NicheStack TCP/IP Stack - Nios II Edition," accessible via the provided link. If you are unfamiliar with the Nios II Eclipse tool's GUI, refer to the linked document for assistance.
After generating the Simple Socket Server template using Nios II – Eclipse, you can replace the default .c and .h files with those provided in the <project directory>/software/src folder. These modified files are updated to match the Qsys system names and to assign a static IP address. For instance, the IP address configuration can be modified in the simple_socket_server.h file, as illustrated in Figure 13.
Figure 13: Static IP address can be set in the file "simple_socket_server.h". A code snippet from the simple_socket_server.h file demonstrates how to configure static IP addresses, gateway, and subnet mask using #define directives.
Remember to save and recompile the project after making any changes.
7. Revision History
| Revision | Description |
|---|---|
| 1.0 | Initial Revision |
