Arrow.com View guide user manual
101 Innovation Drive San Jose, CA 95134 www.altera.com MNL-01067-1.1 Reference Manual Arria V GX FPGA Development Board FeedbackSubscribe Arria V GX FPGA Development Board Reference Manual
File Info : application/pdf, 90 Pages, 1.96MB
DocumentDocumentArria V GX FPGA Development Board Reference Manual Arria V GX FPGA Development Board Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com MNL-01067-1.1 Downloaded from Arrow.com. Feedback Subscribe © 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. Contents Chapter 1. Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Dual FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FPGA 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FPGA 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 2. Board Components Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Featured Device: Arria V GX FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MAX II CPLD EPM2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 FPGA Programming over On-Board USB-Blaster II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 JTAG Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 PCI Express Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 MAX II Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Configuration Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Image Select Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 On-Board Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Off-Board Clock Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 User-Defined DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 General User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 HSMC User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 SDI Video Output/Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 HSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 SFP+ Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 FMC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Bull's Eye Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. iv Contents DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 DDR3A for FPGA 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 DDR3B/C for FPGA 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 QDRII+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Additional Information Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info1 Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation 1. Overview This document describes the hardware features of the Arria® V GX FPGA development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board. General Description The Arria V GX FPGA development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera's Arria V GX FPGA device. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Arria V GX FPGA designs. Two high-speed mezzanine card (HSMC) connectors are available to add additional functionality via a variety of HSMCs available from Altera® and various partners. f To see a list of the latest HSMCs available or to download a copy of the HSMC specification, refer to the Development Board Daughtercards page of the Altera website. Design advancements and innovations, such as the PCI Express hard IP implementation and programmable power technology ensure that designs implemented in the Arria V GX FPGAs operate faster, with lower power, and have a faster time to market than previous FPGA families. f For more information on the following topics, refer to the respective documents: Arria V device family, refer to the Arria V GX Device Handbook. PCI Express MegaCore function, refer to the PCI Express Compiler User Guide. HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification. November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 12 Chapter 1: Overview Board Component Blocks Board Component Blocks The development board features the following major component blocks: Two Arria V GX FPGA 5AGXFB3HF40 in the 1517-pin FineLine BGA (FBGA) package 362 LEs 136,880 adaptive logic modules (ALMs) 17,260 Kbit (Kb) M10K on-die memory 2,098 Kb MLAB memory 24 6-Gbps transceivers 12 phase locked loops (PLLs) 2,090 18x18 multipliers 1.1-V core voltage MAX® II CPLD EPM2210GF324 System Controller in the 324-pin FBGA package FPGA configuration circuitry MAX II CPLD EPM570GM100 and flash fast passive parallel (FPP) configuration On-board USB-BlasterTM II for use with the Quartus® II Programmer Clocking circuitry Nine on-board oscillators One 50-MHz oscillator Two 125-MHz oscillators Clock buffer with six outputs sourced by SMA or programmable oscillator with a default frequency of 100-MHz One programmable oscillator with a default frequency of 148.5-MHz Four programmable oscillators with four outputs each of various default frequencies Clock buffer with two outputs sourced by one of the above four programmable oscillators with one output to the FPGA reference clock and Bull's Eye® SMA SMA connectors for external LVPECL clock input Power supply 14-V 20-V DC input PCI Express edge connector power 12-V PCI Express ATX supply On-board power measurement circuitry Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 1: Overview 13 Board Component Blocks Mechanical PCI Express long form factor (4.376" x 10.45") PCI Express chassis or bench-top operation Dual FPGA The development board includes two Arria V GX FPGAs that connect to other components on the board to provide a better transceiver and bandwidth design solution. FPGA 1 The first FPGA device (FPGA 1) connects to the following components: Communication ports One PCI Express x8 edge connector One universal HSMC expansion port (port A) One USB 2.0 connector One gigabit Ethernet port Chip-to-Chip (C2C) bridge with 29 LVDS inputs and 29 LVDS outputs, and x8 transceivers One small form factor pluggable plus (SFP+) channel One SMA 6 Gbps channel Memory 1152-Mbyte (MB) DDR3 SDRAM with a 72-bit data bus 4.5-MB QDRII+ SRAM 1-Gbit (Gb) synchronous flash with a 16-bit data bus November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 14 Chapter 1: Overview Board Component Blocks General user I/O LEDs and displays Eight dual color user LEDs Two-line character LCD display Three configuration select LEDs One configuration done LED Two HSMC interface transmit/receive (TX/RX) LEDs Three PCI Express LEDs Five Ethernet LEDs Push buttons One CPU reset push button One Max II CPLD EPM2210 System Controller configuration reset push button One load image push button (to program the FPGA from flash memory) One image select push button (select an image to load from flash memory) Three general user push buttons Eight MAX II control DIP switches FPGA 2 The second FPGA device (FPGA 2) connects to the following components: Communication ports One universal HSMC expansion port (port B) One FMC port C2C bridge with 29 LVDS inputs and 29 LVDS outputs, and x8 transceivers One serial digital interface (SDI) channel One Bull's Eye 6 Gbps transceiver channel One SMA 6 Gbps channel Memory 1024-MB DDR3 SDRAM with a 64-bit data bus (soft controller) 512-MB DDR3 SDRAM with a 32-bit data bus (hard IP controller) Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 1: Overview 15 Development Board Block Diagram General user I/O LEDs and displays Eight dual color user LEDs Two HSMC interface transmit/receive (TX/RX) LEDs Push buttons One CPU reset push button Three general user push buttons Eight MAX II control DIP switches Development Board Block Diagram Figure 11 shows a block diagram of the Arria V GX FPGA development board. Figure 11. Arria V GX FPGA Development Board Block Diagram Mini-USB 2.0 Z On-Board USB-Blaster II and USB Interface JTAG Chain USB Interface x19 SMAs 6G XCVR x1 Gigabit Ethernet x16 PHY (RGMII) SFP+ XCVR x1 x80 CLKIN x3 CLKOUT x3 XCVR x4 x11 Port A 2x16 LCD 5AGXFB3H4F40 FPGA 1 x72 1152-MB DDR3 (x72) SDI XCVR x1 x36 72-MB TX/RX QDRII+ XCVR x8 Chip-to Chip LVDS x29 Chip-to Chip LVDS x29 Chip-to Chip x4 Push buttons x8 DIP Switches x16 8 bi-color LEDs Bullseye 6G SMAs 6G XCVR x1 XCVR x1 x80 CLKIN x3 CLKOUT x3 XCVR x4 Port B 5AGXFB3H4F40 FPGA 2 x32 Hard IP (x64 Soff IP) DDR3 (x64) x4 Push Buttons x8 DIP Switches x16 8 bi-color LEDs XVCR x4 XVCR x8 ADDR x16 Programmable Oscillators + 50 M, 125 M x8 Edge CPLD 1-GB Flash Programmable Oscillators + FMC 50 M, 125 M Handling the Board When handling the board, it is important to observe the following static discharge precaution: c Without proper anti-static handling, the board can be damaged. Therefore, use anti-static handling precautions when touching the board. November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 16 Chapter 1: Overview Handling the Board Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation 2. Board Components Introduction This chapter introduces the major components on the Arria V GX FPGA development board. Figure 21 illustrates the component locations and Table 21 provides a brief description of all component features of the board. 1 A complete set of schematics, a physical layout database, and GERBER files for the development board reside in the Arria V GX FPGA development kit documents directory. f For information about powering up the board and installing the demonstration software, refer to the Arria V GX FPGA Development Kit, User Guide. This chapter consists of the following sections: "Board Overview" "Featured Device: Arria V GX FPGA" on page 26 "MAX II CPLD EPM2210 System Controller" on page 29 "Configuration, Status, and Setup Elements" on page 215 "Clock Circuitry" on page 224 "General User Input/Output" on page 229 "Components and Interfaces" on page 237 "Memory" on page 258 "Power Supply" on page 273 "Statement of China-RoHS Compliance" on page 277 November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 22 Chapter 2: Board Components Board Overview Board Overview This section provides an overview of the Arria V GX FPGA development board, including an annotated board image and component descriptions. Figure 21 shows an overview of the available components. Figure 21. Overview of the Arria V GX FPGA Development Board Features Flash Memory (U4) JTAG Connector (J1) MAX II CPLD EPM2210 System Controller (U2) Embedded USB-Blaster Circuitry (J7) Gigabit Ethernet Port (J8) SFP+ Port (J10) SFP+ Port (J15) [Available in Arria V GT Development Kit only] User LEDs (D18-D25) Configuration LEDs (D12-D17) CPU Reset User Push Configuration Push HSMC User DIP Buttons Push Buttons Button (S4) Port A (J2) Switch (SW2) (S5-S7) (S1-S3) DDR3B (U6, U12) FMC VCCPD B4 Select (J5) CPU Reset Push Button (S8) HSMC Port B (J3) User DIP Switch (SW3) User Push Buttons (S9-S11) User LEDs (D26-D33) Board Power Switch (SW1) ATX Power Connector (J4) DC Input Jack (J6) Character LCD (J29) FMC Connector (J9) Arria V GX FPGA (U16) Clock Input SMA Connector (J10, J11) Fan Power (J23) PCI Tx/Rx DDR3A Bullseye Express Edge Transceivers (U7, U11, U18, SMA Connector (J19-J22) U21, U28) Connector (J14) (J16) DDR3C Fan Power (U19, U22) (J14) Tx/Rx SDI Video Transceivers Port (J12, J13, (J26, J27) J24, J25) Arria V GX FPGA (U13) FMC Bank B Voltage Select (J11) FMC Bank B Power Source Select (J28) Table 21 describes the components and lists their corresponding board references. Table 21. Arria V GX FPGA Development Board Components (Part 1 of 4) Board Reference Type Description Featured Devices U13, U16 FPGA U2 CPLD Two Arria V GX FPGA, 5AGXFB3HF40, 1517-pin FBGA. MAX II CPLD, EPM2210F324, 324-pin BGA. Configuration, Status, and Setup Elements J1 JTAG connector J7 On-Board USB-Blaster II SW5 Board settings DIP switch SW6 JTAG chain DIP switch SW7 PCI Express DIP switch Disables the on-board USB-Blaster II (for use with external USB-Blasters). Mini-USB 2.0 connector for programming and debugging the FPGA. Controls the MAX II CPLD EPM2210 System Controller functions such as clock enable, SMA clock input control, and which image to load from flash memory at power-up. This switch is located on the bottom of the board. Enables and disables devices in the JTAG chain. Controls the PCI Express lane width by connecting prsnt pins together on the PCI Express edge connector. This switch is located on the bottom of the board. Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components 23 Board Overview Table 21. Arria V GX FPGA Development Board Components (Part 2 of 4) Board Reference Type SW8 FPGA 1 mode select DIP switch SW4 FPGA 2 mode select DIP switch S2 Image select push button S3 Program configuration push button D1 Power LED D2, D3 JTAG Tx/Rx LEDs D4, D5 D6 D7, D8 D9 HSMC port A LEDs HSMC port A present LED HSMC port B LEDs HSMC port B present LED D10, D11 System Console Tx/Rx LEDs D12, D13, D14 Configuration LEDs D15 D16 D17 D36, D37, D38, D39, D40 D42, D43, D44 Error LED Configuration done LED Load LED Ethernet LEDs PCI Express link LEDs Description Sets the Arria V MSEL[4,2,1] pins. This switch is located on the bottom of the board. Sets the Arria V MSEL[4,2,1] pins. This switch is located on the bottom of the board. Toggles the configuration LEDs which selects the program image that loads from flash memory to the FPGA. Configures the FPGA from flash memory image based on the program LEDs. Illuminates when 5.0-V power is present. Indicate the transmit or receive activity of the JTAG chain. The Tx and Rx LEDs blink when the link is in use and active. The LEDs are off when not in use and on when in use or idle. You can configure these LEDs to indicate transmit or receive activity. Illuminates when a daughtercard is plugged into the HSMC port A. You can configure these LEDs to indicate transmit or receive activity. Illuminates when a daughtercard is plugged into the HSMC port B. Indicate the transmit or receive activity of the System Console USB interface. The Tx and Rx LEDs blink when the link is in use and active. The LEDs are off when not in use and on when in use or idle. Illuminates to show the LED sequence that determines which flash memory image loads to the FPGA when you press the PGM1_SEL push button. Illuminates when the FPGA configuration from flash memory fails. Illuminates when the FPGA is configured. Illuminates when the MAX II CPLD EPM2210 System Controller is actively configuring the FPGA. Shows the connection speed as well as transmit or receive activity. You can configure these LEDs to display the PCI Express link width (x1, x4, x8). Clock Circuitry U48 Si5338 programmable oscillator U53 Si5338 programmable oscillator U52 Si5338 programmable oscillator Programmable oscillator with default frequencies of CLK0=125 MHz, CLK1=100 MHz, CLK2=625 MHz, CLK3=125 MHz at I2C address 71 HEX. The frequency is programmable using the clock GUI with the default MAX II CPLD EPM2210 System Controller design programmed into the MAX II EPM2210. Programmable oscillator with default frequencies of CLK0=625 MHz, CLK1=156.25 MHz, CLK2=125 MHz, CLK3=125 MHz at I2C address 70 HEX. The frequency is programmable using the clock GUI with the default MAX II CPLD EPM2210 System Controller design programmed into the MAX II EPM2210. Programmable oscillator with default frequencies of CLK0=125 MHz, CLK1=100 MHz, CLK2=156.25 MHz, CLK3=125 MHz at I2C address 73 HEX. The frequency is programmable using the clock GUI with the default MAX II CPLD EPM2210 System Controller design programmed into the MAX II EPM2210. November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 24 Chapter 2: Board Components Board Overview Table 21. Arria V GX FPGA Development Board Components (Part 3 of 4) Board Reference Type Description Programmable oscillator with default frequencies of CLK0=625 MHz, U34 Si5338 programmable oscillator CLK1=100 MHz, CLK2=625 MHz, CLK3=125 MHz at I2C address 72 HEX. The frequency is programmable using the clock GUI with the default MAX II CPLD EPM2210 System Controller design programmed into the MAX II EPM2210. X1 125 MHz oscillator 125.000 MHz crystal oscillator for general purpose logic to FPGA 1. X4 125 MHz oscillator 125.000 MHz crystal oscillator for general purpose logic to FPGA 2. Programmable oscillator for SDI or REFCLK0RP/N with default X2 Si571 programmable frequencies at I2C address 55 HEX. The frequency is programmable Oscillator (148.5 MHz default) using the clock GUI with the default MAX II EPM2210 System Controller design programmed into the MAX II EPM2210. X7, or J17 and Programmable oscillator J18 to U56 buffer (100 MHz default) Programmable oscillator with a default frequency of 100.00 MHz. The frequency is programmable using the clock GUI with the default MAX II CPLD EPM2210 System Controller design programmed into the MAX II EPM2210. Multiplex with CLKIN_SMA_P/N based on CLK_SEL switch value. X6 to U51 1:3 zero delay clock buffer 50 MHz oscillator 50.000 MHz crystal oscillator for general purpose logic. Three outputs connect to the FPGA 1, FPGA 2, and MAX II devices. J17, J18 Clock input SMAs Drive LVPECL-compatible clock inputs into the clock multiplexer buffer (U56). General User Input/Output SW2 FPGA 1 user DIP switch Octal user DIP switches. When the switch is ON, a logic 0 is selected. SW3 FPGA 2 user DIP switch Octal user DIP switches. When the switch is ON, a logic 0 is selected. S1 MAX II reset push button Resets the MAX II CPLD EPM2210 System Controller. S4 FPGA 1 CPU reset push button Resets the FPGA 1 logic. S8 FPGA 2 CPU reset push button Resets the FPGA 2 logic. S5S7 FPGA 1 general user push buttons Three user push buttons. Driven low when pressed. S9S11 FPGA 2 general user push buttons Three user push buttons. Driven low when pressed. D18D25 FPGA 1 user LEDs Eight bi-color user LEDs. Illuminates when driven low. D26D33 FPGA 2 user LEDs Eight bi-color user LEDs. Illuminates when driven low. D35 FPGA 1 LED LED indicator for FPGA 1. D32 FPGA 2 LED LED indicator for FPGA 2. Memory Devices U4 Flash x16 memory U8 QDRII+ memory U7, U11, U18, U21, U28 DDR3A memory Synchronous burst mode flash device that provides a 16-bit 125-MB non-volatile memory port. 9-MB QDRII+ SRAM with a 36-bit data bus. The device has a separate 36-bit read and 36-bit write port with DDR signalling at up to 533 MHz. DDR3 SDRAM interface on FPGA 1. This 1152-MB DDR3 x72-bit data bus consists of four x16 devices and one x8 device with a single address or command bus. Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components 25 Board Overview Table 21. Arria V GX FPGA Development Board Components (Part 4 of 4) Board Reference Type U6, U12, U19, U22 DDR3B/C memory Description DDR3 SDRAM interface on FPGA 2. There are two interface options: Option 1: 512-MB interface with a 32-bit data bus. This DDR3 x32-bit data bus consists of two x16 devices with a single shared address. Option 2: 1024-MB interface with a 64-bit data bus. This DDR3 x64-bit data bus consists of four x16 devices with a single shared address. Communication Ports J30 PCI Express edge connector J2 HSMC port A J3 HSMC port B J7 Mini-USB type-AB connector J8 Gigabit Ethernet Gold-plated edge fingers connector for up to ×8 signaling in Gen1 and x4 Gen2 modes. Provides four transceiver channels and 80 CMOS or 17 LVDS channels per the HSMC specification. Provides four transceiver channels and 80 CMOS or 17 LVDS channels per the HSMC specification. USB interface for programming the FPGA through on-board USB-Blaster II JTAG via a type-AB Mini-USB cable. RJ-45 connector which provides a 10/100/1000 Ethernet connection via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode. Display Ports J29 Character LCD connector Connector which interfaces to the provided 16 character × 2 line LCD module along with two standoffs at MTH7 and MTH8. Power Supply J6 J4 J30 SW1 DC input jack ATX power connector PCI Express edge connector Power switch Accepts a 19-V DC power supply. Do not use this input jack while the board is plugged into a PCI Express slot. PCI Express auxiliary power source option. Interfaces to a PCI Express root port such as an appropriate PC motherboard. Switch to power on or off the board when power is supplied from the DC input jack. November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 26 Chapter 2: Board Components Featured Device: Arria V GX FPGA Featured Device: Arria V GX FPGA The Arria V GX FPGA development board features two Arria V GX FPGA 5AGXFB3HF40 device (U13 and U16) in a 1517-pin FBGA package. f For more information about Arria V device family, refer to the Arria V GX Device Handbook. Table 22 describes the features of the Arria V GX FPGA 5AGXFB3HF40 device. Table 22. Arria V GX FPGA Features ALMs Equivalent M10K RAM Total RAM 18-bit × 18-bit LEs Blocks Kbits Multipliers PLLs Transceivers Package Type 136,880 362,000 17,260 19,358 2,090 12 24 1517-pin FBGA Table 23 lists the Arria V GX FPGA component reference and manufacturing information. Table 23. Arria V GX FPGA Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number U13, U16 FPGA, Arria V GX F1517, 362K LEs, leadfree Altera Corporation 5AGXFB3HF40 Manufacturer Website www.altera.com Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components 27 Featured Device: Arria V GX FPGA I/O Resources Figure 22 illustrates the bank organization and I/O count for the Arria V GX FPGA 5AGXFB3HF40 device in the 1517-pin FBGA package. Figure 22. Arria V GX FPGA Device I/O Bank Diagrams 2.5 V HSMA SFP+ USER ENET PCIe AW1 48 Bank 4A 48 Bank 4B 32 Bank 4C 48 Bank 4D 1.8 V 48 Bank 3D C2C HSMA x8 x4 GXB_R XCVRs 5AGXFB3HF40 FPGA 1 A1 Bank 7A 48 Bank 7B 48 Bank 7C 32 Bank 7D 48 Bank 8D 48 2.5 V Chip-to-Chip LCD USER 1.5 V QDRII+ Flash/MAX 48 Bank 3C 32 Bank 3B GXB_L XCVRs Bank 8C 48 Bank 8B 32 48 Bank 3A PCIe x8 SFP+ x1 SMA Bank 8A 48 DDR3 x72 USB 1.5 V DDR3 x64 2.5 V Chip-to-Chip 48 Bank 8A 32 Bank 8B 48 Bank 8C C2C x8 GXB_L XCVRs Bank 3A 48 Bank 3B 32 Bank 3C 48 48 Bank 8D 48 Bank 7D 5AGXFB3HF40 FPGA 2 Bank 3D 48 Bank 4D 48 32 Bank 7C Bank 4C 32 48 Bank 7B GXB_R XCVRs Bank 4B 48 48 Bank 7A A1 FMC x4 Bullseye SMA SMA SDI HSMB x1 x4 Bank 4A 48 2.5 V HSMB SDI USER 2.5 V FMC Table 24 lists the Arria V GX FPGA 1 pin count and usage by function on the development board. Clocks are listed under special pins as it uses dedicated I/O pins. Table 24. Arria V GX FPGA 1 Pin Count and Usage (Part 1 of 2) Function I/O Standard DDR3 ×72 interface QDRII+ ×36 interface MAX II System Controller 1.5-V SSTL 1.8-V HSTL 1.8-V CMOS I/O Count 125 103 8 Special Pins 1 differential ×9 differential DQS 1 differential ×36 differential DQS -- November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 28 Chapter 2: Board Components Featured Device: Arria V GX FPGA Table 24. Arria V GX FPGA 1 Pin Count and Usage (Part 2 of 2) Function Flash PCI Express HSMC port A Gigabit Ethernet On-Board USB-Blaster II SFP+ Chip-to-chip bridge Buttons Switches LCD LEDs Clocks or Oscillators I/O Standard 1.8-V CMOS 2.5-V CMOS 2.5-V CMOS + LVDS 2.5-V CMOS + LVDS 1.5-V/2.5-V CMOS 2.5-V CMOS 2.5-V 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 1.8-V CMOS + LVDS Total I/O Used: Transceivers SMA -- HSMC port A -- PCI Express -- Chip-to-chip bridge -- SFP+ -- Total Transceiver Used: I/O Count 49 10 84 16 19 16 120 3 4 11 16 10 625 4 16 32 32 4 88 Special Pins -- 1 reference clock 1 reference clock -- -- 2 reference clocks 2 reference clocks -- -- -- -- 5 differential clocks, 1 single-ended -- -- -- -- -- Table 24 lists the Arria V GX FPGA 2 pin count and usage by function on the development board. Clocks are listed under special pins as it uses dedicated I/O pins. Table 25. Arria V GX FPGA 2 Pin Count and Usage (Part 1 of 2) Function DDR3 ×64 device HSMC port B FMC SDI Chip-to-chip bridge Buttons Switches LEDs Clocks or Oscillators I/O Standard 1.5-V SSTL 2.5-V CMOS + LVDS 2.5-V 2.5-V CMOS 2.5-V 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 1.8-V CMOS + LVDS Total I/O Used: Transceivers SMAs or Bull's Eye -- HSMC port B -- I/O Count 156 84 178 8 120 4 8 16 10 584 8 16 Special Pins 1 differential ×9 differential DQS 1 reference clock 1 reference clock 1 reference clock 1 reference clock -- -- -- 5 differential clocks, 1 single-ended -- -- Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components 29 MAX II CPLD EPM2210 System Controller Table 25. Arria V GX FPGA 2 Pin Count and Usage (Part 2 of 2) Function I/O Standard I/O Count FMC Chip-to-chip bridge -- 16 -- -- 32 -- Total Transceivers: 88 Special Pins MAX II CPLD EPM2210 System Controller The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the following purposes: FPGA configuration from flash Power consumption monitoring Virtual JTAG interface for PC-based GUI Control registers for clocks Control registers for remote system update Figure 23 illustrates the MAX II CPLD EPM2210 System Controller's functionality and external circuit connections as a block diagram. Figure 23. MAX II CPLD EPM2210 System Controller Block Diagram MAX II CPLD PC JTAG Control Embedded Blaster SLD-HUB Encoder Virtual-JTAG Decoder Power Measurement Results LTC2418 Controller Power Calculations Information Register Control Register PFL A5GX Flash GPIO November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 210 Chapter 2: Board Components MAX II CPLD EPM2210 System Controller Table 26 lists the I/O signals present on the MAX II CPLD EPM2210 System Controller. The signal names and functions are relative to the MAX II device (U2). Table 26. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 1 of 5) Schematic Signal Name CLK125A_EN CLK125B_EN CLK50_EN CLK_CONFIG CLK_ENABLE CLK_SEL CLKIN_MAX_50 CLOCK_SCL CLOCK_SDA CPU1_RESETN CPU2_RESETN DEVICE1_LED DEVICE2_LED EXTRA_SIG0 EXTRA_SIG1 EXTRA_SIG2 FACTORY_USER1 FACTORY_USER2 FACTORY_REQUEST FACTORY_STATUS FLASH_ACCESSN FLASH_ADVN FLASH_CEN FLASH_CLK FLASH_OEN FLASH_RDYBSYN FLASH_RESETN FLASH_WEN FM_A0 FM_A1 FM_A2 FM_A3 FM_A4 FM_A5 FM_A6 FM_A7 MAX II CPLD Pin Number I/O Standard Description B13 2.5-V 125 MHz oscillator enable D7 2.5-V 125 MHz oscillator enable D11 2.5-V 50 MHz oscillator enable K6 2.5-V 100 MHz configuration clock input B5 2.5-V DIP switch for clock oscillator enable E7 2.5-V DIP switch for clock select--SMA or oscillator K13 2.5-V 50 MHz clock input C14 2.5-V Programmable oscillator I2C clock L4 2.5-V Programmable oscillator I2C data B8 2.5-V FPGA 1 reset push button E6 2.5-V FPGA 2 reset push button D13 2.5-V FPGA 1 configuration done LED C15 2.5-V FPGA 2 configuration done LED B10 2.5-V Reserved for future use. F16 1.8-V Reserved for future use. J16 1.8-V Reserved for future use. A5 2.5-V Load factory or user design at power-up C4 2.5-V Load factory or user design at power-up B9 2.5-V On-Board USB-Blaster II request to send FACTORY command F10 2.5-V On-Board USB-Blaster II FACTORY command status B12 1.8-V FM bus flash memory access indication G15 1.8-V FM bus flash memory address valid E16 1.8-V FM bus flash memory chip enable E17 1.8-V FM bus flash memory clock F14 1.8-V FM bus flash memory output enable D18 1.8-V FM bus flash memory ready F13 1.8-V FM bus flash memory reset D17 1.8-V FM bus flash memory write enable T17 1.8-V FM bus address R15 1.8-V FM bus address T16 1.8-V FM bus address F15 1.8-V FM bus address R16 1.8-V FM bus address P15 1.8-V FM bus address R17 1.8-V FM bus address P14 1.8-V FM bus address Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components MAX II CPLD EPM2210 System Controller 211 Table 26. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 5) Schematic Signal Name FM_A8 FM_A9 FM_A10 FM_A11 FM_A12 FM_A13 FM_A14 FM_A15 FM_A16 FM_A17 FM_A18 FM_A19 FM_A20 FM_A21 FM_A22 FM_A23 FM_A24 FM_A25 FM_A26 FM_D0 FM_D1 FM_D2 FM_D3 FM_D4 FM_D5 FM_D6 FM_D7 FM_D8 FM_D9 FM_D10 FM_D11 FM_D12 FM_D13 FM_D14 FM_D15 FMC_C2M_PG FMC_M2C_PG FMC_PRSNT FMC_SCL MAX II CPLD Pin Number I/O Standard Description R18 1.8-V FM bus address N15 1.8-V FM bus address P16 1.8-V FM bus address N14 1.8-V FM bus address P18 1.8-V FM bus address M15 1.8-V FM bus address N16 1.8-V FM bus address P17 1.8-V FM bus address N13 1.8-V FM bus address M14 1.8-V FM bus address N17 1.8-V FM bus address M13 1.8-V FM bus address N18 1.8-V FM bus address M12 1.8-V FM bus address M16 1.8-V FM bus address K14 1.8-V FM bus address K18 1.8-V FM bus address K15 1.8-V FM bus address H17 1.8-V FM bus address L16 1.8-V FM data bus M18 1.8-V FM data bus L14 1.8-V FM data bus L17 1.8-V FM data bus L13 1.8-V FM data bus L18 1.8-V FM data bus M17 1.8-V FM data bus L15 1.8-V FM data bus K16 1.8-V FM data bus K17 1.8-V FM data bus D15 1.8-V FM data bus C17 1.8-V FM data bus E15 1.8-V FM data bus C16 1.8-V FM data bus D16 1.8-V FM data bus E14 1.8-V FM data bus P6 2.5-V FMC card to module power good T4 2.5-V FMC module to card power good U3 2.5-V FMC module present R5 2.5-V FMC module clock November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 212 Chapter 2: Board Components MAX II CPLD EPM2210 System Controller Table 26. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 3 of 5) Schematic Signal Name FMC_SDA FPGA1_CEN FPGA1_CEON FPGA1_CONF_DONE FPGA1_CONFIG_D0 FPGA1_CONFIG_D1 FPGA1_CONFIG_D2 FPGA1_CONFIG_D3 FPGA1_CONFIG_D4 FPGA1_CONFIG_D5 FPGA1_CONFIG_D6 FPGA1_CONFIG_D7 FPGA1_CONFIG_D8 FPGA1_CONFIG_D9 FPGA1_CONFIG_D10 FPGA1_CONFIG_D11 FPGA1_CONFIG_D12 FPGA1_CONFIG_D13 FPGA1_CONFIG_D14 FPGA1_CONFIG_D15 FPGA1_CVP_CONFDONE FPGA1_MSEL0 FPGA1_MSEL1 FPGA1_MSEL2 FPGA1_MSEL3 FPGA1_MSEL4 FPGA1_NCONFIG FPGA1_NSTATUS FPGA1_PR_DONE FPGA1_PR_ERROR FPGA1_PR_READY FPGA1_PR_REQUEST FPGA2_CEN FPGA2_CEON FPGA2_CONF_DONE FPGA2_CVP_CONFDONE FPGA2_MSEL0 FPGA2_MSEL1 FPGA2_MSEL2 MAX II CPLD Pin Number I/O Standard Description V2 2.5-V FMC module data L1 2.5-V FPGA 1 chip enable F11 2.5-V FPGA 1 chip output enable M4 2.5-V FPGA 1 configuration done D1 2.5-V FPGA configuration data D3 2.5-V FPGA configuration data E2 2.5-V FPGA configuration data D4 2.5-V FPGA configuration data E1 2.5-V FPGA configuration data E3 2.5-V FPGA configuration data F3 2.5-V FPGA configuration data E4 2.5-V FPGA configuration data F2 2.5-V FPGA configuration data E5 2.5-V FPGA configuration data F1 2.5-V FPGA configuration data F4 2.5-V FPGA configuration data G3 2.5-V FPGA configuration data F5 2.5-V FPGA configuration data G2 2.5-V FPGA configuration data F6 2.5-V FPGA configuration data M1 2.5-V FPGA 1 configuration via protocol done F8 2.5-V FPGA 1 mode select 0 A6 2.5-V FPGA 1 mode select 1 E8 2.5-V FPGA 1 mode select 2 B7 2.5-V FPGA 1 mode select 3 D8 2.5-V FPGA 1 mode select 4 M5 2.5-V FPGA 1 configuration active N1 2.5-V FPGA 1 configuration ready K4 2.5-V FPGA 1 partial reconfiguration done L5 2.5-V FPGA 1 partial reconfiguration error L6 2.5-V FPGA 1 partial reconfiguration ready L2 2.5-V FPGA 1 partial reconfiguration request K5 2.5-V FPGA 2 chip enable C11 2.5-V FPGA 2 chip output enable M3 2.5-V FPGA 2 configuration done B18 2.5-V FPGA 2 configuration via protocol done U5 2.5-V FPGA 2 mode select 0 R7 2.5-V FPGA 2 mode select 1 V5 2.5-V FPGA 2 mode select 2 Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components MAX II CPLD EPM2210 System Controller 213 Table 26. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 4 of 5) Schematic Signal Name FPGA2_MSEL3 FPGA2_MSEL4 FPGA2_NCONFIG FPGA2_NSTATUS FPGA2_PR_DONE FPGA2_PR_ERROR FPGA2_PR_READY FPGA2_PR_REQUEST FPGA_DCLK HSMA_PRSNTN HSMB_PRSNTN INIT_DONE1 INIT_DONE2 JTAG_EPM2210_TDI JTAG_BLASTER_TDI JTAG_TCK JTAG_TMS M570_CLOCK M570_PCIE_JTAG_EN MAX_BEN0 MAX_BEN1 MAX_BEN2 MAX_BEN3 MAX_CLK MAX_CSN MAX_OEN MAX_WEN MAX_CONF_DONE1 MAX_CTL0 MAX_CTL1 MAX_CTL2 MAX_ERROR1 MAX_LOAD1 MAX_RESETN OVERTEMP1 OVERTEMP2 PGM1_CONFIG MAX II CPLD Pin Number I/O Standard Description T7 2.5-V FPGA 2 mode select 3 U6 2.5-V FPGA 2 mode select 4 M2 2.5-V FPGA 2 configuration active M6 2.5-V FPGA 2 configuration ready B16 2.5-V FPGA 2 partial reconfiguration done D14 2.5-V FPGA 2 partial reconfiguration error A17 2.5-V FPGA 2 partial reconfiguration ready E13 2.5-V FPGA 2 partial reconfiguration request N2 2.5-V FPGA configuration clock A14 2.5-V HSMC port A present E11 2.5-V HSMC port B present T6 2.5-V FPGA initialization done V4 2.5-V FPGA initialization done M7 2.5-V MAX II CPLD on-board JTAG chain data in N6 2.5-V MAX II CPLD on-board JTAG chain data out R4 2.5-V JTAG chain clock P5 2.5-V JTAG mode select A10 1.8-V 25-MHz clock to the on-board USB-Blaster II for sending FACTORY command D9 1.8-V Low signal to disable the on-board USB-Blaster II when the PCI Express acts as a master to the JTAG chain. B11 2.5-V FM bus MAX II byte enable 0 C10 2.5-V FM bus MAX II byte enable 1 A11 2.5-V FM bus MAX II byte enable 2 C9 2.5-V FM bus MAX II byte enable 3 J18 1.8-V FM bus MAX II clock J17 1.8-V FM bus MAX II chip select J15 1.8-V FM bus MAX II output enable J14 1.8-V FM bus MAX II write enable B3 2.5-V FPGA configuration done LED E10 2.5-V FPGA 1 to MAX II option A12 2.5-V FPGA 1 to MAX II option D10 2.5-V FPGA 1 to MAX II option C7 2.5-V FPGA 1 configuration error LED B6 2.5-V FPGA 1 configuration active LED E18 1.8-V MAX II reset push button B14 2.5-V FPGA 1 fan RPM control C12 2.5-V FPGA 2 fan RPM control B4 2.5-V Load the flash memory image identified by the PGM LEDs November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 214 Chapter 2: Board Components MAX II CPLD EPM2210 System Controller Table 26. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 5 of 5) Schematic Signal Name PGM1_LED0 PGM1_LED1 PGM1_LED2 PGM1_SEL PHASE0 SDI_A_RX_BYPASS SDI_A_RX_EN SDI_A_TX_EN SENSE_CS0N SENSE_CS1N SENSE_SCK SENSE_SDI SENSE_SDO SI570_EN SI571_EN USB_CFG0 USB_CFG1 USB_CFG2 USB_CFG3 USB_CFG4 USB_CFG5 USB_CFG6 USB_CFG7 USB_CFG8 USB_CFG9 USB_CFG10 USB_CFG11 USB_CLK VCCINT_SCL VCCINT_SDA MAX II CPLD Pin Number I/O Standard Description A4 2.5-V Flash memory PGM select indicator 0 F7 2.5-V Flash memory PGM select indicator 1 C5 2.5-V Flash memory PGM select indicator 2 D6 2.5-V Toggles the PGM_LED[0:2] LED sequence P8 2.5-V LTM4601 phase control A8 2.5-V SDI equalization bypass E9 2.5-V SDI receive enable F9 2.5-V SDI transmit enable F12 2.5-V Power monitor chip select B15 2.5-V Power monitor chip select E12 2.5-V Power monitor SPI clock A15 2.5-V Power monitor SPI data in D12 2.5-V Power monitor SPI data out A13 2.5-V Si570 programmable oscillator enable C13 2.5-V Si571 programmable VCXO enable H14 1.8-V On-board USB-Blaster II data H13 1.8-V On-board USB-Blaster II data G13 1.8-V On-board USB-Blaster II data F17 1.8-V On-board USB-Blaster II data G12 1.8-V On-board USB-Blaster II data F18 1.8-V On-board USB-Blaster II data H16 1.8-V On-board USB-Blaster II data G16 1.8-V On-board USB-Blaster II data H15 1.8-V On-board USB-Blaster II data G17 1.8-V On-board USB-Blaster II data G14 1.8-V On-board USB-Blaster II data G18 1.8-V On-board USB-Blaster II data J6 2.5-V On-board USB-Blaster II clock R3 2.5-V LTC3880 serial clock R2 2.5-V LTC3880 serial data Table 27 lists the MAX II CPLD EPM2210 System Controller component reference and manufacturing information. Table 27. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website U2 IC - MAX II CPLD EPM2210 324FBGA -3 LF 1.8V VCCINT Altera Corporation EPM2210F324 www.altera.com Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components Configuration, Status, and Setup Elements 215 Configuration, Status, and Setup Elements This section describes the board's configuration, status, and setup elements. Configuration This section describes the FPGA, flash memory, and MAX II CPLD EPM2210 System Controller device programming methods supported by the Arria V GX FPGA development board. The Arria V GX FPGA development board supports the following three configuration methods: On-board USB-Blaster II is the default method for configuring the FPGA at any time using the Quartus II Programmer in JTAG mode with the supplied USB cable. External USB-Blaster for configuring the FPGA using an external USB-Blaster that connects to the JTAG programming header (J1). Flash memory download for configuring the FPGA using stored images from the flash memory on either power-up or pressing the program configuration push button, PGM1_CONFIG (S3). FPGA Programming over On-Board USB-Blaster II This configuration method implements a USB Type-AB connector (J7), a FTDI USB 2.0 PHY device (U5), and an Altera MAX II CPLD (U2) to allow the FPGA configuration using a USB cable that connects directly between the USB port on the board and a USB port of a PC running the Quartus II software. The on-board USB-Blaster II in the MAX II CPLD EPM570GM100 normally masters the JTAG chain. To prevent contention between the JTAG masters, the on-board USB-Blaster II is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG connector. If the USB-Blaster II is detected but no hardware is found in the chain, try reducing the clock frequency of the JTAG chain using these commands: To check the current setting: jtagconfig --getparam <cable-no> JtagClock To set a new setting (example clock frequency = 6 M): jtagconfig --setparam <cable-no> JtagClock 6M Only 6 M, 16 M, and 24 M clock frequency options are available. Insert a value of 1 for <cable-no> if this is the only JTAG cable you attach to the board. 1 Installing daughtercards such as HSMC or FMC can affect performance and requires a lower speed. November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 216 Chapter 2: Board Components Configuration, Status, and Setup Elements Figure 24 illustrates the JTAG chain. Figure 24. JTAG Chain DISABLE 10-pin JTAG Header GPIO GPIO TCK Cypress GPIO TMS On-Board GPIO TDO USB-Blaster II TDI JTAG Master 2.5V TCK TMS Arria V TDI (FPGA 1) TDO JTAG Slave ALWAYS ENABLED (in-chain) TCK TMS Arria V TDI (FPGA 2) TDO JTAG Slave ALWAYS ENABLED (in-chain) ENABLE Analog Switch TCK TMS HSMC TDI Port A TDO 2.5V JTAG Slave Installed HSMC Card ENABLE DIP switch Analog Switch ENABLE DIP switch Analog Switch TCK TMS HSMC TDI Port B TDO 2.5V JTAG Slave TCK TMS FMC Port TDI TDO JTAG Slave Installed HSMC Card Installed FMC Card TCK TMS MAX II CPLD System TDI Controller TDO JTAG Slave ALWAYS ENABLED (in-chain) Each jumper shown in Figure 24 is located in the JTAG chain DIP switch (SW6) on the back of the board. To connect a device or interface in the chain, you must set the corresponding switch from the JTAG chain DIP switch (SW6). The interface in the JTAG chain depends on the switch settings but the FPGAs and MAX II devices are always in the JTAG chain. Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Configuration, Status, and Setup Elements 217 Flash Memory Programming Flash memory programming is possible through a variety of methods. The default method is to use the factory design--Board Update Portal (BUP). This design is an embedded webserver, which serves the BUP web page. The web page allows you to select new FPGA designs including hardware, software, or both in an industry-standard S-Record File (.flash) and write the design to the user hardware page (page 1) of the flash memory over the network. The secondary method is to use the pre-built parallel flash loader (PFL) design included in the development kit. The development board implements the Altera PFL megafunction for flash memory programming. The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible flash memory device. This pre-built design contains the PFL megafunction that allows you to write either page 0, page 1, or other areas of flash memory over the USB interface using the Quartus II software. This method is used to restore the development board to its factory default settings. Other methods to program the flash memory can be used as well, including the Nios® II processor. f For more information on the Nios II processor, refer to the Nios II Processor page of the Altera website. FPGA Programming from Flash Memory On either power-up or by pressing the program configuration push button, PGM1_CONFIG (S3), the MAX II CPLD EPM2210 System Controller's PFL configures the FPGA from the flash memory when the PGM1_LED[2:0] are ON. The PFL megafunction reads 16-bit data from the flash memory and converts it to fast passive parallel (FPP) format. This 8-bit data is then written to the FPGA's dedicated configuration pins during configuration. November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 218 Chapter 2: Board Components Configuration, Status, and Setup Elements Figure 25 shows the PFL configuration. Figure 25. PFL Configuration DIP Switch DIP Switch 2.5 V 2.5 V 56.2 100 2.5 V 56.2 MAX II CPLD EPM2210 System Controller MAX_ERROR1 MAX_LOAD1 MAX_CONF_DONE1 FPGA_INIT_DONE FPGA_nSTATUS FPGA_nCONFIG CLK_SEL FPGA_CONF_DONE CLK_ENABLE FACTORY1 FACTORY2 CONF_DONE FPGA_DATA [7:0] MAX_RESETn FPGA_DCLK FLASH_A [26:1] PGM1_CONFIG FLASH_D [15:0] FLASH_CEn PGM1_SEL FLASH_OEn FLASH_WEn FLASH_RYBSYn PGM1_LED0 FLASH_CLK PGM1_LED1 FLASH_RSTn PGM1_LED2 FLASH_ADVn CFI Flash FLASH_A [26:0] FLASH_D [15:0] FLASH_CEn FLASH_OEn FLASH_WEn FLASH_RYBSYn FLASH_CLK FLASH_RESETn FLASH_WPn FLASH_ADVn 50 MHz 100 MHz 2.5 V 2.5 V 56.2 10 k CONF_DONE_LED Arria V FPGA INIT_DONE nSTATUS nCONFIG CONF_DONE nCE MSEL[4:0] also goes to MAX II CPLD MSEL4 MSEL2 MSEL1 MSEL3 MSEL0 1 k PS Port DATA [7:0] DCLK Flash Interface 1.8 V 10 k 10 k f For information on the flash memory map storage, refer to the refer to the Arria V GX FPGA Development Kit, User Guide. There are two pages reserved for the FPGA configuration data. The factory hardware page--page 0--loads upon power-up when the Factory1 DIP switch (SW5.3) is set to '1'. Otherwise, the user hardware page 1 loads. Pressing the PGM1_CONFIG push button (S3) loads the FPGA with a hardware page based on which PGM1_LED[2:0] LED (D12, D13, D14) illuminates. Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components Configuration, Status, and Setup Elements 219 Table 28 defines the hardware page that loads when you press the PGM1_CONFIG push button (S3). Table 28. PGM1_LED Settings PGM1_LED0 ON OFF OFF PGM1_LED1 OFF ON OFF PGM1_LED2 OFF OFF ON Design Factory hardware User design 1 User design 2 FPGA Programming over External USB-Blaster The JTAG programming header provides another method for configuring the FPGA using an external USB-Blaster device with the Quartus II Programmer running on a PC. The external USB-Blaster connects to the board through the JTAG connector (J5). Both FPGAs and the MAX II devices are always in the JTAG chain. f For more information on the following topics, refer to the respective documents: Board Update Portal and PFL design, refer to the Arria V GX FPGA Development Kit, User Guide. PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide. Status Elements The development board includes status LEDs. This section describes the status elements. Table 29 lists the LED board references, names, and functional descriptions. Table 29. Board-Specific LEDs (Part 1 of 2) Board Reference D1 Schematic Signal Name Power Arria V GX FPGA Pin Number -- D16 MAX_CONF_DONE1 -- D17 MAX_LOAD1 -- D15 MAX_ERROR1 -- D12, D13, D14 PGM1_LED[2:0] -- I/O Standard 5.0-V 2.5-V 2.5-V 2.5-V 2.5-V Description Blue LED. Illuminates when 5.0 V power is active. Green LED. Illuminates when the MAX II CPLD EPM2210 System Controller is successfully configured. Driven by the MAX II CPLD EPM2210 System Controller. Green LED. Illuminates when the MAX II CPLD EPM2210 System Controller is actively configuring the FPGA. Driven by the MAX II CPLD EPM2210 System Controller wire-OR'd with the on-board USB-Blaster II CPLD. Red LED. Illuminates when the MAX II CPLD EPM2210 System Controller fails to configure the FPGA. Driven by the MAX II CPLD EPM2210 System Controller. Green LEDs. Illuminates to indicate which hardware page loads from flash memory when you press the PGM1_SEL push button or when you power-on the board. November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 220 Chapter 2: Board Components Configuration, Status, and Setup Elements Table 29. Board-Specific LEDs (Part 2 of 2) Board Reference Schematic Signal Arria V GX FPGA Name Pin Number D34 DEVICE1_LED -- D35 DEVICE2_LED -- D36 ENET_LED_TX -- D37 ENET_LED_RX -- D40 ENET_LED_LINK10 -- D38 ENET_LED_LINK100 -- D39 ENET_LED_LINK1000 D4 HSMA_RX_LED D5 HSMA_TX_LED D6 HSMA_PRSNTn D7 HSMB_RX_LED D8 HSMB_TX_LED D9 HSMB_PRSNTn D44 PCIE_LED_X1 D43 PCIE_LED_X4 D42 PCIE_LED_X8 AN17 AT15 AH14 AW15 AG26 AM28 AT24 AC18 AD17 AT16 I/O Standard 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 3.3-V 2.5-V 2.5-V 3.3-V 2.5-V 2.5-V 2.5-V Description Green LED. Illuminates when FPGA 1 is successfully configured. Driven by the MAX II CPLD EPM2210 System Controller. Green LED. Illuminates when FPGA 2 is successfully configured. Driven by the MAX II CPLD EPM2210 System Controller. Green LED. Illuminates to indicate Ethernet PHY transmit activity. Driven by the Marvell 88E1111 PHY. Green LED. Illuminates to indicate Ethernet PHY receive activity. Driven by the Marvell 88E1111 PHY. Green LED. Illuminates to indicate Ethernet linked at 10 Mbps connection speed. Driven by the Marvell 88E1111 PHY. Green LED. Illuminates to indicate Ethernet linked at 100 Mbps connection speed. Driven by the Marvell 88E1111 PHY. Green LED. Illuminates to indicate Ethernet linked at 1000 Mbps connection speed. Driven by the Marvell 88E1111 PHY. Green LED. Illuminates to indicate HSMA port A receive data activity. Green LED. Illuminates to indicate HSMA port A transmit data activity. Green LED. Illuminates when HSMC port A has a board or cable plugged-in such that pin 160 becomes grounded. Driven by the add-in card. Green LED. Illuminates to indicate HSMA port B receive data activity. Green LED. Illuminates to indicate HSMA port B transmit data activity. Green LED. Illuminates when HSMC port B has a board or cable plugged-in such that pin 160 becomes grounded. Driven by the add-in card. Yellow LED. Configure this LED to display the PCI Express link width x1. Yellow LED. Configure this LED to display the PCI Express link width x4. Yellow LED. Configure this LED to display the PCI Express link width x8. Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components Configuration, Status, and Setup Elements 221 Table 210 lists the board-specific LEDs component references and manufacturing information. Table 210. Board-Specific LEDs Component References and Manufacturing Information Board Reference Description D2D12, D14D17, D34D40, D45 Green LEDs D42, D43, D44 Yellow LEDs D18D33 Bi color Red/Green LEDs D13 Red LED D1 Blue LED Manufacturer Lumex Inc. Lumex Inc. Lite-On Lumex Inc. Lumex Inc. Manufacturer Part Number SML-LXT0805GW-TR SML-LXT0805YW-TR LTST-C195KGJRKT SML-LXT0805IW-TR SML-LX0805USBC-TR Manufacturer Website www.lumex.com www.lumex.com www.lite-on.com www.lumex.com www.lumex.com Setup Elements The development board includes several different kinds of setup elements. This section describes the following setup elements: Board settings DIP switch JTAG chain header switch PCI Express control DIP switch CPU reset push button MAX II reset push button Configuration push button Image select push button Board Settings DIP Switch The board settings DIP switch (SW5) controls various features specific to the board and the MAX II CPLD EPM2210 System Controller logic design. Table 211 lists the switch controls and descriptions. Table 211. Board Settings DIP Switch Controls Switch Schematic Signal Name Description 1 CLK_SEL 2 CLK_ENABLE 3 FACTORY_USER1 4 FACTORY_USER2 ON : 100 MHz clock select OFF : SMA input clock select ON : On-board oscillators enable OFF : On-board oscillators disable ON : Load the factory design from flash for Arria V FPGA 1 at power up. OFF : Load the user design from flash at power up. Unused Default OFF ON ON OFF November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 222 Chapter 2: Board Components Configuration, Status, and Setup Elements Table 212 lists the board settings DIP switch component reference and manufacturing information. Table 212. Board Settings DIP Switch Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website SW5 Four-position DIP switch C&K Components/ ITT Industries TDA04H0SB1 www.ittcannon.com JTAG Settings DIP Switch The JTAG settings DIP switch (SW6) either remove or include devices in the active JTAG chain. However, the Arria V GX FPGA 1 is always in the JTAG chain. Table 213 lists the switch controls and its descriptions. Table 213. JTAG Chain Header Switch Controls Switch Schematic Signal Name Description 1 HSMA_JTAG_EN 2 HSMB_JTAG_EN 3 FMC_JTAG_EN 4 NC ON : Bypass HSMA OFF : HSMA in-chain ON : Bypass HSMB OFF : HSMB in-chain ON : Bypass FMC connector OFF : FMC connector in-chain Unused Default ON ON ON OFF Table 214 lists the JTAG chain header switch component reference and manufacturing information. Table 214. JTAG Chain Header Switch Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website SW6 Four-position DIP switch C&K Components/ ITT Industries TDA04H0SB1 www.ittcannon.com PCI Express Control DIP Switch The PCI Express control DIP switch (SW7) is provided to enable or disable different configurations. Table 215 lists the switch controls and descriptions. Table 215. PCI Express Control DIP Switch Controls (Part 1 of 2) Switch Schematic Signal Name Description 1 PCIE_PRSNT2n_x1 2 PCIE_PRSNT2n_x4 ON : Enable x1 presence detect OFF : Disable x1 presence detect ON : Enable x4 presence detect OFF : Disable x4 presence detect Default ON ON Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components Configuration, Status, and Setup Elements 223 Table 215. PCI Express Control DIP Switch Controls (Part 2 of 2) Switch Schematic Signal Name Description 3 PCIE_PRSNT2n_x8 4 NC ON : Enable x8 presence detect OFF : Disable x8 presence detect Unused Default ON OFF Table 216 lists the PCI Express control DIP switch component reference and manufacturing information. Table 216. PCI Express Control DIP Switch Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website SW7 Four-position DIP switch C&K Components/ ITT Industries TDA04H0SB1 www.ittcannon.com CPU Reset Push Button Each Arria V GX FPGA has a CPU reset push button, CPU1_RESETn (S4) for FPGA 1 and CPU2_RESETn (S8) for FPGA 2. Both these push button are inputs to the Arria V GX FPGA DEV_CLRn pin and are open-drain I/Os from the MAX II CPLD System Controller. The push button is the default reset for both the FPGA and CPLD logic. The MAX II System Controller also drives these push button during POR. 1 You must enable the CPU_RESETn signal within the Quartus II software for this reset function to work. Otherwise, the CPU_RESETn acts as a regular I/O pin. When you enable the signal in the Quartus II software, and then pull high on the board, every register within the FPGA resets to a low signal. Table 217 lists the CPU reset push button component reference and manufacturing information. Table 217. CPU Reset Configuration Push Button Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website S4, S8 Push button Dawning Precision Co., Ltd. TS-A02SA-2-S100 www.dawning2.com.tw MAX II Reset Push Button The MAX II reset push button, MAX_RESETn, is an input to the MAX II CPLD System Controller. This push button is the default reset for the CPLD logic. Table 219 lists the MAX II reset push button component reference and manufacturing information. Table 218. MAX II Reset Push Button Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website S1 Push button Dawning Precision Co., Ltd. TS-A02SA-2-S100 www.dawning2.com.tw November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 224 Chapter 2: Board Components Clock Circuitry Configuration Push Button The configuration push button, PGM1_CONFIG (S3), is an input to the MAX II CPLD EPM2210 System Controller. The push button forces a reconfiguration of the FPGA from flash memory. The location in the flash memory is based on the settings of the PGM1_LED[2:0], which is controlled by the image select push button, PGM1_SEL (S2). Valid settings include PGM1_LED0, PGM1_LED1, or PGM1_LED2 on the three pages in flash memory reserved for FPGA designs. Table 219 lists the configuration push button component reference and manufacturing information. Table 219. Configuration Push Button Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website S3 Push button Dawning Precision Co. TS-A02SA-2-S100 www.dawning2.com.tw Image Select Push Button The program select push button, PGM1_SEL (S2), is an input to the MAX II CPLD System Controller. The push button toggles the PGM1_LED[2:0]sequence that selects which location in the flash memory is used to configure the FPGA. Refer to Table 28 for the PGM1_LED[2:0] sequence definitions. Table 220 lists the image select push button component reference and manufacturing information. Table 220. Image Select Push Button Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website S2 Push button Dawning Precision Co., Ltd. TS-A02SA-2-S100 www.dawning2.com.tw Clock Circuitry This section describes the board's clock inputs and outputs. On-Board Oscillators The development board includes fixed and programmable oscillators with a frequency of 50-MHz, 100-MHz, 125-MHz, 148.5-MHz, 156.25-MHz, and 625-MHz. Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components Clock Circuitry 225 Figure 26 shows the default frequencies of all external clocks going to the Arria V GX FPGA development board. Figure 26. Arria V GX FPGA Development Board Clocks SMA SMA REFCLK INPUT X6 50 MHz X7 S i5 7 0 100 MHz Default U51 B u ffe r 50 MHz U56 B u ffe r 100 MHz Default 50 MHz CLKIN_M AX_50 100 MHz 125 MHz 50 MHz CLK0 CLKA_125_P/N C LK 5p C LK IN A _50 CLK7 CLKINBOTA_P/N[1] CLK6 CLKINBOTA_P/N[0] U53 CLK3 125 MHz CLK2 125 MHz S i5 3 8 8 CLK1 156.25 MHz CLK0 625 MHz 100 MHz 125 MHz R E F C L K 1 A _ Q L 0 _ P /N (P C Ie ) P C IE _ R E F _ C L K _ P /N R E F C L K 3 _ A _ Q L 1 _ P /N (SFP+) R E F C L K 2 _ A _ Q L 1 _ P /N (SFP+) R E F C L K 4 _ A _ Q L 2 _ P /N (SFP+) U25 J16 Clock Buffer 1:2 156.25 MHz Bullseye Connector U16 QL0 B3 QL1 B8 QL2 QR0 B4 QR1 B7 QR2 125 MHz R E F C L K 0 _ A _ Q R 0 _ P /N (C 2 C ) R E F C L K 2 _ A _ Q R 1 _ P /N (C2C, HSMA) R E F C L K 4 _ A _ Q R 2 _ P /N (H S M A ) 125 MHz 625 MHz 100 MHz 125 MHz U48 CLK3 CLK2 S i5 3 8 8 CLK1 CLK0 CLKINTOPA_P/N[0] CLK19 CLKINTOPA_P/N[1] CLK17 100 MHz 100 MHz 125 MHz 125 MHz CLK0p CLKINB_50 CLK6 CLKB_125_P/N CLK7 CLKINBOTB_P/N[1] C LK 11 C LK IN B O T B _P /N [0] 50 MHz 100 MHz U34 CLK3 125 MHz CLK2 625 MHz S i5 3 8 8 CLK1 100 MHz CLK0 625 MHz R E F C L K 1 _ B _ Q L 0 _ P /N R E F C L K 0 _ B _ Q L 0 _ P /N (C 2 C ) R E F C L K 2 _ B _ Q L 1 _ P /N (C 2 C ) R E F C L K 4 _ B _ Q L 2 _ P /N (C 2 C ) U13 QL0 B3 QL1 B8 QL2 QR0 B4 QR1 B7 QR2 U53 SDI (148.5 M/148.35 M) S i5 7 1 148.5 MHz Default RE F C L K 0 _ B _ Q R 0 _ P /N (HSM B, SDI) R E F C L K 1 _ B _ Q R 0 _ P /N (HSM B, SDI) R E F C L K 2 _ B _ Q R 1 _ P /N (F M C ) R E F C L K 3 _ B _ Q R 2 _ P /N (F M C ) 125 MHz 156.25 MHz 100 MHz U52 CLK3 CLK2 S i5 3 8 8 CLK1 125 MHz CLK0 100 MHz 125 MHz CLKINTOPB_P/N[0] CLK20 CLKINTOPB_P/N[1] CLK15 November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 226 Chapter 2: Board Components Clock Circuitry Table 221 lists the oscillators, its I/O standard, and voltages required for the development board. Table 221. On-Board Oscillators Source Schematic Signal Name X6 to U51 1:3 clock buffer X3 CLKIN_MAX_50 CLKINA_50 CLKINB_50 CLK_CONFIG REFCLK1_A_QL0_P REFCLK1_A_QL0_N CLKINBOTA_P0 CLKINBOTA_N0 X7 to U56 1:6 CLKINTOPA_P0 clock buffer CLKINTOPA_N0 CLKINBOTB_P0 CLKINBOTB_N0 CLKINTOPB_P0 CLKINTOPB_N0 CLKA_125_P X1 CLKA_125_N CLKB_125_P X4 CLKB_125_N REFCLK0_QR0_P X2 REFCLK0_QL2_N REFCLK4_A_QL2_P REFCLK4_A_QL2_N REFCLK3_A_BUF_P REFCLK3_A_BUF_N U53 REFCLK2_A_QL1_P REFCLK2_A_QL1_N CLKINBOTA_P1 CLKINBOTA_N1 REFCLK4_A_QR2_P REFCLK4_A_QR2_N REFCLK2_A_QR1_P REFCLK2_A_QR1_N U48 REFCLK0_A_QR0_P REFCLK0_A_QR0_N CLKINTOPA_P1 CLKINTOPA_N1 Frequency 50.000 MHz 100.000 MHz 100.000 MHz 125.000 MHz 125.000 MHz 148.500 MHz 625.000 MHz 156.250 MHz 125.000 MHz 125.000 MHz 125.000 MHz 100.000 MHz 625.000 MHz 125.000 MHz I/O Standard 1.8-V 1.8-V 1.8-V 2.5-V CMOS LVDS (fanout buffer) LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS Arria V GX FPGA Pin Number -- AF21 AP34 -- AE31 AE32 AD20 AC21 C20 D20 AK7 AJ7 C34 D34 AP34 AN34 AD20 AC21 -- -- W31 W32 -- -- U31 U32 AL20 AK20 T9 T8 AB9 AB8 AF8 AF7 A22 A21 Application Nios II and MAX II CPLD Fast FPGA configuration PCI Express host/dual-XTL Bottom edge FPGA 1 QDRII+ Top edge FPGA 1 DDR3 Bottom edge FPGA 2 Top edge FPGA 2 DDR3 Fixed clock at 125 MHz for FPGA 1 bank 3A Fixed clock at 125 MHz for FPGA 1 bank 3D HD-SDI video SFP+ SFP+, Bull's Eye connector, 1:2 clock to REFCLK3 on FPGA 1, Bottom edge FPGA 1 memory HSMC port A, C2C C2C Top edge FPGA 1 memory Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Clock Circuitry 227 Table 221. On-Board Oscillators Source Schematic Signal Name Frequency REFCLK4_B_QL2_P REFCLK4_B_QL2_N 625.000 MHz REFCLK2_B_QL1_P 100.000 MHz REFCLK2_B_QL1_N U34 REFCLK0_B_QL0_P 625.000 MHz REFCLK0_B_QL0_N CLKINBOTB_P1 CLKINBOTB_N1 125.000 MHz REFCLK3_B_QR2_P REFCLK3_B_QR2_N 125.000 MHz REFCLK2_B_QR1_P 100.000 MHz REFCLK2_B_QR1_N U52 REFCLK1_B_QR0_P 156.250 MHz REFCLK1_B_QR0_N CLKINTOPB_P1 CLKINTOPB_N1 125.000 MHz I/O Standard LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS Arria V GX FPGA Pin Number U31 U32 AC31 AC32 AG32 AG33 AL20 AK20 T9 T8 Y9 Y8 AD9 AD8 H6 J6 Application C2C C2C C2C Bottom edge FPGA 2 memory FMC FMC HSMC port B, SDI Top edge FPGA 2 Off-Board Clock Input/Output The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device's specification. Table 222 lists the clock inputs for the development board. Table 222. Off-Board Clock Inputs Source Schematic Signal Name CLKIN_SMA_P SMA CLKIN_SMA_N HSMC HSMC HSMC HSMC HSMA_CLK_IN0 HSMA_CLK_IN_P1 HSMA_CLK_IN_N1 HSMA_CLK_IN_P2 HSMA_CLK_IN_N2 HSMB_CLK_IN0 HSMC HSMB_CLK_IN_P1 HSMB_CLK_IN_N1 I/O Standard LVPECL LVPECL 2.5-V LVDS/2.5-V LVDS/LVTTL LVDS/LVTTL LVDS/LVTTL 2.5-V LVDS/LVTTL LVDS/LVTTL Arria V GX FPGA Pin Number Description -- Input to LVDS fan-out buffer (drives one REFCLK, one clock on the top edge and one on the bottom -- edge of each FPGA) AT7 Single-ended input from the installed HSMC cable or board. AW4 LVDS input from the installed HSMC cable or AV4 board. Can also support 2x LVTTL inputs. AR6 LVDS input from the installed HSMC cable or AP6 board. Can also support 2x LVTTL inputs. AR6 Single-ended input from the installed HSMC cable or board. AM33 AL33 LVDS input from the installed HSMC cable or board. Can also support 2x LVTTL inputs. November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 228 Chapter 2: Board Components Clock Circuitry Table 222. Off-Board Clock Inputs Source Schematic Signal Name HSMC PCI Express Edge FMC HSMB_CLK_IN_P2 HSMB_CLK_IN_N2 PCIE_REFCLK_P PCIE_REFCLK_N FMC_REFCLK_P0 FMC_REFCLK_P1 FMC_REFCLK_N0 FMC_REFCLK_N1 FMC_CLK_M2C_P0 FMC_CLK_M2C_P1 FMC_CLK_M2C_N0 FMC_CLK_M2C_N0 I/O Standard LVDS/LVTTL LVDS/LVTTL LVDS/LVTTL HCSL LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS Arria V GX FPGA Pin Number AU32 AT32 AG32 AG33 AB9 V9 AB8 V8 AV19 AF21 AU19 AE21 Description LVDS input from the installed HSMC cable or board. Can also support 2x LVTTL inputs. LVDS input from the PCI Express edge connector. LVDS input from the FMC board (drives two REFCLKs on FPGA 2) LVDS input from the FMC board. Table 223 lists the clock outputs for the development board. Table 223. Off-Board Clock Outputs Source Schematic Signal Name I/O Standard HSMC HSMC HSMC HSMC HSMC HSMC HSMA_CLK_OUT0 HSMA_CLK_OUT_P1 HSMA_CLK_OUT_N1 HSMA_CLK_OUT_P2 HSMA_CLK_OUT_N2 HSMB_CLK_OUT0 HSMB_CLK_OUT_P1 HSMB_CLK_OUT_N1 HSMB_CLK_OUT_P2 HSMB_CLK_OUT_N2 2.5V CMOS LVDS/2.5V CMOS LVDS/2.5V CMOS LVDS/2.5V CMOS LVDS/2.5V CMOS 2.5V CMOS LVDS/2.5V CMOS LVDS/2.5V CMOS LVDS/2.5V CMOS LVDS/2.5V CMOS Arria V GX FPGA Pin Number AL14 AU13 AT13 AM7 AL7 AJ33 AM33 AL34 AU32 AD26 Description FPGA CMOS output (or GPIO) LVDS output. Can also support 2x CMOS outputs. LVDS output. Can also support 2x CMOS outputs. FPGA CMOS output (or GPIO) LVDS output. Can also support 2x CMOS outputs. LVDS output. Can also support 2x CMOS outputs. Table 224 lists the crystal oscillators component references and manufacturing information. Table 224. Crystal Oscillator Component References and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website X1, X4 125.000-MHz LVDS saw clock oscillator X5 25-MHz oscillator Y3 24-MHz crystal oscillator Y1, Y2, Y4, Y5 25-MHz crystal oscillator Epson Epson Epson Epson EG-2121CA 125.0000MLGPNL3 SG-310SDF 25.0000M-B3 FA-128 24.0000MB-W FA-128 25.0000MB-C www.eea.epson.com www.eea.epson.com www.eea.epson.com www.eea.epson.com Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components General User Input/Output 229 Table 224. Crystal Oscillator Component References and Manufacturing Information Board Reference X6 U34, U48, U53, U52 Description 50-MHz oscillator Quad output programmable clock generator X7 100-MHz single output programmable oscillator X2 148.5-MHz single output programmable VCXO X7 100 MHz crystal oscillator Manufacturer Manufacturer Part Number Manufacturer Website ECS Inc. ECS-3518-500-B-xx www.ecsxtal.com Si5338A-A01316-GM, Silicon Labs Inc. Si5338A-A01317-GM, Si5338A-A01318-GM, Si5338A-A01319-GM www.silabs.com Silicon Labs Inc. 570FAB000433DG www.silabs.com Silicon Labs Inc. 571FDB000159DG ECS Inc. ECS-3525-1000-B-TR www.silabs.com www.ecsxtal.com General User Input/Output This section describes the user I/O interface to the FPGA, including the push buttons, DIP switches, status LEDs, character LCD, and SDI video output/input port. User-Defined Push Buttons The development board includes three user-defined push buttons for each FPGA device. For information on the system and safe reset push buttons, refer to "Setup Elements" on page 221. Board references S5, S6, and S7 are push buttons that allow you to interact with the Arria V GX FPGA 1 while S9, S10, and S11 are for use with the Arria V GX FPGA 2. When you press and hold down the button, the device pin is set to logic 0; when you release the button, the device pin is set to logic 1. There are no board-specific functions for these general user push buttons. Table 225 lists the user-defined push button schematic signal names and their corresponding Arria V GX FPGA device pin numbers. Table 225. User-Defined Push Button Schematic Signal Names and Functions Board Reference Schematic Signal Name Arria V GX FPGA Pin Number I/O Standard S6 USER1_PB0 U16.T19 2.5-V S5 USER1_PB1 U16.R19 2.5-V S4 USER1_PB2 U16.F18 2.5-V S11 USER2_PB0 U13.D6 2.5-V S10 USER2_PB1 U13.C6 2.5-V S9 USER2_PB2 U13.K7 2.5-V Description User-defined push buttons for FPGA 1. User-defined push buttons for FPGA 2. November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 230 Chapter 2: Board Components General User Input/Output Table 226 lists the user-defined push button component reference and the manufacturing information. Table 226. User-defined Push Button Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website S4S6, S9S11 Push button Dawning Precision Co. TS-A02SA-2-S100 www.dawning2.com.tw User-Defined DIP Switches Board references SW2 and SW3 are two sets of eight-pin DIP switches. There are no board-specific functions for these switches. Each of the Arria V GX FPGA have a set of user-defined DIP switch. When the switch is in the OFF position, a logic 1 is selected. When the switch is in the ON position, a logic 0 is selected. Table 227 lists the user-defined DIP switch schematic signal names and their corresponding Arria V GX FPGA pin numbers. Table 227. User-defined DIP Switch Schematic Signal Names and Functions Board Reference Schematic Signal Name SW2.1 USER1_DIPSW0 SW2.2 USER1_DIPSW1 SW2.3 USER1_DIPSW2 SW2.4 USER1_DIPSW3 SW2.5 USER1_DIPSW4 SW2.6 USER1_DIPSW5 SW2.7 USER1_DIPSW6 SW2.8 USER1_DIPSW7 SW3.1 USER2_DIPSW0 SW3.2 USER2_DIPSW1 SW3.3 USER2_DIPSW2 SW3.4 USER2_DIPSW3 SW3.5 USER2_DIPSW4 SW3.6 USER2_DIPSW5 SW3.7 USER2_DIPSW6 SW3.8 USER2_DIPSW7 Arria V GX FPGA Pin Number P18 N18 C16 B16 G17 F17 D17 C17 C8 D8 E7 E6 G8 F8 D15 G11 I/O Standard Description 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V User-defined DIP switch that connects to FPGA 1. User-defined DIP switch that connects to FPGA 2. Table 228 lists the user-defined DIP switch component reference and the manufacturing information. Table 228. User-defined DIP Switch Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number SW2, SW3 Eight-position DIP switch C&K Components/ ITT Industries TDA08H0SB1 Manufacturer Website www.ittcannon.com Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components General User Input/Output 231 User-Defined LEDs The development board includes general and user-defined LEDs. This section describes all user-defined LEDs. For information on board specific or status LEDs, refer to "Status Elements" on page 219. General User-Defined LEDs Board references D18 through D25 and D26 through D33 are two sets of eight pairs user-defined LEDs. Each of the Arria V GX FPGA have a set of user-defined LEDs. The LEDs illuminate when a logic 0 is driven, and turns off when a logic 1 is driven. There are no board-specific functions for these LEDs. Table 229 lists the user-defined LED schematic signal names and their corresponding Arria V GX FPGA pin numbers. Table 229. User-Defined LED Schematic Signal Names and Functions Board Reference D25 D24 D23 D22 D21 D20 D19 D18 Schematic Signal Name USER1_LED_G0 USER1_LED_R0 USER1_LED_G1 USER1_LED_R1 USER1_LED_G2 USER1_LED_R2 USER1_LED_G3 USER1_LED_R3 USER1_LED_G4 USER1_LED_R4 USER1_LED_G5 USER1_LED_R5 USER1_LED_G6 USER1_LED_R6 USER1_LED_G7 USER1_LED_R7 Arria V GX FPGA Pin Number U16.C15 U16.AL15 U16.R18 U16.AC15 U16.F11 U16.AD14 U16.AP11 U16.AN8 U16.AU14 U16.AP8 U16.AE16 U16.AK14 U16.AF15 U16.AG14 U16.AK15 U16.AH15 I/O Standard Description 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V User-defined LEDs for FPGA 1. November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 232 Chapter 2: Board Components General User Input/Output Table 229. User-Defined LED Schematic Signal Names and Functions Board Reference D33 D32 D31 D30 D29 D28 D27 D26 Schematic Signal Name USER2_LED_G0 USER2_LED_R0 USER2_LED_G1 USER2_LED_R1 USER2_LED_G2 USER2_LED_R2 USER2_LED_G3 USER2_LED_R3 USER2_LED_G4 USER2_LED_R4 USER2_LED_G5 USER2_LED_R5 USER2_LED_G6 USER2_LED_R6 USER2_LED_G7 USER2_LED_R7 Arria V GX FPGA Pin Number U13.M19 U13.N20 U13.L19 U13.C15 U13.K19 U13.AL28 U13.J19 U13.F11 U13.K20 U13.AJ31 U13.J20 U13.AN34 U13.T20 U13.AJ34 U13.R20 U13.AK33 I/O Standard Description 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V 2.5-V User-defined LEDs for FPGA 2. Table 230 lists the user-defined LED component reference and the manufacturing information. Table 230. User-Defined LED Component Reference and Manufacturing Information Board Reference Device Description Manufacturer Manufacturer Part Number Manufacturer Website D18D25, D26D33 Bi-color red and green LEDs Lite-On LTST-C195GEKT www.us.liteon.com/opto.index.html HSMC User-Defined LEDs Each HSMC port has two LEDs located nearby. There are no board-specific functions for the HSMC LEDs. The LEDs are labeled TX and RX, and are intended to display data flow to and from the connected HSMC daughtercards. The LEDs are driven by the Arria V GX FPGA. Table 231 lists the HSMC user-defined LED schematic signal names and their corresponding Arria V GX FPGA pin numbers. Table 231. HSMC User-Defined LED Schematic Signal Names and Functions Board Reference Schematic Signal Name Arria V GX FPGA Pin Number I/O Standard D5 HSMA_TX_LED U16.AH14 2.5-V D4 HSMA_RX_LED U16.AT15 2.5-V Description User-defined LEDs. Labeled TX for HSMC port A. User-defined LEDs. Labeled RX for HSMC port A. Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components General User Input/Output 233 Table 231. HSMC User-Defined LED Schematic Signal Names and Functions Board Reference Schematic Signal Name Arria V GX FPGA Pin Number I/O Standard D8 HSMB_TX_LED U13.AM28 2.5-V D7 HSMB_RX_LED U13.AG26 2.5-V Description User-defined LEDs. Labeled TX for HSMC port B. User-defined LEDs. Labeled RX for HSMC port B. Table 232 lists the HSMC user-defined LED component reference and the manufacturing information. Table 232. HSMC User-Defined LED Component Reference and Manufacturing Information Board Reference Description D4, D5, D7, D8 Green LEDs Manufacturer Lumex Inc. Manufacturer Part Number SML-LXT0805GW-TR Manufacturer Website www.lumex.com LCD The development board includes a single 14-pin 0.1" pitch dual-row header that interfaces to a 16 character × 2 line Lumex LCD display. The LCD has a 14-pin receptacle that mounts directly to the board's 14-pin header, so it can be easily removed for access to components under the display. You can also use the header for debugging or other purposes. Table 233 summarizes the LCD pin assignments. The signal names and directions are relative to the Arria V GX FPGA. Table 233. LCD Pin Assignments, Schematic Signal Names, and Functions Board Reference (J30) Schematic Signal Name Arria V GX FPGA Pin Number I/O Standard 7 LCD1_DATA0 8 LCD1_DATA1 9 LCD1_DATA2 10 LCD1_DATA3 11 LCD1_DATA4 12 LCD1_DATA5 13 LCD1_DATA6 14 LCD1_DATA7 4 LCD1_D_Cn 5 LCD1_WEn 6 LCD1_CSn N20 2.5-V R20 2.5-V T20 2.5-V J20 2.5-V K20 2.5-V J19 2.5-V K19 2.5-V L19 2.5-V M19 2.5-V M20 2.5-V E18 2.5-V Description LCD data bus LCD data bus LCD data bus LCD data bus LCD data bus LCD data bus LCD data bus LCD data bus LCD data or command select LCD write enable LCD chip select November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 234 Chapter 2: Board Components General User Input/Output Table 234 lists the LCD pin definitions, and is an excerpt from Lumex data sheet. Table 234. LCD Pin Definitions and Functions Pin Number 1 2 3 Symbol VDD VSS V0 4 RS 5 6 714 R/W E DB0DB7 Level -- -- -- H/L H/L H, H to L H/L Function 5 V Power supply GND (0 V) For LCD drive Register select signal H: Data input L: Instruction input H: Data read (module to MPU) L: Data write (MPU to module) Enable Data bus--software selectable 4-bit or 8-bit mode f For more information such as timing, character maps, interface guidelines, and other related documentation, visit www.lumex.com. Table 235 lists the LCD component references and the manufacturing information. Table 235. LCD Component References and Manufacturing Information Board Reference J30 Description 2×7 pin, 100 mil, vertical header 2×16 character display, 5×8 dot matrix Manufacturer Samtec Lumex Inc. Manufacturer Part Number TSM-107-01-G-DV LCM-S01602DSR/C Manufacturer Website www.samtec.com www.lumex.com SDI Video Output/Input The SDI video port consists of a LMH0303SQx cable driver and a LMH0384SQ cable equalizer. The PHY devices from National Semiconductor interface to single-ended 75- SMB connectors. The cable driver supports operation at 270 Mbit standard definition (SD), 1.5 Gbit high definition (HD), and 3.0 Gbit dual-link HD modes. Control signals are allowed for SD and HD modes selections, as well as device enable. The device can be clocked by the 148.5 MHz voltage-controlled crystal oscillator (VCXO) and matched to incoming signals within 50 ppm using the UP and DN voltage control lines to the VCXO. Table 236 lists the supported output standards for the SD and HD input. Table 236. Supported Output Standards for SD and HD Input SD_HD Input Supported Output Standards 0 SMPTE 424M, SMPTE 292M 1 SMPTE 259M Rise TIme Faster Slower Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components General User Input/Output 235 f For more information about the application circuit of the LMH0303SQx cable driver, refer to the cable driver data sheet at www.national.com. Table 237 summarizes the SDI video output interface pin assignments, signal names, and functions. Table 237. SDI Video Output Interface Pin Assignments, Schematic Signal Names, and Functions Board Reference (U24) Schematic Signal Name 1 SDI_A_TX_P 2 SDI_A_TX_N 4 SDI_A_TX_RSET 6 SDI_A_TX_EN 10 SDI_A_TX_SD_HDN 11 SDI_A_TXDRV_N 12 SDI_A_TXDRV_P Arria V GX FPGA Pin Number AH3 AH4 -- AK31 M20 -- -- I/O Standard 1.4-V PCML 1.4-V PCML 3.3-V 2.5-V 2.5-V 3.3-V 3.3-V Description SDI video input P SDI video input N Device reset pull up register Device enable High definition select SDI video output from cable driver N SDI video output from cable driver P The cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD, and 3.0 Gbit dual-link HD modes. Control signals are allowed for bypassing or disabling the device, as well as a carrier detect or auto-mute signal interface. Table 238 lists the cable equalizer lengths. Table 238. SDI Cable Equalizer Lengths Data Rate (Mbps) Cable Type 270 1485 2970 Belden 1694A Maximum Cable Length (m) 400 140 120 November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 236 Chapter 2: Board Components General User Input/Output Figure 27 is an excerpt from the LMH0384SQ cable equalizer data sheet that shows the SDI cable equalizer. On this development board, the output is a single-ended output, with the negative channel driving a load local to the board. Figure 27. SDI Cable Equalizer Coaxial Cable 75 3.9 nH 1.0 F 1.0 F 75 37.4 SDI Adaptive Cable Equalizer SDI SDO SDI SDO MUTE MUTEREF BYPASS CD To FPGA AEC+ AEC MUTE MUTEREF BYPASS CD 1.0 F Table 239 summarizes the SDI video input interface pin assignments, signal names, and functions. Table 239. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions Board Reference (U23) Schematic Signal Name 2 SDI_A_EQIN_P1 3 SDI_A_EQIN_N1 7 SDI_A_RX_BYPASS 11 SDI_A_RX_P 10 SDI_A_RX_N 14 SDI_A_RX_EN 15 SDI_A_RX_CDN Arria V GX FPGA Pin Number -- -- P19 AJ1 AJ2 AK34 -- I/O Standard 3.3-V 3.3-V 2.5-V 1.4-V PCML 1.4-V PCML 2.5-V 3.3-V Description SDI video cable equalizer input P SDI video cable equalizer input N Equalizer bypass enable SDI video output P SDI video output N Device enable SDI video cable equalizer input carrier detect output to LED Table 240 lists the SDI connector component reference and manufacturing information. Table 240. SDI Connector Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number U24 3-Gbps HD/SD SDI cable driver with cable detect National Semiconductor LMH0303SQx U23 3-Gbps HD/SD SDI adaptive cable equalizer National Semiconductor LMH0384SQ Manufacturer Website www.national.com www.national.com Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Components and Interfaces 237 Components and Interfaces This section describes the development board's communication ports and interface cards relative to the Arria V GX FPGA. The development board supports the following communication ports: PCI Express 10/100/1000 Ethernet HSMC SFP+ module FMC connector Bull's Eye connector PCI Express The Arria V GX FPGA development board is designed to fit entirely into a PC motherboard with a ×8 PCI Express slot that can accommodate a full height long form factor add-in card. This interface uses the Arria V GX FPGA's PCI Express hard IP block, saving logic resources for the user logic application. The PCI express edge connector has a presence detect feature to allow the motherboard to determine if a card is installed. f For more information on using the PCI Express hard IP block, refer to the PCI Express Compiler User Guide. The PCI Express interface supports auto-negotiating channel width from ×1 to ×4 to ×8 by using Altera's PCIe MegaCore IP. You can also configure this board to a ×1, ×4, or ×8 interface through a DIP switch that connects the PRSNTn pins for each bus width. The PCI Express edge connector has a connection speed of 2.5 Gbps/lane for a maximum of 20 Gbps full-duplex (Gen1) or 5.0 Gbps/lane for a maximum of 40 Gbps full-duplex (Gen2). The power for the board can be sourced entirely from the PCI Express edge connector when installed into a PC motherboard. Although the board can also be powered by a laptop power supply for use on a lab bench, Altera recommends that you do not power up from both supplies at the same time. Ideal diode power sharing devices have been designed into this board to prevent damages or back-current from one supply to the other. The PCIE_REFCLK_P signal is a 100 MHz differential input that is driven from the PC motherboard on to this board through the edge connector. This signal connects directly to a Arria V GX FPGA REFCLK input pin pair using DC coupling. This clock is terminated on the motherboard and therefore, no on-board termination is required. This clock can have spread-spectrum properties that change its period between 9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic (HCSL). November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 238 Chapter 2: Board Components Components and Interfaces Figure 28 shows the PCI Express reference clock levels. Figure 28. PCI Express Reference Clock Levels VMAX = 1.15 V REFCLK VCROSS MAX = 550 mV VCROSS MIN = 250 mV REFCLK + VMIN = 0.30 V The JTAG and SMB are optional signals in the PCI Express specification. Therefore, the JTAG signal loopback from PCI Express TDI to PCI Express TDO and are not used on this board. The SMB signals are wired to the Arria V GX FPGA but are not required for normal operation. Table 241 summarizes the PCI Express pin assignments. The signal names and directions are relative to the Arria V GX FPGA. Table 241. PCI Express Pin Assignments, Schematic Signal Names, and Functions Board Reference (J4) Schematic Signal Name A5 PCIE_JTAG_TCK A6 PCIE_JTAG_TDI A7 PCIE_JTAG_TDO A8 PCIE_JTAG_TMS A11 PCIE_PERSTN A1 PCIE_PRSNT1N B17 PCIE_PRSNT2N_X1 B31 PCIE_PRSNT2N_X4 B48 PCIE_PRSNT2N_X8 A14 PCIE_REFCLK_N A13 PCIE_REFCLK_P B15 PCIE_RX_N0 B20 PCIE_RX_N1 B24 PCIE_RX_N2 B28 PCIE_RX_N3 B34 PCIE_RX_N4 B38 PCIE_RX_N5 B42 PCIE_RX_N6 B46 PCIE_RX_N7 B14 PCIE_RX_P0 B19 PCIE_RX_P1 B23 PCIE_RX_P2 Arria V GX FPGA Pin Number -- -- -- -- N9 -- -- -- -- AG33 AG32 AW36 AT38 AP38 AM38 AH38 AF38 AD38 AB38 AW37 AT39 AP39 I/O Standard Description 1.5-V PCML JTAG chain clock 1.5-V PCML JTAG chain data in 1.5-V PCML JTAG chain data out 1.5-V PCML JTAG chain mode select 1.5-V PCML Presence detect DIP switch 1.5-V PCML Presence detect DIP switch 1.5-V PCML Presence detect DIP switch 1.5-V PCML Presence detect DIP switch 1.5-V PCML Presence detect DIP switch 1.5-V PCML Motherboard reference clock 1.5-V PCML Motherboard reference clock 1.5-V PCML Receive bus 1.5-V PCML Receive bus 1.5-V PCML Receive bus 1.5-V PCML Receive bus 1.5-V PCML Receive bus 1.5-V PCML Receive bus 1.5-V PCML Receive bus 1.5-V PCML Receive bus 1.5-V PCML Receive bus 1.5-V PCML Receive bus 1.5-V PCML Receive bus Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Components and Interfaces 239 Table 241. PCI Express Pin Assignments, Schematic Signal Names, and Functions Board Reference (J4) Schematic Signal Name B27 PCIE_RX_P3 B33 PCIE_RX_P4 B37 PCIE_RX_P5 B41 PCIE_RX_P6 B45 PCIE_RX_P7 B5 PCIE_SMBCLK B6 PCIE_SMBDAT A17 PCIE_TX_CN0 A22 PCIE_TX_CN1 A26 PCIE_TX_CN2 A30 PCIE_TX_CN3 A36 PCIE_TX_CN4 A40 PCIE_TX_CN5 A44 PCIE_TX_CN6 A48 PCIE_TX_CN7 A16 PCIE_TX_CP0 A21 PCIE_TX_CP1 A25 PCIE_TX_CP2 A29 PCIE_TX_CP3 A35 PCIE_TX_CP4 A39 PCIE_TX_CP5 A43 PCIE_TX_CP6 A47 PCIE_TX_CP7 B11 PCIE_WAKEN_R Arria V GX FPGA Pin Number AM39 AH39 AF39 AD39 AB39 AV18 AM16 AU36 AR36 AN36 AL36 AG36 AE36 AC36 AA36 AU37 AR37 AN37 AL37 AG37 AE37 AC37 AA37 AL16 I/O Standard Description 1.5-V PCML Receive bus 1.5-V PCML Receive bus 1.5-V PCML Receive bus 1.5-V PCML Receive bus 1.5-V PCML Receive bus 1.5-V PCML SMB clock 1.5-V PCML SMB data 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Transmit bus 1.5-V PCML Wake signal Table 244 lists the PCI Express interface component reference and manufacturing information. Table 242. PCI Express Component Reference and Manufacturing Information Board Reference J4 Description Manufacturer 4.20-mm pitch header, 13 A per pin, dual row, right angle, with PCB mounting flanges. Molex Manufacturing Part Number 50-34-8571 Manufacturer Website www.molex.com November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 240 Chapter 2: Board Components Components and Interfaces 10/100/1000 Ethernet This development board supports 10/100/1000 base-T Ethernet using an external Marvell 88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function. The PHY-to-MAC interface employs RGMII using the Arria V GX FPGA LVDS pins in Soft-CDR mode at 1.25 Gbps transmit and receive. In 10-Mb or 100-Mb mode, the RGMII interface still runs at 1.25 GHz but the packet data is repeated 10 or 100 times. The MAC function must be provided in the FPGA for typical networking applications. The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires a 25 MHz reference clock driven from a dedicated oscillator. The PHY interfaces to a HALO HFJ11-1G02E model RJ45 with internal magnetics that can be used for driving copper lines with Ethernet traffic. Figure 29 shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111 PHY. Figure 29. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY RXD[3:0] 10/100/1000 Mbps TXD[3:0] Ethernet MAC Marvell 88E1111 PHY Device Transformer RJ45 RGMII Interface Table 243 lists the Ethernet PHY interface pin assignments. Table 243. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 1 of 2) Board Reference (U14) 8 23 60 70 76 74 73 58 69 68 25 24 Schematic Signal Name ENET_GTX_CLK ENET_INTN ENET_LED_DUPLEX ENET_LED_DUPLEX ENET_LED_LINK10 ENET_LED_LINK100 ENET_LED_LINK1000 ENET_LED_RX ENET_LED_RX ENET_LED_TX ENET_MDC ENET_MDIO Arria V GX FPGA Pin Number I/O Standard Description AN16 AP16 -- -- -- -- AN17 -- -- -- AJ18 AL17 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS RGMII transmit clock Management bus interrupt Duplex link LED Duplex link LED 10-Mb link LED 100-Mb link LED 1000-Mb link LED RX data active LED RX data active LED TX data active LED Management bus data clock Management bus data Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Components and Interfaces 241 Table 243. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 2 of 2) Board Reference (U14) Schematic Signal Name Arria V GX FPGA Pin Number I/O Standard Description 28 ENET_RESETN 30 ENET_RSET 2 ENET_RX_CLK 95 ENET_RX_D0 92 ENET_RX_D1 93 ENET_RX_D2 91 ENET_RX_D3 94 ENET_RX_DV 75 ENET_RX_N 77 ENET_RX_P 11 ENET_TX_D0 12 ENET_TX_D1 14 ENET_TX_D2 16 ENET_TX_D3 9 ENET_TX_EN 81 ENET_TX_N 82 ENET_TX_P 55 ENET_XTAL_25MHZ 29 MDI_P0 31 MDI_N0 33 MDI_P1 34 MDI_N1 39 MDI_P2 41 MDI_N2 42 MDI_P3 43 MDI_N3 AK17 -- AK7 AU17 AT17 AW16 AH18 AW17 AK19 AL19 AT19 AU18 AH19 AG19 AP19 AE19 AF19 -- -- -- -- -- -- -- -- -- 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS Device reset Bias voltage for the Ethernet PHY. This pin connects to ground through a 4.99-K resistor. RGMII receive clock RGMII receive data RGMII receive data RGMII receive data RGMII receive data RGMII receive data valid RGMII receive channel RGMII receive channel RGMII transmit data RGMII transmit data RGMII transmit data RGMII transmit data RGMII transmit enable RGMII transmit channel RGMII transmit channel 25-MHz clock Media dependent interface 0 Media dependent interface 0 Media dependent interface 1 Media dependent interface 1 Media dependent interface 2 Media dependent interface 2 Media dependent interface 3 Media dependent interface 3 Table 244 lists the Ethernet PHY interface component reference and manufacturing information. Table 244. Ethernet PHY Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number U14 Ethernet PHY BASE-T device Marvell Semiconductor 88E1111-B2-CAA1C000 Manufacturer Website www.marvell.com November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 242 Chapter 2: Board Components Components and Interfaces HSMC The development board contains two HSMC interfaces--port A on device 1 and port B on device 2. HSMC port A and port B interfaces support both single-ended and differential signaling. This physical interface provides four channels of 6.5536 Gbps-capable transceivers for the GX version of this board. For the GT version, Port A provides eight channels. The HSMC interface also supports a full SPI4.2 interface (17 LVDS channels), three input and output clocks, JTAG and SMB signals, as well as power for compatible HSMC cards. The LVDS channels can be used for CMOS signaling as well as LVDS. 1 The HSMC is an Altera-developed open specification, which allows you to expand the functionality of the development board through the addition of daughtercards (HSMCs). f For more information about the HSMC specification such as signaling standards, signal integrity, compatible connectors, and mechanical information, refer to the High Speed Mezzanine Card (HSMC) Specification manual. The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins, and 13 ground pins. The ground pins are located between the two rows of signal and power pins, acting both as a shield and a reference. The HSMC host connector is based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board connectors from Samtec. There are three banks in this connector. Bank 1 has every third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have all the pins populated as done in the QSH/QTH series. Figure 210 shows the bank arrangement of signals with respect to the Samtec connector's three banks. Figure 210. HSMC Signal and Bank Diagram Bank 3 Power D(79.40) -orLVDS CLKIN2, CLKOUT2 Bank 2 Power D(39:0) -orD[3:0] + LVDS CLKIN1, CLKOUT1 Bank 1 8 TX Channels CDR 8 RX Channels CDR JTAG SMB CLKIN0, CLKOUT0 The HSMC interface has programmable bi-directional I/O pins that can be used as 2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as various differential I/O standards including, but not limited to, LVDS, mini-LVDS, and RSDS with up to 17 full-duplex channels. Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components Components and Interfaces 243 1 As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and single-ended I/O standards are only guaranteed to function when mixed according to either the generic single-ended pin-out or generic differential pin-out. Table 245 lists the HSMC port A interface pin assignments, signal names, and functions. Table 245. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4) Board Reference (J1) Schematic Signal Name 1 HSMA_TX_P7 2 HSMA_RX_P7 3 HSMA_TX_N7 4 HSMA_RX_N7 5 HSMA_TX_P6 6 HSMA_RX_P6 7 HSMA_TX_N6 8 HSMA_RX_N6 9 HSMA_TX_P5 10 HSMA_RX_P5 11 HSMA_TX_N5 12 HSMA_RX_N5 13 HSMA_TX_P4 14 HSMA_RX_P4 15 HSMA_TX_N4 16 HSMA_RX_N4 17 HSMA_TX_P3 18 HSMA_RX_P3 19 HSMA_TX_N3 20 HSMA_RX_N3 21 HSMA_TX_P2 22 HSMA_RX_P2 23 HSMA_TX_N2 24 HSMA_RX_N2 25 HSMA_TX_P1 26 HSMA_RX_P1 27 HSMA_TX_N1 28 HSMA_RX_N1 29 HSMA_TX_P0 30 HSMA_RX_P0 31 HSMA_TX_N0 32 HSMA_RX_N0 Arria V GX FPGA Pin Number D3 E1 D4 E2 H3 J1 H4 J2 K3 L1 K4 L2 M3 N1 M4 N2 AH3 AJ1 AH4 AJ2 V3 W1 V4 W2 T3 U1 T4 U2 P3 R1 P4 R2 I/O Standard Description 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML Transceiver TX bit 7 Transceiver RX bit 7 Transceiver TX bit 7n Transceiver RX bit 7n Transceiver TX bit 6 Transceiver RX bit 6 Transceiver TX bit 6n Transceiver RX bit 6n Transceiver TX bit 5 Transceiver RX bit 5 Transceiver TX bit 5n Transceiver RX bit 5n Transceiver TX bit 4 Transceiver RX bit 4 Transceiver TX bit 4n Transceiver RX bit 4n Transceiver TX bit 3 Transceiver RX bit 3 Transceiver TX bit 3n Transceiver RX bit 3n Transceiver TX bit 2 Transceiver RX bit 2 Transceiver TX bit 2n Transceiver RX bit 2n Transceiver TX bit 1 Transceiver RX bit 1 Transceiver TX bit 1n Transceiver RX bit 1n Transceiver TX bit 0 Transceiver RX bit 0 Transceiver TX bit 0n Transceiver RX bit 0n November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 244 Chapter 2: Board Components Components and Interfaces Table 245. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4) Board Reference (J1) Schematic Signal Name Arria V GX FPGA Pin Number I/O Standard Description 33 HSMA_SDA 34 HSMA_SCL 35 JTAG_TCK 36 HSMA_JTAG_TMS 37 HSMA_JTAG_TDO 38 AVB_JTAG_TDO 39 HSMA_CLK_OUT0 40 HSMA_CLK_IN0 41 HSMA_D0 42 HSMA_D1 43 HSMA_D2 44 HSMA_D3 47 HSMA_TX_D_P0 48 HSMA_RX_D_P0 49 HSMA_TX_D_N0 50 HSMA_RX_D_N0 53 HSMA_TX_D_P1 54 HSMA_RX_D_P1 55 HSMA_TX_D_N1 56 HSMA_RX_D_N1 59 HSMA_TX_D_P2 60 HSMA_RX_D_P2 61 HSMA_TX_D_N2 62 HSMA_RX_D_N2 65 HSMA_TX_D_P3 66 HSMA_RX_D_P3 67 HSMA_TX_D_N3 68 HSMA_RX_D_N3 71 HSMA_TX_D_P4 72 HSMA_RX_D_P4 73 HSMA_TX_D_N4 74 HSMA_RX_D_N4 77 HSMA_TX_D_P5 78 HSMA_RX_D_P5 79 HSMA_TX_D_N5 80 HSMA_RX_D_N5 83 HSMA_TX_D_P6 84 HSMA_RX_D_P6 AT14 AU15 AV34 -- -- AT34 AL14 AT7 AG16 AH16 AV13 AW13 AV6 AW12 AV7 AV12 AU6 AR18 AT6 AP18 AU9 AU8 AT9 AU7 AV10 AW8 AU10 AW7 AU12 AW9 AT12 AV9 AP9 AU11 AN9 AT11 AP12 AR9 2.5-V CMOS Management serial data 2.5-V CMOS Management serial clock 2.5-V CMOS JTAG clock signal 2.5-V CMOS JTAG mode select signal 2.5-V CMOS JTAG data output 2.5-V CMOS JTAG data output LVDS or 2.5-V Dedicated CMOS clock out LVDS or 2.5-V Dedicated CMOS clock in 2.5-V CMOS Dedicated CMOS I/O bit 0 2.5-V CMOS Dedicated CMOS I/O bit 1 2.5-V CMOS Dedicated CMOS I/O bit 2 2.5-V CMOS Dedicated CMOS I/O bit 3 LVDS or 2.5-V LVDS TX bit 0 or CMOS bit 4 LVDS or 2.5-V LVDS RX bit 0 or CMOS bit 5 LVDS or 2.5-V LVDS TX bit 0n or CMOS bit 6 LVDS or 2.5-V LVDS RX bit 0n or CMOS bit 7 LVDS or 2.5-V LVDS TX bit 1 or CMOS bit 8 LVDS or 2.5-V LVDS RX bit 1 or CMOS bit 9 LVDS or 2.5-V LVDS TX bit 1n or CMOS bit 10 LVDS or 2.5-V LVDS RX bit 1n or CMOS bit 11 LVDS or 2.5-V LVDS TX bit 2 or CMOS bit 12 LVDS or 2.5-V LVDS RX bit 2 or CMOS bit 13 LVDS or 2.5-V LVDS TX bit 2n or CMOS bit 14 LVDS or 2.5-V LVDS RX bit 2n or CMOS bit 15 LVDS or 2.5-V LVDS TX bit 3 or CMOS bit 16 LVDS or 2.5-V LVDS RX bit 3 or CMOS bit 17 LVDS or 2.5-V LVDS TX bit 3n or CMOS bit 18 LVDS or 2.5-V LVDS RX bit 3n or CMOS bit 19 LVDS or 2.5-V LVDS TX bit 4 or CMOS bit 20 LVDS or 2.5-V LVDS RX bit 4 or CMOS bit 21 LVDS or 2.5-V LVDS TX bit 4n or CMOS bit 22 LVDS or 2.5-V LVDS RX bit 4n or CMOS bit 23 LVDS or 2.5-V LVDS TX bit 5 or CMOS bit 24 LVDS or 2.5-V LVDS RX bit 5 or CMOS bit 25 LVDS or 2.5-V LVDS TX bit 5n or CMOS bit 26 LVDS or 2.5-V LVDS RX bit 5n or CMOS bit 27 LVDS or 2.5-V LVDS TX bit 6 or CMOS bit 28 LVDS or 2.5-V LVDS RX bit 6 or CMOS bit 29 Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Components and Interfaces 245 Table 245. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4) Board Reference (J1) Schematic Signal Name Arria V GX FPGA Pin Number I/O Standard Description 85 HSMA_TX_D_N6 86 HSMA_RX_D_N6 89 HSMA_TX_D_P7 90 HSMA_RX_D_P7 91 HSMA_TX_D_N7 92 HSMA_RX_D_N7 95 HSMA_CLK_OUT_P1 96 HSMA_CLK_IN_P1 97 HSMA_CLK_OUT_N1 98 HSMA_CLK_IN_N1 101 HSMA_TX_D_P8 102 HSMA_RX_D_P8 103 HSMA_TX_D_N8 104 HSMA_RX_D_N8 107 HSMA_TX_D_P9 108 HSMA_RX_D_P9 109 HSMA_TX_D_N9 110 HSMA_RX_D_N9 113 HSMA_TX_D_P10 114 HSMA_RX_D_P10 115 HSMA_TX_D_N10 116 HSMA_RX_D_N10 119 HSMA_TX_D_P11 120 HSMA_RX_D_P11 121 HSMA_TX_D_N11 122 HSMA_RX_D_N11 125 HSMA_TX_D_P12 126 HSMA_RX_D_P12 127 HSMA_TX_D_N12 128 HSMA_RX_D_N12 131 HSMA_TX_D_P13 132 HSMA_RX_D_P13 133 HSMA_TX_D_N13 134 HSMA_RX_D_N13 137 HSMA_TX_D_P14 138 HSMA_RX_D_P14 139 HSMA_TX_D_N14 140 HSMA_RX_D_N14 AN12 AT8 AM9 AW5 AL9 AW6 AU13 AW4 AT13 AV4 AL8 AW11 AK8 AW10 AK10 AR10 AK9 AP10 AL11 AM10 AK11 AL10 AL12 AJ13 AK12 AH13 AM13 AH11 AL13 AG11 AE12 AG12 AD12 AF12 AD11 AD13 AC12 AC13 LVDS or 2.5-V LVDS TX bit 6n or CMOS bit 30 LVDS or 2.5-V LVDS RX bit 6n or CMOS bit 31 LVDS or 2.5-V LVDS TX bit 7 or CMOS bit 32 LVDS or 2.5-V LVDS RX bit 7 or CMOS bit 33 LVDS or 2.5-V LVDS TX bit 7n or CMOS bit 34 LVDS or 2.5-V LVDS RX bit 7n or CMOS bit 35 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 36 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 37 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 38 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 39 LVDS or 2.5-V LVDS TX bit 8 or CMOS bit 40 LVDS or 2.5-V LVDS RX bit 8 or CMOS bit 41 LVDS or 2.5-V LVDS TX bit 8n or CMOS bit 42 LVDS or 2.5-V LVDS RX bit 8n or CMOS bit 43 LVDS or 2.5-V LVDS TX bit 9 or CMOS bit 44 LVDS or 2.5-V LVDS RX bit 9 or CMOS bit 45 LVDS or 2.5-V LVDS TX bit 9n or CMOS bit 46 LVDS or 2.5-V LVDS RX bit 9n or CMOS bit 47 LVDS or 2.5-V LVDS TX bit 10 or CMOS bit 48 LVDS or 2.5-V LVDS RX bit 10 or CMOS bit 49 LVDS or 2.5-V LVDS TX bit 10n or CMOS bit 50 LVDS or 2.5-V LVDS RX bit 10n or CMOS bit 51 LVDS or 2.5-V LVDS TX bit 11 or CMOS bit 52 LVDS or 2.5-V LVDS RX bit 11 or CMOS bit 53 LVDS or 2.5-V LVDS TX bit 11n or CMOS bit 54 LVDS or 2.5-V LVDS RX bit 11n or CMOS bit 55 LVDS or 2.5-V LVDS TX bit 12 or CMOS bit 56 LVDS or 2.5-V LVDS RX bit 12 or CMOS bit 57 LVDS or 2.5-V LVDS TX bit 12n or CMOS bit 58 LVDS or 2.5-V LVDS RX bit 12n or CMOS bit 59 LVDS or 2.5-V LVDS TX bit 13 or CMOS bit 60 LVDS or 2.5-V LVDS RX bit 13 or CMOS bit 61 LVDS or 2.5-V LVDS TX bit 13n or CMOS bit 62 LVDS or 2.5-V LVDS RX bit 13n or CMOS bit 63 LVDS or 2.5-V LVDS TX bit 14 or CMOS bit 64 LVDS or 2.5-V LVDS RX bit 14 or CMOS bit 65 LVDS or 2.5-V LVDS TX bit 14n or CMOS bit 66 LVDS or 2.5-V LVDS RX bit 14n or CMOS bit 67 November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 246 Chapter 2: Board Components Components and Interfaces Table 245. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4) Board Reference (J1) Schematic Signal Name Arria V GX FPGA Pin Number I/O Standard Description 143 HSMA_TX_D_P15 144 HSMA_RX_D_P15 145 HSMA_TX_D_N15 146 HSMA_RX_D_N15 149 HSMA_TX_D_P16 150 HSMA_RX_D_P16 151 HSMA_TX_D_N16 152 HSMA_RX_D_N16 155 HSMA_CLK_OUT_P2 156 HSMA_CLK_IN_P2 157 HSMA_CLK_OUT_N2 158 HSMA_CLK_IN_N2 160 HSMA_PSNTN AR13 AE13 AP13 AE14 AJ12 AG13 AH12 AF13 AM7 AR6 AL7 AP6 AW15 LVDS or 2.5-V LVDS TX bit 15 or CMOS bit 68 LVDS or 2.5-V LVDS RX bit 15 or CMOS bit 69 LVDS or 2.5-V LVDS TX bit 15n or CMOS bit 70 LVDS or 2.5-V LVDS RX bit 15n or CMOS bit 71 LVDS or 2.5-V LVDS TX bit 16 or CMOS bit 72 LVDS or 2.5-V LVDS RX bit 16 or CMOS bit 73 LVDS or 2.5-V LVDS TX bit 16n or CMOS bit 74 LVDS or 2.5-V LVDS RX bit 16n or CMOS bit 75 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 76 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 77 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 78 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 79 2.5-V CMOS HSMC port A presence detect Table 246 lists the HSMC port B interface pin assignments, signal names, and functions. Table 246. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4) Board Reference (J2) Schematic Signal Name 17 HSMB_TX_P3 18 HSMB_RX_P3 19 HSMB_TX_N3 20 HSMB_RX_N3 21 HSMB_TX_P2 22 HSMB_RX_P2 23 HSMB_TX_N2 24 HSMB_RX_N2 25 HSMB_TX_P1 26 HSMB_RX_P1 27 HSMB_TX_N1 28 HSMB_RX_N1 29 HSMB_TX_P0 30 HSMB_RX_P0 31 HSMB_TX_N0 32 HSMB_RX_N0 33 HSMB_SDA 34 HSMB_SCL 35 JTAG_TCK Arria V GX FPGA Pin Number AT3 AU1 AT4 AU2 AP3 AR1 AP4 AR2 AM3 AN1 AM4 AN2 AK3 AL1 AK4 AL2 AG25 AH26 AV34 I/O Standard Description 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 2.5-V CMOS 2.5-V CMOS 2.5-V CMOS Transceiver TX bit 3 Transceiver RX bit 3 Transceiver TX bit 3n Transceiver RX bit 3n Transceiver TX bit 2 Transceiver RX bit 2 Transceiver TX bit 2n Transceiver RX bit 2n Transceiver TX bit 1 Transceiver RX bit 1 Transceiver TX bit 1n Transceiver RX bit 1n Transceiver TX bit 0 Transceiver RX bit 0 Transceiver TX bit 0n Transceiver RX bit 0n Management serial data Management serial clock JTAG clock signal Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Components and Interfaces 247 Table 246. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4) Board Reference (J2) Schematic Signal Name Arria V GX FPGA Pin Number I/O Standard Description 36 HSMB_JTAG_TMS 37 HSMB_JTAG_TDO 38 HSMB_JTAG_TDI 39 HSMB_CLK_OUT0 40 HSMB_CLK_IN0 41 HSMB_D0 42 HSMB_D1 43 HSMB_D2 44 HSMB_D3 47 HSMB_TX_D_P0 48 HSMB_RX_D_P0 49 HSMB_TX_D_N0 50 HSMB_RX_D_N0 53 HSMB_TX_D_P1 54 HSMB_RX_D_P1 55 HSMB_TX_D_N1 56 HSMB_RX_D_N1 59 HSMB_TX_D_P2 60 HSMB_RX_D_P2 61 HSMB_TX_D_N2 62 HSMB_RX_D_N2 65 HSMB_TX_D_P3 66 HSMB_RX_D_P3 67 HSMB_TX_D_N3 68 HSMB_RX_D_N3 71 HSMB_TX_D_P4 72 HSMB_RX_D_P4 73 HSMB_TX_D_N4 74 HSMB_RX_D_N4 77 HSMB_TX_D_P5 78 HSMB_RX_D_P5 79 HSMB_TX_D_N5 80 HSMB_RX_D_N5 83 HSMB_TX_D_P6 84 HSMB_RX_D_P6 85 HSMB_TX_D_N6 86 HSMB_RX_D_N6 89 HSMB_TX_D_P7 -- -- -- AJ33 AR6 AW25 AW26 AV25 AV24 AC29 AC25 AB29 AB25 AE28 AF25 AD28 AE25 AE29 AD27 AD29 AC27 AK27 AB28 AJ27 AB27 AL29 AJ28 AK29 AH28 AL30 AG28 AK30 AF28 AL32 AH30 AK32 AG30 AM31 2.5-V CMOS JTAG mode select signal 2.5-V CMOS JTAG data output 2.5-V CMOS JTAG data input LVDS or 2.5-V Dedicated CMOS clock out LVDS or 2.5-V Dedicated CMOS clock in 2.5-V CMOS Dedicated CMOS I/O bit 0 2.5-V CMOS Dedicated CMOS I/O bit 1 2.5-V CMOS Dedicated CMOS I/O bit 2 2.5-V CMOS Dedicated CMOS I/O bit 3 LVDS or 2.5-V LVDS TX bit 0 or CMOS bit 4 LVDS or 2.5-V LVDS RX bit 0 or CMOS bit 5 LVDS or 2.5-V LVDS TX bit 0n or CMOS bit 6 LVDS or 2.5-V LVDS RX bit 0n or CMOS bit 7 LVDS or 2.5-V LVDS TX bit 1 or CMOS bit 8 LVDS or 2.5-V LVDS RX bit 1 or CMOS bit 9 LVDS or 2.5-V LVDS TX bit 1n or CMOS bit 10 LVDS or 2.5-V LVDS RX bit 1n or CMOS bit 11 LVDS or 2.5-V LVDS TX bit 2 or CMOS bit 12 LVDS or 2.5-V LVDS RX bit 2 or CMOS bit 13 LVDS or 2.5-V LVDS TX bit 2n or CMOS bit 14 LVDS or 2.5-V LVDS RX bit 2n or CMOS bit 15 LVDS or 2.5-V LVDS TX bit 3 or CMOS bit 16 LVDS or 2.5-V LVDS RX bit 3 or CMOS bit 17 LVDS or 2.5-V LVDS TX bit 3n or CMOS bit 18 LVDS or 2.5-V LVDS RX bit 3n or CMOS bit 19 LVDS or 2.5-V LVDS TX bit 4 or CMOS bit 20 LVDS or 2.5-V LVDS RX bit 4 or CMOS bit 21 LVDS or 2.5-V LVDS TX bit 4n or CMOS bit 22 LVDS or 2.5-V LVDS RX bit 4n or CMOS bit 23 LVDS or 2.5-V LVDS TX bit 5 or CMOS bit 24 LVDS or 2.5-V LVDS RX bit 5 or CMOS bit 25 LVDS or 2.5-V LVDS TX bit 5n or CMOS bit 26 LVDS or 2.5-V LVDS RX bit 5n or CMOS bit 27 LVDS or 2.5-V LVDS TX bit 6 or CMOS bit 28 LVDS or 2.5-V LVDS RX bit 6 or CMOS bit 29 LVDS or 2.5-V LVDS TX bit 6n or CMOS bit 30 LVDS or 2.5-V LVDS RX bit 6n or CMOS bit 31 LVDS or 2.5-V LVDS TX bit 7 or CMOS bit 32 November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 248 Chapter 2: Board Components Components and Interfaces Table 246. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4) Board Reference (J2) Schematic Signal Name Arria V GX FPGA Pin Number I/O Standard Description 90 HSMB_RX_D_P7 91 HSMB_TX_D_N7 92 HSMB_RX_D_N7 95 HSMB_CLK_OUT_P1 96 HSMB_CLK_IN_P1 97 HSMB_CLK_OUT_N1 98 HSMB_CLK_IN_N1 101 HSMB_TX_D_P8 102 HSMB_RX_D_P8 103 HSMB_TX_D_N8 104 HSMB_RX_D_N8 107 HSMB_TX_D_P9 108 HSMB_RX_D_P9 109 HSMB_TX_D_N9 110 HSMB_RX_D_N9 113 HSMB_TX_D_P10 114 HSMB_RX_D_P10 115 HSMB_TX_D_N10 116 HSMB_RX_D_N10 119 HSMB_TX_D_P11 120 HSMB_RX_D_P11 121 HSMB_TX_D_N11 122 HSMB_RX_D_N11 125 HSMB_TX_D_P12 126 HSMB_RX_D_P12 127 HSMB_TX_D_N12 128 HSMB_RX_D_N12 131 HSMB_TX_D_P13 132 HSMB_RX_D_P13 133 HSMB_TX_D_N13 134 HSMB_RX_D_N13 137 HSMB_TX_D_P14 138 HSMB_RX_D_P14 139 HSMB_TX_D_N14 140 HSMB_RX_D_N14 143 HSMB_TX_D_P15 144 HSMB_RX_D_P15 145 HSMB_TX_D_N15 AP29 AL31 AN29 AM34 AM33 AL34 AL33 AN27 AU29 AM27 AT29 AP30 AW31 AN30 AW30 AR28 AW28 AP28 AW29 AV30 AU27 AU30 AT27 AV31 AW27 AU31 AV27 AR27 AW32 AP27 AW33 AP31 AT31 AN31 AR31 AP32 AV28 AN32 LVDS or 2.5-V LVDS RX bit 7 or CMOS bit 33 LVDS or 2.5-V LVDS TX bit 7n or CMOS bit 34 LVDS or 2.5-V LVDS RX bit 7n or CMOS bit 35 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 36 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 37 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 38 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 39 LVDS or 2.5-V LVDS TX bit 8 or CMOS bit 40 LVDS or 2.5-V LVDS RX bit 8 or CMOS bit 41 LVDS or 2.5-V LVDS TX bit 8n or CMOS bit 42 LVDS or 2.5-V LVDS RX bit 8n or CMOS bit 43 LVDS or 2.5-V LVDS TX bit 9 or CMOS bit 44 LVDS or 2.5-V LVDS RX bit 9 or CMOS bit 45 LVDS or 2.5-V LVDS TX bit 9n or CMOS bit 46 LVDS or 2.5-V LVDS RX bit 9n or CMOS bit 47 LVDS or 2.5-V LVDS TX bit 10 or CMOS bit 48 LVDS or 2.5-V LVDS RX bit 10 or CMOS bit 49 LVDS or 2.5-V LVDS TX bit 10n or CMOS bit 50 LVDS or 2.5-V LVDS RX bit 10n or CMOS bit 51 LVDS or 2.5-V LVDS TX bit 11 or CMOS bit 52 LVDS or 2.5-V LVDS RX bit 11 or CMOS bit 53 LVDS or 2.5-V LVDS TX bit 11n or CMOS bit 54 LVDS or 2.5-V LVDS RX bit 11n or CMOS bit 55 LVDS or 2.5-V LVDS TX bit 12 or CMOS bit 56 LVDS or 2.5-V LVDS RX bit 12 or CMOS bit 57 LVDS or 2.5-V LVDS TX bit 12n or CMOS bit 58 LVDS or 2.5-V LVDS RX bit 12n or CMOS bit 59 LVDS or 2.5-V LVDS TX bit 13 or CMOS bit 60 LVDS or 2.5-V LVDS RX bit 13 or CMOS bit 61 LVDS or 2.5-V LVDS TX bit 13n or CMOS bit 62 LVDS or 2.5-V LVDS RX bit 13n or CMOS bit 63 LVDS or 2.5-V LVDS TX bit 14 or CMOS bit 64 LVDS or 2.5-V LVDS RX bit 14 or CMOS bit 65 LVDS or 2.5-V LVDS TX bit 14n or CMOS bit 66 LVDS or 2.5-V LVDS RX bit 14n or CMOS bit 67 LVDS or 2.5-V LVDS TX bit 15 or CMOS bit 68 LVDS or 2.5-V LVDS RX bit 15 or CMOS bit 69 LVDS or 2.5-V LVDS TX bit 15n or CMOS bit 70 Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Components and Interfaces 249 Table 246. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4) Board Reference (J2) Schematic Signal Name Arria V GX FPGA Pin Number I/O Standard Description 146 HSMB_RX_D_N15 149 HSMB_TX_D_P16 150 HSMB_RX_D_P16 151 HSMB_TX_D_N16 152 HSMB_RX_D_N16 155 HSMB_CLK_OUT_P2 156 HSMB_CLK_IN_P2 157 HSMB_CLK_OUT_N2 158 HSMB_CLK_IN_N2 160 HSMB_PRSNTN AU28 AP33 AT30 AN33 AR30 AE26 AU32 AD26 AT32 AT24 LVDS or 2.5-V LVDS RX bit 15n or CMOS bit 71 LVDS or 2.5-V LVDS TX bit 16 or CMOS bit 72 LVDS or 2.5-V LVDS RX bit 16 or CMOS bit 73 LVDS or 2.5-V LVDS TX bit 16n or CMOS bit 74 LVDS or 2.5-V LVDS RX bit 16n or CMOS bit 75 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 76 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 77 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 78 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 79 2.5-V CMOS HSMC port B presence detect Table 247 lists the HSMC connector component reference and manufacturing information. Table 247. HSMC Connector Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number J1, J2 HSMC, custom version of QSH-DP family high-speed socket. Samtec ASP-122953-01 Manufacturer Website www.samtec.com SFP+ Module The development board include two SFP+ modules that use transceiver channels from the FPGA. These modules takes in serial data from the FPGA and transform them into optical signals. The Arria V GX FPGA development board includes one SFP+ cage assembly for the SFP+ port that is used by the device. 1 The second SFP+ port is active and includes the SFP+ cage assembly only when the Arria V GT FPGA device is installed. Table 248 lists the SFP+ module interface pin assignments, signal names, and functions. Table 248. SFP+ Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2) Board Reference (J10) Schematic Signal Name Arria V GX FPGA Pin Number I/O Standard Description 6 SFP_MOD_ABS1 8 SFP_OP_RX_LOS1 2 SFP_OP_TX_FLT1 12 SFP_RX_N1 13 SFP_RX_P1 5 SFP_SCL1 AK16 AN19 AG17 Y38 Y39 AL18 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML Module present indicator Signal present indicator Transmitter fault indicator Receiver data Receiver data Serial 2-wire clock November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 250 Chapter 2: Board Components Components and Interfaces Table 248. SFP+ Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2) Board Reference (J10) Schematic Signal Name Arria V GX FPGA Pin Number I/O Standard Description 4 SFP_SDA1 3 SFP_TX_DIS1 19 SFP_TX_N1 18 SFP_TX_P1 7 SFP_TX_RS01 9 SFP_TX_RS11 AC16 AN15 W36 W37 AN14 AE15 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML 1.5-V PCML Serial 2-wire data Drive low to disable transmitter Transmitter data Transmitter data Reserved Reserved Table 249 lists the SFP+ module component reference and manufacturing information. Table 249. SFP+ Interface Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number B2 SFP+ right-angle, press-fit cage J10 SFP+ right-angle, 20-pin SMT connector Molex Samtec 74754-0101 MECT-110-01-M-D-RA1 Manufacturer Website www.molex.com www.samtec.com FMC Connector The development board contains a high pin count (HPC) FPGA mezzanine card (FMC) connector that functions with a quadrature amplitude modulation (QAM) digital-to-analog converter (DAC) FMC module or daughter card. This pinout satisfies a QAM DAC that requires 58 LVDS data output pairs, one LVDS input clock pair, and three low-voltage differential signaling (LVDS) control pairs from the Arria V. These pins also have the option to be used as single-ended I/O pins. The VCCIO supply for the FMC A banks in the low pin count (LPC) and HPC provide a variable voltage of 1.5 V, 1.8 V, 2.5 V (default), or 3.3 V. The VCCIO supply for the FMC B bank in the HPC provides a variable voltage from 1.2 V to 3.3 V, which can be supplied by the FMC module. However, for the sake of device safety concerns, a jumper is available for you to connect this bank to the same VCCIO used for the FMC A banks. This allows the VCCIO pins on the FPGA to be tied to a known power. The VCCIO pins also allows you the option to perform a manual check for the module's input voltage before connecting to the FPGA. This is to ensure that the module does not exceed the power supply maximum voltage rating. Table 250 lists the FMC connector pin assignments, signal names, and functions. Table 250. FMC Connector Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 7) Board Reference (J10) Schematic Signal Name D1 FMC_C2M_PG K4 FMC_CLK_BIDIR_P2 K5 FMC_CLK_BIDIR_N2 J2 FMC_CLK_BIDIR_P3 Arria V GX FPGA I/O Standard Pin Number Description -- 2.5-V CMOS Power good output AE23 2.5-V CMOS Clock input or output 2 AD22 2.5-V CMOS Clock input or output 2 AU22 2.5-V CMOS Clock input or output 3 Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Components and Interfaces 251 Table 250. FMC Connector Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 7) Board Reference (J10) Schematic Signal Name Arria V GX FPGA I/O Standard Pin Number Description J3 FMC_CLK_BIDIR_N3 B1 FMC_CLK_DIR H4 FMC_CLK_M2C_P0 H5 FMC_CLK_M2C_N0 G2 FMC_CLK_M2C_P1 G3 FMC_CLK_M2C_N1 C3 FMC_DP_C2M_N0 A23 FMC_DP_C2M_N1 A27 FMC_DP_C2M_N2 A31 FMC_DP_C2M_N3 A35 FMC_DP_C2M_N4 A39 FMC_DP_C2M_N5 B37 FMC_DP_C2M_N6 B33 FMC_DP_C2M_N7 B29 FMC_DP_C2M_N8 B25 FMC_DP_C2M_N9 C2 FMC_DP_C2M_P0 A22 FMC_DP_C2M_P1 A26 FMC_DP_C2M_P2 A30 FMC_DP_C2M_P3 A34 FMC_DP_C2M_P4 A38 FMC_DP_C2M_P5 B36 FMC_DP_C2M_P6 B32 FMC_DP_C2M_P7 B28 FMC_DP_C2M_P8 B24 FMC_DP_C2M_P9 C7 FMC_DP_M2C_N0 A3 FMC_DP_M2C_N1 A7 FMC_DP_M2C_N2 A11 FMC_DP_M2C_N3 A15 FMC_DP_M2C_N4 A19 FMC_DP_M2C_N5 B17 FMC_DP_M2C_N6 B13 FMC_DP_M2C_N7 B9 FMC_DP_M2C_N8 B5 FMC_DP_M2C_N9 C6 FMC_DP_M2C_P0 A2 FMC_DP_M2C_P1 AT22 AW21 AV19 AU19 AF21 AE21 AD4 Y4 T4 P4 H4 M4 K4 F4 D4 B4 AD3 Y3 T3 P3 H3 M3 K3 F3 D3 B3 AE2 AA2 U2 R2 J2 N2 L2 G2 E2 C2 AE1 AA1 2.5-V CMOS Clock input or output 3 2.5-V CMOS Clock direction select for FMC_CLK_BIDIR 2.5-V CMOS Clock input 0 2.5-V CMOS Clock input 0 2.5-V CMOS Clock input 1 2.5-V CMOS Clock input 1 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 252 Chapter 2: Board Components Components and Interfaces Table 250. FMC Connector Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 7) Board Reference (J10) Schematic Signal Name Arria V GX FPGA I/O Standard Pin Number Description A6 FMC_DP_M2C_P2 A10 FMC_DP_M2C_P3 A14 FMC_DP_M2C_P4 A18 FMC_DP_M2C_P5 B16 FMC_DP_M2C_P6 B12 FMC_DP_M2C_P7 B8 FMC_DP_M2C_P8 B4 FMC_DP_M2C_P9 D4 FMC_GBTCLK_M2C_P0 D5 FMC_GBTCLK_M2C_N0 B20 FMC_GBTCLK_M2C_P1 B21 FMC_GBTCLK_M2C_N1 F5 FMC_HA_N0 E3 FMC_HA_N1 K8 FMC_HA_N2 J7 FMC_HA_N3 F8 FMC_HA_N4 E7 FMC_HA_N5 K11 FMC_HA_N6 J10 FMC_HA_N7 F11 FMC_HA_N8 E10 FMC_HA_N9 K14 FMC_HA_N10 J13 FMC_HA_N11 F14 FMC_HA_N12 E13 FMC_HA_N13 J16 FMC_HA_N14 F17 FMC_HA_N15 E16 FMC_HA_N16 K17 FMC_HA_N17 J19 FMC_HA_N18 F20 FMC_HA_N19 E19 FMC_HA_N20 K20 FMC_HA_N21 J22 FMC_HA_N22 K23 FMC_HA_N23 F4 FMC_HA_P0 E2 FMC_HA_P1 U1 R1 J1 N1 L1 G1 E1 C1 AB9 AB8 -- -- AG16 AE17 AU16 AN17 AK9 AK11 K8 AG14 AC19 AL7 G6 AD17 AH18 AE19 AC15 AG20 AK17 AR25 AN20 AN19 AM21 AN23 AN22 AN24 AH16 AF16 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device) 2.5-V CMOS Transceiver reference clock 0 2.5-V CMOS Transceiver reference clock 0 2.5-V CMOS Transceiver reference clock 1 2.5-V CMOS Transceiver reference clock 1 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Components and Interfaces 253 Table 250. FMC Connector Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 7) Board Reference (J10) Schematic Signal Name Arria V GX FPGA I/O Standard Pin Number Description K7 FMC_HA_P2 J6 FMC_HA_P3 F7 FMC_HA_P4 E6 FMC_HA_P5 K10 FMC_HA_P6 J9 FMC_HA_P7 F10 FMC_HA_P8 E9 FMC_HA_P9 K13 FMC_HA_P10 J12 FMC_HA_P11 F13 FMC_HA_P12 E12 FMC_HA_P13 J15 FMC_HA_P14 F16 FMC_HA_P15 E15 FMC_HA_P16 K16 FMC_HA_P17 J18 FMC_HA_P18 F19 FMC_HA_P19 E18 FMC_HA_P20 K19 FMC_HA_P21 J21 FMC_HA_P22 K22 FMC_HA_P23 K26 FMC_HB_N0 J25 FMC_HB_N1 F23 FMC_HB_N2 E22 FMC_HB_N3 F26 FMC_HB_N4 E25 FMC_HB_N5 K29 FMC_HB_N6 J28 FMC_HB_N7 F29 FMC_HB_N8 E28 FMC_HB_N9 K32 FMC_HB_N10 J31 FMC_HB_N11 F32 FMC_HB_N12 E31 FMC_HB_N13 K35 FMC_HB_N14 J34 FMC_HB_N15 AV16 AP17 AK10 AL11 J8 AH14 AD19 AM7 F6 AC18 AJ18 AF19 AD14 AH20 AL17 AT25 AP20 AP19 AN21 AP23 AP22 AP24 AH13 AV12 AT11 AW10 AF13 AE14 AF12 AG11 AP10 AL10 AC13 AV9 AU10 AT9 AP13 AH12 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank A 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 254 Chapter 2: Board Components Components and Interfaces Table 250. FMC Connector Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 7) Board Reference (J10) Schematic Signal Name Arria V GX FPGA I/O Standard Pin Number Description F35 FMC_HB_N16 K38 FMC_HB_N17 J37 FMC_HB_N18 E34 FMC_HB_N19 F38 FMC_HB_N20 E37 FMC_HB_N21 K25 FMC_HB_P0 J24 FMC_HB_P1 F22 FMC_HB_P2 E21 FMC_HB_P3 F25 FMC_HB_P4 E24 FMC_HB_P5 K28 FMC_HB_P6 J27 FMC_HB_P7 F28 FMC_HB_P8 E27 FMC_HB_P9 K31 FMC_HB_P10 J30 FMC_HB_P11 F31 FMC_HB_P12 E30 FMC_HB_P13 K34 FMC_HB_P14 J33 FMC_HB_P15 F34 FMC_HB_P16 K37 FMC_HB_P17 J36 FMC_HB_P18 E33 FMC_HB_P19 F37 FMC_HB_P20 E36 FMC_HB_P21 D30 FMC_JTAG_TDI D31 FMC_JTAG_TDO D33 FMC_JTAG_TMS G7 FMC_LA_N0 D9 FMC_LA_N1 H8 FMC_LA_N2 G10 FMC_LA_N3 H11 FMC_LA_N4 D12 FMC_LA_N5 C11 FMC_LA_N6 AN12 AC12 AD12 AT12 AK12 AL13 AJ13 AW12 AU11 AW11 AG13 AE13 AG12 AH11 AR10 AM10 AD13 AW9 AV10 AU9 AR13 AJ12 AP12 AD11 AE12 AU12 AL12 AM13 -- -- -- AN16 AV13 AT15 AW14 AK8 AN7 AL9 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS FMC data bus HPC bank B 2.5-V CMOS JTAG data in 2.5-V CMOS JTAG data out 2.5-V CMOS JTAG mode select 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Components and Interfaces 255 Table 250. FMC Connector Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 7) Board Reference (J10) Schematic Signal Name Arria V GX FPGA I/O Standard Pin Number Description H14 FMC_LA_N7 G13 FMC_LA_N8 D15 FMC_LA_N9 C15 FMC_LA_N10 H17 FMC_LA_N11 G16 FMC_LA_N12 D18 FMC_LA_N13 C19 FMC_LA_N14 H20 FMC_LA_N15 G19 FMC_LA_N16 D21 FMC_LA_N17 C23 FMC_LA_N18 H23 FMC_LA_N19 G22 FMC_LA_N20 H26 FMC_LA_N21 G25 FMC_LA_N22 D24 FMC_LA_N23 H29 FMC_LA_N24 G28 FMC_LA_N25 D27 FMC_LA_N26 C27 FMC_LA_N27 H32 FMC_LA_N28 G31 FMC_LA_N29 H35 FMC_LA_N30 G34 FMC_LA_N31 H38 FMC_LA_N32 G37 FMC_LA_N33 G6 FMC_LA_P0 D8 FMC_LA_P1 H7 FMC_LA_P2 G9 FMC_LA_P3 H10 FMC_LA_P4 D11 FMC_LA_P5 C10 FMC_LA_P6 H13 FMC_LA_P7 G12 FMC_LA_P8 D14 FMC_LA_P9 C14 FMC_LA_P10 AU6 AN9 AG17 AV7 AK15 AJ16 AK14 AT13 AL16 AK24 AN15 AC16 AV22 AR16 AG22 AD21 AV18 AJ25 AK23 AK22 AG23 AG24 AN26 AE27 AG27 AD23 AC24 AP16 AW13 AU15 AW15 AL8 AP7 AM9 AT6 AP9 AH17 AV6 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 256 Chapter 2: Board Components Components and Interfaces Table 250. FMC Connector Pin Assignments, Schematic Signal Names, and Functions (Part 7 of 7) Board Reference (J10) Schematic Signal Name Arria V GX FPGA I/O Standard Pin Number Description H16 FMC_LA_P11 G15 FMC_LA_P12 D17 FMC_LA_P13 C18 FMC_LA_P14 H19 FMC_LA_P15 G18 FMC_LA_P16 D20 FMC_LA_P17 C22 FMC_LA_P18 H22 FMC_LA_P19 G21 FMC_LA_P20 H25 FMC_LA_P21 G24 FMC_LA_P22 D23 FMC_LA_P23 H28 FMC_LA_P24 G27 FMC_LA_P25 D26 FMC_LA_P26 C26 FMC_LA_P27 H31 FMC_LA_P28 G30 FMC_LA_P29 H34 FMC_LA_P30 G33 FMC_LA_P31 H37 FMC_LA_P32 G36 FMC_LA_P33 F1 FMC_M2C_PG H2 FMC_PRSNT C30 FMC_SCL C31 FMC_SDA AL15 AK16 AL14 AU13 AM16 AL24 AP15 AD16 AW22 AT16 AH22 AC22 AW18 AK25 AL23 AL22 AH23 AH24 AP26 AF27 AH27 AD24 AD25 -- -- -- -- 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS FMC data bus LPC bank A 2.5-V CMOS Power good input 2.5-V CMOS FMC module present 2.5-V CMOS Management serial clock line 2.5-V CMOS Management serial data line Table 249 lists the FMC interface component reference and manufacturing information. Table 251. FMC Connector Component Reference and Manufacturing Information Board Reference J10 Description FMC pitch socket array assembly connector Manufacturer Samtec Manufacturing Part Number ASP-134486-01 Manufacturer Website www.samtec.com Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components Components and Interfaces 257 Bull's Eye Connector The development board comes with Samtec's Bull's Eye system, which includes four SMA cables along with the insertion tool to insert the cables into the connector. The Bull's Eye high-density RF interconnect system allows many channels to be compacted into a small area on a printed circuit board at a comparable performance to SMA connectors. The cables allow you to monitor only two differential signals at a time. You can move the cables from one channel to another using the tool included with this board. 1 You can order more cables from www.samtec.com and these cable systems can be reused on other boards. f For specific instructions on how to install the connector to the board and insert the cables into the connector, refer to Samtec's web page regarding this system. Table 254 lists the Bull's eye connector pin assignments, signal names, and functions. Table 252. Bull's Eye Connector Pin Assignments, Schematic Signal Names, and Functions Board Reference (J16) Schematic Signal Name 4 BULLSEYE_SMA_CLKN 3 BULLSEYE_SMA_CLKP 21 SMA_A_10G_RX_N0 2 SMA_A_10G_RX_N1 22 SMA_A_10G_RX_P0 1 SMA_A_10G_RX_P1 7 SMA_A_6G_RX_N2 11 SMA_A_6G_RX_P2 13 SMA_A_TX_L15_N 12 SMA_A_TX_L15_P 17 SMA_A_TX_R16_N 18 SMA_A_TX_R16_P 8 SMA_A_TX_R17_N 9 SMA_A_TX_R17_P 15 SMA_B_10G_RX_N1 16 SMA_B_10G_RX_P1 5 SMA_B_6G_RX_N0 6 SMA_B_6G_RX_P0 19 SMA_B_TX_L15_N 20 SMA_B_TX_L15_P 10 SMA_B_TX_R6_N 14 SMA_B_TX_R6_P Arria V GX FPGA Pin Number -- -- G2 H38 G1 H39 C2 C1 G36 G37 F4 F3 B4 B3 H38 H39 AC2 AC1 G36 G37 AB4 AB3 I/O Standard Description LVDS or 2.5-V Clock buffer LVDS or 2.5-V Clock buffer LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel LVDS or 2.5-V Transceiver channel November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 258 Chapter 2: Board Components Memory Table 249 lists the Bull's Eye connector component reference and manufacturing information. Table 253. Bull's Eye Connector Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Bull's Eye test point receptacle J16 Four CCA-25M cable assemblies Insertion/Extraction tool Samtec BAR-J-22 BE25S-01SP1-01.0-02-0152 CAT-EX-SCC-01 Manufacturer Website www.samtec.com Memory This section describes the development board's memory interface support and also their signal names, types, and connectivity relative to the Arria V GX FPGA. The development board has the following memory interfaces: DDR3 QDRII+ Flash f For more information about the memory interfaces, refer to the following documents: Timing Analysis section in volume 4 of the External Memory Interface Handbook. DDR, DDR2, and DDR3 SDRAM Design Tutorials section in volume 6 of the External Memory Interface Handbook. DDR3 DDR3A for FPGA 1 The development board supports a 16Mx72x8 bank DDR3 SDRAM interface on FPGA 1 for very high-speed sequential memory access. The 72-bit data bus consists of four x16 devices and one x8 device with a single address or command bus. This interface connects to the vertical I/O banks on the top edge of the FPGA and utilizes the memory soft controller. This memory interface is designed to run at a target frequency of 667 MHz for a maximum theoretical bandwidth of over 115.2 Gbps. The minimum frequency for this device is 667 MHz. The target Micron device is rated at 800 MHz with a CAS latency of 11. Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components Memory 259 Table 254 lists the DDR3A (x72 soft controller) pin assignments, signal names, and functions. The signal names and types are relative to the Arria V GX FPGA in terms of I/O setting and direction. Table 254. DDR3A Devices Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 5) Board Reference Schematic Signal Name DDR3A (U11, U18, U21, U28) N3 DDR3A_A0 P7 DDR3A_A1 P3 DDR3A_A2 N2 DDR3A_A3 P8 DDR3A_A4 P2 DDR3A_A5 R8 DDR3A_A6 R2 DDR3A_A7 T8 DDR3A_A8 R3 DDR3A_A9 L7 DDR3A_A10 R7 DDR3A_A11 N7 DDR3A_A12 T3 DDR3A_A13 M2 DDR3A_BA0 N8 DDR3A_BA1 M3 DDR3A_BA2 K3 DDR3A_CASN K9 DDR3A_CKE K7 DDR3A_CLK_N J7 DDR3A_CLK_P L2 DDR3A_CSN K1 DDR3A_ODT J3 DDR3A_RASN T2 DDR3A_RESETN L3 DDR3A_WEN DDR3A (U7) K3 DDR3A_A0 L7 DDR3A_A1 L3 DDR3A_A2 K2 DDR3A_A3 L8 DDR3A_A4 L2 DDR3A_A5 M8 DDR3A_A6 Arria V GX FPGA Pin Number I/O Standard Description M34 1.5-V SSTL Class I Address bus H25 1.5-V SSTL Class I Address bus F32 1.5-V SSTL Class I Address bus P28 1.5-V SSTL Class I Address bus L24 1.5-V SSTL Class I Address bus G32 1.5-V SSTL Class I Address bus R21 1.5-V SSTL Class I Address bus K30 1.5-V SSTL Class I Address bus D21 1.5-V SSTL Class I Address bus M30 1.5-V SSTL Class I Address bus J28 1.5-V SSTL Class I Address bus M21 1.5-V SSTL Class I Address bus G28 1.5-V SSTL Class I Address bus M31 1.5-V SSTL Class I Address bus G30 1.5-V SSTL Class I Bank address bus T24 1.5-V SSTL Class I Bank address bus K34 1.5-V SSTL Class I Bank address bus D32 1.5-V SSTL Class I Row address select K29 1.5-V SSTL Class I Column address select F34 1.5-V SSTL Class I Differential output clock E34 1.5-V SSTL Class I Differential output clock F31 1.5-V SSTL Class I Chip select E33 1.5-V SSTL Class I On-die termination enable A32 1.5-V SSTL Class I Row address select J31 1.5-V SSTL Class I Reset G29 1.5-V SSTL Class I Write enable M34 1.5-V SSTL Class I Address bus H25 1.5-V SSTL Class I Address bus F32 1.5-V SSTL Class I Address bus P28 1.5-V SSTL Class I Address bus L24 1.5-V SSTL Class I Address bus G32 1.5-V SSTL Class I Address bus R21 1.5-V SSTL Class I Address bus November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 260 Chapter 2: Board Components Memory Table 254. DDR3A Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5) Board Reference Schematic Signal Name M2 DDR3A_A7 N8 DDR3A_A8 M3 DDR3A_A9 H7 DDR3A_A10 M7 DDR3A_A11 K7 DDR3A_A12 N3 DDR3A_A13 J2 DDR3A_BA0 K8 DDR3A_BA1 J3 DDR3A_BA2 G3 DDR3A_CASN G9 DDR3A_CKE G7 DDR3A_CLK_N F7 DDR3A_CLK_P H2 DDR3A_CSN B7 DDR3A_DM8 B3 DDR3A_DQ64 C7 DDR3A_DQ65 C2 DDR3A_DQ66 C8 DDR3A_DQ67 E3 DDR3A_DQ68 E8 DDR3A_DQ69 D2 DDR3A_DQ70 E7 DDR3A_DQ71 D3 DDR3A_DQS_N8 C3 DDR3A_DQS_P8 G1 DDR3A_ODT F3 DDR3A_RASN N2 DDR3A_RESETN H3 DDR3A_WEN H8 DDR3A_ZQ05 DDR3A (U11) E7 DDR3A_DM6 D3 DDR3A_DM7 E3 DDR3A_DQ48 F7 DDR3A_DQ49 F2 DDR3A_DQ50 F8 DDR3A_DQ51 H3 DDR3A_DQ52 Arria V GX FPGA Pin Number K30 D21 M30 J28 M21 G28 M31 G30 T24 K34 D32 K29 F34 E34 F31 P22 B22 L22 C22 N22 E22 J22 A23 F22 D23 C23 E33 A32 J31 G29 -- I/O Standard Description 1.5-V SSTL Class I Address bus 1.5-V SSTL Class I Address bus 1.5-V SSTL Class I Address bus 1.5-V SSTL Class I Address bus 1.5-V SSTL Class I Address bus 1.5-V SSTL Class I Address bus 1.5-V SSTL Class I Address bus 1.5-V SSTL Class I Bank address bus 1.5-V SSTL Class I Bank address bus 1.5-V SSTL Class I Bank address bus 1.5-V SSTL Class I Row address select 1.5-V SSTL Class I Column address select 1.5-V SSTL Class I Differential output clock 1.5-V SSTL Class I Differential output clock 1.5-V SSTL Class I Chip select 1.5-V SSTL Class I Write mask byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data strobe N byte lane 1.5-V SSTL Class I Data strobe P byte lane 1.5-V SSTL Class I On-die termination enable 1.5-V SSTL Class I Row address select 1.5-V SSTL Class I Reset 1.5-V SSTL Class I Write enable 1.5-V SSTL Class I ZQ impedance calibration M32 1.5-V SSTL Class I Write mask byte lane D31 1.5-V SSTL Class I Write mask byte lane T26 1.5-V SSTL Class I Data bus byte lane R24 1.5-V SSTL Class I Data bus byte lane D25 1.5-V SSTL Class I Data bus byte lane T25 1.5-V SSTL Class I Data bus byte lane E25 1.5-V SSTL Class I Data bus byte lane Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Memory 261 Table 254. DDR3A Devices Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5) Board Reference Schematic Signal Name H8 DDR3A_DQ53 G2 DDR3A_DQ54 H7 DDR3A_DQ55 D7 DDR3A_DQ56 C3 DDR3A_DQ57 C8 DDR3A_DQ58 C2 DDR3A_DQ59 A7 DDR3A_DQ60 A2 DDR3A_DQ61 B8 DDR3A_DQ62 A3 DDR3A_DQ63 G3 DDR3A_DQS_N6 B7 DDR3A_DQS_N7 F3 DDR3A_DQS_P6 C7 DDR3A_DQS_P7 L8 DDR3A_ZQ04 DDR3A (U18) E7 DDR3A_DM4 D3 DDR3A_DM5 E3 DDR3A_DQ32 F7 DDR3A_DQ33 F2 DDR3A_DQ34 F8 DDR3A_DQ35 H3 DDR3A_DQ36 H8 DDR3A_DQ37 G2 DDR3A_DQ38 H7 DDR3A_DQ39 D7 DDR3A_DQ40 C3 DDR3A_DQ41 C8 DDR3A_DQ42 C2 DDR3A_DQ43 A7 DDR3A_DQ44 A2 DDR3A_DQ45 B8 DDR3A_DQ46 A3 DDR3A_DQ47 G3 DDR3A_DQS_N4 B7 DDR3A_DQS_N5 F3 DDR3A_DQS_P4 C7 DDR3A_DQS_P5 Arria V GX FPGA Pin Number N24 G25 K24 F23 J23 G23 C24 F24 R23 G24 M23 B25 E24 A25 D24 -- I/O Standard Description 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data strobe N byte lane 1.5-V SSTL Class I Data strobe N byte lane 1.5-V SSTL Class I Data strobe P byte lane 1.5-V SSTL Class I Data strobe P byte lane 1.5-V SSTL Class I ZQ impedance calibration E27 1.5-V SSTL Class I Write mask byte lane A26 1.5-V SSTL Class I Write mask byte lane P27 1.5-V SSTL Class I Data bus byte lane B27 1.5-V SSTL Class I Data bus byte lane R27 1.5-V SSTL Class I Data bus byte lane C27 1.5-V SSTL Class I Data bus byte lane M27 1.5-V SSTL Class I Data bus byte lane H27 1.5-V SSTL Class I Data bus byte lane N27 1.5-V SSTL Class I Data bus byte lane K27 1.5-V SSTL Class I Data bus byte lane J26 1.5-V SSTL Class I Data bus byte lane D26 1.5-V SSTL Class I Data bus byte lane K25 1.5-V SSTL Class I Data bus byte lane G26 1.5-V SSTL Class I Data bus byte lane T27 1.5-V SSTL Class I Data bus byte lane F26 1.5-V SSTL Class I Data bus byte lane R26 1.5-V SSTL Class I Data bus byte lane C26 1.5-V SSTL Class I Data bus byte lane T28 1.5-V SSTL Class I Data strobe N byte lane N26 1.5-V SSTL Class I Data strobe N byte lane R28 1.5-V SSTL Class I Data strobe P byte lane M26 1.5-V SSTL Class I Data strobe P byte lane November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 262 Chapter 2: Board Components Memory Table 254. DDR3A Devices Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5) Board Reference Schematic Signal Name L8 DDR3A_ZQ03 DDR3A (U21) E7 DDR3A_DM2 D3 DDR3A_DM3 E3 DDR3A_DQ16 F7 DDR3A_DQ17 F2 DDR3A_DQ18 F8 DDR3A_DQ19 H3 DDR3A_DQ20 H8 DDR3A_DQ21 G2 DDR3A_DQ22 H7 DDR3A_DQ23 D7 DDR3A_DQ24 C3 DDR3A_DQ25 C8 DDR3A_DQ26 C2 DDR3A_DQ27 A7 DDR3A_DQ28 A2 DDR3A_DQ29 B8 DDR3A_DQ30 A3 DDR3A_DQ31 G3 DDR3A_DQS_N2 B7 DDR3A_DQS_N3 F3 DDR3A_DQS_P2 C7 DDR3A_DQS_P3 L8 DDR3A_ZQ01 DDR3A (U28) E7 DDR3A_DM0 D3 DDR3A_DM1 E3 DDR3A_DQ0 F7 DDR3A_DQ1 F2 DDR3A_DQ2 F8 DDR3A_DQ3 H3 DDR3A_DQ4 H8 DDR3A_DQ5 G2 DDR3A_DQ6 H7 DDR3A_DQ7 D7 DDR3A_DQ8 C3 DDR3A_DQ9 C8 DDR3A_DQ10 Arria V GX FPGA Pin Number -- I/O Standard Description 1.5-V SSTL Class I ZQ impedance calibration M32 1.5-V SSTL Class I Write mask byte lane D31 1.5-V SSTL Class I Write mask byte lane D30 1.5-V SSTL Class I Data bus byte lane C29 1.5-V SSTL Class I Data bus byte lane R30 1.5-V SSTL Class I Data bus byte lane A29 1.5-V SSTL Class I Data bus byte lane L30 1.5-V SSTL Class I Data bus byte lane A28 1.5-V SSTL Class I Data bus byte lane J30 1.5-V SSTL Class I Data bus byte lane B28 1.5-V SSTL Class I Data bus byte lane J29 1.5-V SSTL Class I Data bus byte lane C28 1.5-V SSTL Class I Data bus byte lane L28 1.5-V SSTL Class I Data bus byte lane F28 1.5-V SSTL Class I Data bus byte lane N29 1.5-V SSTL Class I Data bus byte lane D28 1.5-V SSTL Class I Data bus byte lane M29 1.5-V SSTL Class I Data bus byte lane M28 1.5-V SSTL Class I Data bus byte lane P30 1.5-V SSTL Class I Data strobe N byte lane T29 1.5-V SSTL Class I Data strobe N byte lane N30 1.5-V SSTL Class I Data strobe P byte lane R29 1.5-V SSTL Class I Data strobe P byte lane -- 1.5-V SSTL Class I ZQ impedance calibration M32 1.5-V SSTL Class I Write mask byte lane D31 1.5-V SSTL Class I Write mask byte lane N33 1.5-V SSTL Class I Data bus byte lane N31 1.5-V SSTL Class I Data bus byte lane N34 1.5-V SSTL Class I Data bus byte lane L31 1.5-V SSTL Class I Data bus byte lane N32 1.5-V SSTL Class I Data bus byte lane J34 1.5-V SSTL Class I Data bus byte lane P31 1.5-V SSTL Class I Data bus byte lane J32 1.5-V SSTL Class I Data bus byte lane A30 1.5-V SSTL Class I Data bus byte lane C30 1.5-V SSTL Class I Data bus byte lane B30 1.5-V SSTL Class I Data bus byte lane Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Memory 263 Table 254. DDR3A Devices Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5) Board Reference Schematic Signal Name C2 DDR3A_DQ11 A7 DDR3A_DQ12 A2 DDR3A_DQ13 B8 DDR3A_DQ14 A3 DDR3A_DQ15 G3 DDR3A_DQS_N0 B7 DDR3A_DQS_N1 F3 DDR3A_DQS_P0 C7 DDR3A_DQS_P1 L8 DDR3A_ZQ01 Arria V GX FPGA Pin Number H31 B31 E31 A31 C31 M33 B33 L33 N30 -- I/O Standard Description 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data strobe N byte lane 1.5-V SSTL Class I Data strobe N byte lane 1.5-V SSTL Class I Data strobe P byte lane 1.5-V SSTL Class I Data strobe P byte lane 1.5-V SSTL Class I ZQ impedance calibration DDR3B/C for FPGA 2 The development board supports a 16Mx64x8 bank DDR3 SDRAM interface on FPGA 2 for very high-speed sequential memory access. The 64-bit data bus consists of four x16 devices with a single address or command bus. This interface connects to the vertical I/O banks on the top edge of the FPGA. This DDR3 SDRAM has two interface options. The first option is a x32 interface using a memory hard controller. The second option is a x64 interface using a memory soft controller. Table 255 lists the DDR3B (x32 hard controller) pin assignments, signal names, and functions. The signal names and types are relative to the Arria V GX FPGA in terms of I/O setting and direction. Table 255. DDR3 x32 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3) Board Reference Schematic Signal Name DDR3B (U6, U12) N3 DDR3B_A0 P7 DDR3B_A1 P3 DDR3B_A2 N2 DDR3B_A3 P8 DDR3B_A4 P2 DDR3B_A5 R8 DDR3B_A6 R2 DDR3B_A7 T8 DDR3B_A8 R3 DDR3B_A9 L7 DDR3B_A10 R7 DDR3B_A11 N7 DDR3B_A12 Arria V GX FPGA Pin Number I/O Standard Description B31 1.5-V SSTL Class I Address bus A30 1.5-V SSTL Class I Address bus A31 1.5-V SSTL Class I Address bus A32 1.5-V SSTL Class I Address bus A33 1.5-V SSTL Class I Address bus B33 1.5-V SSTL Class I Address bus H31 1.5-V SSTL Class I Address bus J31 1.5-V SSTL Class I Address bus C31 1.5-V SSTL Class I Address bus D31 1.5-V SSTL Class I Address bus C32 1.5-V SSTL Class I Address bus D32 1.5-V SSTL Class I Address bus N31 1.5-V SSTL Class I Address bus November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 264 Chapter 2: Board Components Memory Table 255. DDR3 x32 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3) Board Reference Schematic Signal Name T3 DDR3B_A13 M2 DDR3B_BA0 N8 DDR3B_BA1 M3 DDR3B_BA2 K3 DDR3B_CASN K9 DDR3B_CKE K7 DDR3B_CLK_N J7 DDR3B_CLK_P L2 DDR3B_CSN K1 DDR3B_ODT J3 DDR3B_RASN T2 DDR3B_RESETN L3 DDR3B_WEN L8 DDR3B_ZQ2 DDR3B (U6) E7 DDR3B_DM0 D3 DDR3B_DM1 E3 DDR3B_DQ0 F7 DDR3B_DQ1 F2 DDR3B_DQ2 F8 DDR3B_DQ3 H3 DDR3B_DQ4 H8 DDR3B_DQ5 G2 DDR3B_DQ6 H7 DDR3B_DQ7 D7 DDR3B_DQ8 C3 DDR3B_DQ9 C8 DDR3B_DQ10 C2 DDR3B_DQ11 A7 DDR3B_DQ12 A2 DDR3B_DQ13 B8 DDR3B_DQ14 A3 DDR3B_DQ15 G3 DDR3B_DQS_N0 B7 DDR3B_DQS_N1 F3 DDR3B_DQS_P0 C7 DDR3B_DQS_P1 DDR3B (U12) E7 DDR3B_DM2 Arria V GX FPGA Pin Number P31 M32 N32 J34 L33 E31 C30 B30 L34 L31 K34 G30 M33 -- I/O Standard Description 1.5-V SSTL Class I Address bus 1.5-V SSTL Class I Bank address bus 1.5-V SSTL Class I Bank address bus 1.5-V SSTL Class I Bank address bus 1.5-V SSTL Class I Row address select 1.5-V SSTL Class I Column address select 1.5-V SSTL Class I Differential output clock 1.5-V SSTL Class I Differential output clock 1.5-V SSTL Class I Chip select 1.5-V SSTL Class I On-die termination enable 1.5-V SSTL Class I Row address select 1.5-V SSTL Class I Reset 1.5-V SSTL Class I Write enable 1.5-V SSTL Class I ZQ impedance calibration J30 1.5-V SSTL Class I Write mask byte lane J29 1.5-V SSTL Class I Write mask byte lane B28 1.5-V SSTL Class I Data bus byte lane C29 1.5-V SSTL Class I Data bus byte lane R30 1.5-V SSTL Class I Data bus byte lane A29 1.5-V SSTL Class I Data bus byte lane A28 1.5-V SSTL Class I Data bus byte lane L30 1.5-V SSTL Class I Data bus byte lane D30 1.5-V SSTL Class I Data bus byte lane D29 1.5-V SSTL Class I Data bus byte lane L28 1.5-V SSTL Class I Data bus byte lane M28 1.5-V SSTL Class I Data bus byte lane H28 1.5-V SSTL Class I Data bus byte lane C28 1.5-V SSTL Class I Data bus byte lane D28 1.5-V SSTL Class I Data bus byte lane F28 1.5-V SSTL Class I Data bus byte lane M29 1.5-V SSTL Class I Data bus byte lane N29 1.5-V SSTL Class I Data bus byte lane P30 1.5-V SSTL Class I Data strobe N byte lane T29 1.5-V SSTL Class I Data strobe N byte lane N30 1.5-V SSTL Class I Data strobe P byte lane R29 1.5-V SSTL Class I Data strobe P byte lane J30 1.5-V SSTL Class I Write mask byte lane Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Memory 265 Table 255. DDR3 x32 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3) Board Reference Schematic Signal Name D3 DDR3B_DM3 E3 DDR3B_DQ16 F7 DDR3B_DQ17 F2 DDR3B_DQ18 F8 DDR3B_DQ19 H3 DDR3B_DQ20 H8 DDR3B_DQ21 G2 DDR3B_DQ22 H7 DDR3B_DQ23 D7 DDR3B_DQ24 C3 DDR3B_DQ25 C8 DDR3B_DQ26 C2 DDR3B_DQ27 A7 DDR3B_DQ28 A2 DDR3B_DQ29 B8 DDR3B_DQ30 A3 DDR3B_DQ31 G3 DDR3B_DQS_N2 B7 DDR3B_DQS_N3 F3 DDR3B_DQS_P2 C7 DDR3B_DQS_P3 Arria V GX FPGA Pin Number J29 P27 R27 H27 B27 C27 E27 M27 N27 C26 D26 K25 R26 T27 A26 F26 G26 T28 N26 R28 M26 I/O Standard Description 1.5-V SSTL Class I Write mask byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data bus byte lane 1.5-V SSTL Class I Data strobe N byte lane 1.5-V SSTL Class I Data strobe N byte lane 1.5-V SSTL Class I Data strobe P byte lane 1.5-V SSTL Class I Data strobe P byte lane Table 256 lists the DDR3C (x64 soft controller) pin assignments, signal names, and functions. The signal names and types are relative to the Arria V GX FPGA in terms of I/O setting and direction. Table 256. DDR3 x64 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3) Board Reference Schematic Signal Name DDR3C (U19, U22) N3 DDR3B_A0 P7 DDR3B_A1 P3 DDR3B_A2 N2 DDR3B_A3 P8 DDR3B_A4 P2 DDR3B_A5 R8 DDR3B_A6 R2 DDR3B_A7 T8 DDR3B_A8 R3 DDR3B_A9 Arria V GX FPGA Pin Number I/O Standard Description B31 1.5-V SSTL Class I Address bus A30 1.5-V SSTL Class I Address bus A31 1.5-V SSTL Class I Address bus A32 1.5-V SSTL Class I Address bus A33 1.5-V SSTL Class I Address bus B33 1.5-V SSTL Class I Address bus H31 1.5-V SSTL Class I Address bus J31 1.5-V SSTL Class I Address bus C31 1.5-V SSTL Class I Address bus D31 1.5-V SSTL Class I Address bus November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 266 Chapter 2: Board Components Memory Table 256. DDR3 x64 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3) Board Reference Schematic Signal Name L7 DDR3B_A10 R7 DDR3B_A11 N7 DDR3B_A12 T3 DDR3B_A13 M2 DDR3B_BA0 N8 DDR3B_BA1 M3 DDR3B_BA2 K3 DDR3B_CASN K9 DDR3B_CKE K7 DDR3B_CLK_N J7 DDR3B_CLK_P L2 DDR3B_CSN K1 DDR3B_ODT J3 DDR3B_RASN T2 DDR3B_RESETN L3 DDR3B_WEN DDR3C (U19) E7 DDR3C_DM0 D3 DDR3C_DM1 E3 DDR3C_DQ0 F7 DDR3C_DQ1 F2 DDR3C_DQ2 F8 DDR3C_DQ3 H3 DDR3C_DQ4 H8 DDR3C_DQ5 G2 DDR3C_DQ6 H7 DDR3C_DQ7 D7 DDR3C_DQ8 C3 DDR3C_DQ9 C8 DDR3C_DQ10 C2 DDR3C_DQ11 A7 DDR3C_DQ12 A2 DDR3C_DQ13 B8 DDR3C_DQ14 A3 DDR3C_DQ15 G3 DDR3C_DQS_N0 B7 DDR3C_DQS_N1 F3 DDR3C_DQS_P0 C7 DDR3C_DQS_P1 Arria V GX FPGA Pin Number C32 D32 N31 P31 M32 N32 J34 L33 E31 C30 B30 L34 L31 K34 G30 M33 I/O Standard Description 1.5-V SSTL Class I Address bus 1.5-V SSTL Class I Address bus 1.5-V SSTL Class I Address bus 1.5-V SSTL Class I Address bus 1.5-V SSTL Class I Bank address bus 1.5-V SSTL Class I Bank address bus 1.5-V SSTL Class I Bank address bus 1.5-V SSTL Class I Row address select 1.5-V SSTL Class I Column address select 1.5-V SSTL Class I Differential output clock 1.5-V SSTL Class I Differential output clock 1.5-V SSTL Class I Chip select 1.5-V SSTL Class I On-die termination enable 1.5-V SSTL Class I Row address select 1.5-V SSTL Class I Reset 1.5-V SSTL Class I Write enable M21 1.5-V SSTL Class I Write mask byte lane B22 1.5-V SSTL Class I Write mask byte lane D20 1.5-V SSTL Class I Data bus byte lane H21 1.5-V SSTL Class I Data bus byte lane D21 1.5-V SSTL Class I Data bus byte lane J21 1.5-V SSTL Class I Data bus byte lane A21 1.5-V SSTL Class I Data bus byte lane G21 1.5-V SSTL Class I Data bus byte lane A22 1.5-V SSTL Class I Data bus byte lane C20 1.5-V SSTL Class I Data bus byte lane A23 1.5-V SSTL Class I Data bus byte lane E22 1.5-V SSTL Class I Data bus byte lane L22 1.5-V SSTL Class I Data bus byte lane C22 1.5-V SSTL Class I Data bus byte lane N22 1.5-V SSTL Class I Data bus byte lane F22 1.5-V SSTL Class I Data bus byte lane P22 1.5-V SSTL Class I Data bus byte lane J22 1.5-V SSTL Class I Data bus byte lane B21 1.5-V SSTL Class I Data strobe N byte lane D23 1.5-V SSTL Class I Data strobe N byte lane A20 1.5-V SSTL Class I Data strobe P byte lane C23 1.5-V SSTL Class I Data strobe P byte lane Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Memory 267 Table 256. DDR3 x64 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3) Board Reference Schematic Signal Name L8 DDR3B_ZQ4 DDR3C (U22) E7 DDR3C_DM2 D3 DDR3C_DM3 E3 DDR3C_DQ16 F7 DDR3C_DQ17 F2 DDR3C_DQ18 F8 DDR3C_DQ19 H3 DDR3C_DQ20 H8 DDR3C_DQ21 G2 DDR3C_DQ22 H7 DDR3C_DQ23 D7 DDR3C_DQ24 C3 DDR3C_DQ25 C8 DDR3C_DQ26 C2 DDR3C_DQ27 A7 DDR3C_DQ28 A2 DDR3C_DQ29 B8 DDR3C_DQ30 A3 DDR3C_DQ31 G3 DDR3C_DQS_N2 B7 DDR3C_DQS_N3 F3 DDR3C_DQS_P2 C7 DDR3C_DQS_P3 L8 DDR3B_ZQ3 Arria V GX FPGA Pin Number -- I/O Standard Description 1.5-V SSTL Class I ZQ impedance calibration J23 1.5-V SSTL Class I Write mask byte lane D25 1.5-V SSTL Class I Write mask byte lane C24 1.5-V SSTL Class I Data bus byte lane M23 1.5-V SSTL Class I Data bus byte lane B24 1.5-V SSTL Class I Data bus byte lane R23 1.5-V SSTL Class I Data bus byte lane G24 1.5-V SSTL Class I Data bus byte lane G23 1.5-V SSTL Class I Data bus byte lane F24 1.5-V SSTL Class I Data bus byte lane F23 1.5-V SSTL Class I Data bus byte lane R24 1.5-V SSTL Class I Data bus byte lane G25 1.5-V SSTL Class I Data bus byte lane T26 1.5-V SSTL Class I Data bus byte lane E25 1.5-V SSTL Class I Data bus byte lane N24 1.5-V SSTL Class I Data bus byte lane K24 1.5-V SSTL Class I Data bus byte lane T25 1.5-V SSTL Class I Data bus byte lane P24 1.5-V SSTL Class I Data bus byte lane E24 1.5-V SSTL Class I Data strobe N byte lane B25 1.5-V SSTL Class I Data strobe N byte lane D24 1.5-V SSTL Class I Data strobe P byte lane A25 1.5-V SSTL Class I Data strobe P byte lane -- 1.5-V SSTL Class I ZQ impedance calibration Table 257 lists the DDR3 component reference and manufacturing information. Table 257. DDR3 Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number U6, U11, U12, U18, U19, U21, U22, U28 U7 32M×16×8, 2 Gb, DDR3 memory 16M×8×8, 1 Gb, DDR3 memory Micron Micron MT41J128M16HA-125:D MT41J128M8JP-125:G Manufacturer Website www.micron.com www.micron.com November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 268 Chapter 2: Board Components Memory QDRII+ The development board supports a burst-of-4 QDRII+ SRAM memory device for very-high-speed, low-latency memory access. The QDRII+ has a x36 interface, providing device addressing of up to a 36 Mb. The QDRII+ has separate read and write data ports with DDR signaling at up to 550 MHz. The pinout and footprint is compatible with a burst-of-2 QDRII SSRAM memory device. The FPGA can support up to 400 MHz QDRII data. Table 258 lists the QDRII+ pin assignments, signal names, and functions. Table 258. QDRII+ Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3) Board Reference (U8) Schematic Signal Name R9 QDRII_A0 R8 QDRII_A1 B4 QDRII_A2 B8 QDRII_A3 C5 QDRII_A4 C7 QDRII_A5 N5 QDRII_A6 N6 QDRII_A7 N7 QDRII_A8 P4 QDRII_A9 P5 QDRII_A10 P7 QDRII_A11 P8 QDRII_A12 R3 QDRII_A13 R4 QDRII_A14 R5 QDRII_A15 R7 QDRII_A16 A9 QDRII_A17 A3 QDRII_A18 A10 QDRII_A19 A2 QDRII_A20 B7 QDRII_BWSN0 A7 QDRII_BWSN1 A5 QDRII_BWSN2 B5 QDRII_BWSN3 R6 QDRII_C_N P6 QDRII_C_P A1 QDRII_CQ_N A11 QDRII_CQ_P P10 QDRII_D0 Arria V GX FPGA Pin Number I/O Standard Description AB29 1.8-V HSTL Address bus AC29 1.8-V HSTL Address bus AF28 1.8-V HSTL Address bus AG28 1.8-V HSTL Address bus AK29 1.8-V HSTL Address bus AL29 1.8-V HSTL Address bus AH28 1.8-V HSTL Address bus AJ28 1.8-V HSTL Address bus AD28 1.8-V HSTL Address bus AP28 1.8-V HSTL Address bus AJ27 1.8-V HSTL Address bus AP27 1.8-V HSTL Address bus AM27 1.8-V HSTL Address bus AG27 1.8-V HSTL Address bus AE27 1.8-V HSTL Address bus AC24 1.8-V HSTL Address bus AD26 1.8-V HSTL Address bus AN26 1.8-V HSTL Address bus AJ25 1.8-V HSTL Address bus AT32 1.8-V HSTL Address bus AU32 1.8-V HSTL Address bus AK27 1.8-V HSTL Write byte write select 0 AB25 1.8-V HSTL Write byte write select 1 AM25 1.8-V HSTL Write byte write select 2 AV24 1.8-V HSTL Write byte write select 3 AG24 1.8-V HSTL Clock N AD23 1.8-V HSTL Clock P AR21 1.8-V HSTL Echo clock N AT21 1.8-V HSTL Echo clock P AE28 1.8-V HSTL Write data bus Arria V GX FPGA Development Board Reference Manual November 2013 Altera Corporation Downloaded from Arrow.com. Chapter 2: Board Components Memory 269 Table 258. QDRII+ Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3) Board Reference (U8) Schematic Signal Name N11 QDRII_D1 M11 QDRII_D2 K10 QDRII_D3 J11 QDRII_D4 G11 QDRII_D5 E10 QDRII_D6 D11 QDRII_D7 C11 QDRII_D8 N10 QDRII_D9 M9 QDRII_D10 L9 QDRII_D11 J9 QDRII_D12 G10 QDRII_D13 F9 QDRII_D14 D10 QDRII_D15 C9 QDRII_D16 B9 QDRII_D17 B3 QDRII_D18 C3 QDRII_D19 D2 QDRII_D20 F3 QDRII_D21 G2 QDRII_D22 J3 QDRII_D23 L3 QDRII_D24 M3 QDRII_D25 N2 QDRII_D26 C1 QDRII_D27 D1 QDRII_D28 E2 QDRII_D29 G1 QDRII_D30 J1 QDRII_D31 K2 QDRII_D32 M1 QDRII_D33 N1 QDRII_D34 P2 QDRII_D35 H1 QDRII_DOFFN A6 QDRII_K_N B6 QDRII_K_P P11 QDRII_Q0 Arria V GX FPGA Pin Number I/O Standard Description AB27 1.8-V HSTL Write data bus AB28 1.8-V HSTL Write data bus AM28 1.8-V HSTL Write data bus AC27 1.8-V HSTL Write data bus AD27 1.8-V HSTL Write data bus AR28 1.8-V HSTL Write data bus AU28 1.8-V HSTL Write data bus AV28 1.8-V HSTL Write data bus AW29 1.8-V HSTL Write data bus AW28 1.8-V HSTL Write data bus AR27 1.8-V HSTL Write data bus AT27 1.8-V HSTL Write data bus AU27 1.8-V HSTL Write data bus AN27 1.8-V HSTL Write data bus AV27 1.8-V HSTL Write data bus AW27 1.8-V HSTL Write data bus AH27 1.8-V HSTL Write data bus AC25 1.8-V HSTL Write data bus AF27 1.8-V HSTL Write data bus AD25 1.8-V HSTL Write data bus AG26 1.8-V HSTL Write data bus AH26 1.8-V HSTL Write data bus AE26 1.8-V HSTL Write data bus AG25 1.8-V HSTL Write data bus AH25 1.8-V HSTL Write data bus AP26 1.8-V HSTL Write data bus AN25 1.8-V HSTL Write data bus AK25 1.8-V HSTL Write data bus AT26 1.8-V HSTL Write data bus AU26 1.8-V HSTL Write data bus AT25 1.8-V HSTL Write data bus AW25 1.8-V HSTL Write data bus AW26 1.8-V HSTL Write data bus AL26 1.8-V HSTL Write data bus AV25 1.8-V HSTL Write data bus AN24 1.8-V HSTL DLL enable AE25 1.8-V HSTL Write clock N AF25 1.8-V HSTL Write clock P AD24 1.8-V HSTL Read data bus November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 270 Chapter 2: Board Components Memory Table 258. QDRII+ Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3) Board Reference (U8) Schematic Signal Name M10 QDRII_Q1 L11 QDRII_Q2 K11 QDRII_Q3 J10 QDRII_Q4 F11 QDRII_Q5 E11 QDRII_Q6 C10 QDRII_Q7 B11 QDRII_Q8 P9 QDRII_Q9 N9 QDRII_Q10 L10 QDRII_Q11 K9 QDRII_Q12 G9 QDRII_Q13 F10 QDRII_Q14 E9 QDRII_Q15 D9 QDRII_Q16 B10 QDRII_Q17 B2 QDRII_Q18 D3 QDRII_Q19 E3 QDRII_Q20 F2 QDRII_Q21 G3 QDRII_Q22 K3 QDRII_Q23 L2 QDRII_Q24 N3 QDRII_Q25 P3 QDRII_Q26 B1 QDRII_Q27 C2 QDRII_Q28 E1 QDRII_Q29 F1 QDRII_Q30 J2 QDRII_Q31 K1 QDRII_Q32 L1 QDRII_Q33 M2 QDRII_Q34 P1 QDRII_Q35 A8 QDRII_RPSN A4 QDRII_WPSN Arria V GX FPGA Pin Number I/O Standard Description AT24 1.8-V HSTL Read data bus AU24 1.8-V HSTL Read data bus AL24 1.8-V HSTL Read data bus AE24 1.8-V HSTL Read data bus AF24 1.8-V HSTL Read data bus AH24 1.8-V HSTL Read data bus AW23 1.8-V HSTL Read data bus AW24 1.8-V HSTL Read data bus AP24 1.8-V HSTL Read data bus AT23 1.8-V HSTL Read data bus AU23 1.8-V HSTL Read data bus AP23 1.8-V HSTL Read data bus AD22 1.8-V HSTL Read data bus AE23 1.8-V HSTL Read data bus AL23 1.8-V HSTL Read data bus AT22 1.8-V HSTL Read data bus AU22 1.8-V HSTL Read data bus AW22 1.8-V HSTL Read data bus AV21 1.8-V HSTL Read data bus AW21 1.8-V HSTL Read data bus AH23 1.8-V HSTL Read data bus AE22 1.8-V HSTL Read data bus AF22 1.8-V HSTL Read data bus AP22 1.8-V HSTL Read data bus AW19 1.8-V HSTL Read data bus AW20 1.8-V HSTL Read data bus AH22 1.8-V HSTL Read data bus AT20 1.8-V HSTL Read data bus AU20 1.8-V HSTL Read data bus AK21 1.8-V HSTL Read data bus AU19 1.8-V HSTL Read data bus AV19 1.8-V HSTL Read data bus AN21 1.8-V HSTL Read data bus AE21 1.8-V HSTL Read data bus AG21 1.8-V HSTL Read data bus AR25 1.8-V HSTL Read port select AK24 1.8-V HSTL Write port select Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components Memory 271 Table 257 lists the QDRII+ component reference and manufacturing information. Table 259. QDRII+ Component Reference and Manufacturing Information Board Reference U8 Description SRAM 72-Mb QDRII+ 4-word burst 2M×36, 533 MHz Manufacturer Renesas Technology Corp. Manufacturing Part Number R1QDA7236ABG_19IB0 Manufacturer Website www.am.renesas.com Flash The development board supports a 1 Gb CFI-compatible synchronous flash device for non-volatile storage of FPGA configuration data, board information, test application data, and user code space. This device is part of the shared FM bus that connects to the flash memory and MAX II CPLD EPM2210 System Controller. This 16-bit data memory interface can sustain burst read operations at up to 52 MHz for a throughput of 832 Mbps. The write performance is 270 µs for a single word while the erase time is 800 ms for a 128 K main block. Table 260 lists the flash pin assignments, signal names, and functions. The signal names and types are relative to the Arria V GX FPGA in terms of I/O setting and direction. Table 260. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2) Board Reference (U4) Schematic Signal Name F6 FLASH_ADVN B4 FLASH_CEN E6 FLASH_CLK F8 FLASH_OEN F7 FLASH_RDYBSYN D4 FLASH_RESETN G8 FLASH_WEN C6 FLASH_WPN A1 FM_A1 B1 FM_A2 C1 FM_A3 D1 FM_A4 D2 FM_A5 A2 FM_A6 C2 FM_A7 A3 FM_A8 B3 FM_A9 C3 FM_A10 D3 FM_A11 C4 FM_A12 A5 FM_A13 Arria V GX FPGA Pin Number I/O Standard Description AK30 1.8-V Address valid AU30 1.8-V Chip enable AL31 1.8-V Clock AN30 1.8-V Output enable AK32 1.8-V Ready AL34 1.8-V Reset AN32 1.8-V Write enable -- 1.8-V Write protect AT30 1.8-V Address bus AL30 1.8-V Address bus AP32 1.8-V Address bus AM34 1.8-V Address bus AJ33 1.8-V Address bus AK33 1.8-V Address bus AW33 1.8-V Address bus AH30 1.8-V Address bus AR30 1.8-V Address bus AP33 1.8-V Address bus AM31 1.8-V Address bus AP31 1.8-V Address bus AR31 1.8-V Address bus November 2013 Altera Corporation Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. 272 Chapter 2: Board Components Memory Table 260. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2) Board Reference (U4) Schematic Signal Name B5 FM_A14 C5 FM_A15 D7 FM_A16 D8 FM_A17 A7 FM_A18 B7 FM_A19 C7 FM_A20 C8 FM_A21 A8 FM_A22 G1 FM_A23 H8 FM_A24 B6 FM_A25 B8 FM_A26 F2 FM_D0 E2 FM_D1 G3 FM_D2 E4 FM_D3 E5 FM_D4 G5 FM_D5 G6 FM_D6 H7 FM_D7 E1 FM_D8 E3 FM_D9 F3 FM_D10 F4 FM_D11 F5 FM_D12 H5 FM_D13 G7 FM_D14 E7 FM_D15 Arria V GX FPGA Pin Number I/O Standard Description AT31 1.8-V Address bus AE29 1.8-V Address bus AG30 1.8-V Address bus AV31 1.8-V Address bus AW30 1.8-V Address bus AW31 1.8-V Address bus AV30 1.8-V Address bus AT29 1.8-V Address bus AU29 1.8-V Address bus AP30 1.8-V Address bus AN29 1.8-V Address bus AL32 1.8-V Address bus AK31 1.8-V Address bus AC22 1.8-V Data bus AH20 1.8-V Data bus AG22 1.8-V Data bus AN20 1.8-V Data bus AP20 1.8-V Data bus AV22 1.8-V Data bus AG23 1.8-V Data bus AN22 1.8-V Data bus AH21 1.8-V Data bus AD21 1.8-V Data bus AN23 1.8-V Data bus AM21 1.8-V Data bus AL22 1.8-V Data bus AG20 1.8-V Data bus AK22 1.8-V Data bus AK23 1.8-V Data bus Table 261 lists the flash component reference and manufacturing information. Table 261. Flash Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number U4 512-Mbit synchronous flash Numonyx PC28F512P30BF Manufacturer Website www.numonyx.com Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components Power Supply 273 Power Supply A laptop style DC power input provides power to the development board. The input voltage must be in the range of 14 V to 20 V. The DC voltage is then stepped down to various power rails used by the board components and installed into the HSMC connectors. An on-board multi-channel analog-to-digital converter (ADC) measures both the voltage and current for several specific board rails. The power utilization is displayed on a graphical user interface (GUI) that can graph power consumption versus time. Power Distribution System Figure 211 on page 274 shows the power distribution system on the development board. Regulator efficiencies and sharing are reflected in the currents shown, which are conservative absolute maximum levels. November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 274 Chapter 2: Board Components Power Supply Figure 211. Power Distribution System Power Sequencing VCC/VCCP/VCCR_GXB/VCCT_GXB/VCCL_GXB VCCPD/VCCPGM/VCCAUX/VCCA_FPLL, VCCA_GXB 12 V, 2.093 A LTM4628 Dual 8A 1.2 V, 6.582 A Switching Regulator (+/- 3%) 2.5 V, 5.861 A VCCH_GXB/VCCD_FPLL 1.2 V, 4.512 A RSENSE 1.2 V, 2.070 A BEAD 2.5 V, 0.141 A RSENSE BEAD 2.5 V, 0.704 A 2.5 V, 2.542 A RSENSE 2.5 V, 1.226 A A5_VCCR_GXB VCCR_GXB, VCCL_GXB A5_VCCT_GXB VCCR_GXB A5_VCCA VCCA_FPLL, VCCAUX A5_VCCA VCCA_GXB A5_VCCPD_PGM_IO VCCPD, VCCPGM A5_VCCPD_PGM_IO FPGA VCCIO 2.5-V Banks LT3026 1.5 A LDO (+/- 3%) RSENSE RSENSE 2.5 V, 1.249 A 2.5 V Flash VDDQ, ENET VDD, EPM2210 VCCIO2, NB6L11S, 6 Oscillators 1.5 V, 1.133 A A5_VCCD_PLL VCCD_FPLL, VCCH_GXB, VCCBAT 1.8 V, 0.693 A A5_VCCIO_1.8V FPGA VCCIO 1.8-V Banks 12 V, 1.466 A 1.8 V, 3.614 A LTM4628 Dual 8A Switching Regulator (+/- 3%) 1.5 V, 5.864 A RSENSE 1.8 V, 1.688 A 1.5 V, 1.080 A 1.8 V Flash, QDR_VDD, EPM2210, EPCQ A5_VCCIO_1.5V FPGA VCCIO 1.5-V Bank 8 1.345 A 1.5 V, 4.734 A VREF_DDR3A TPS51200 0.75 V, 0.050 A VREF_DDR3B TPS51200 0.75 V, 0.050 A LTM4618 Switching Regulator RSENSE 1.8 - 3.3 V, 4.500 A 1.5 V DDR3 VDD, EZ_USB VTT_DDR3A VTT_DDR3B A5_VCCIO_FMC VCCIO_FMC 3.426 A 0.018 A PCIe Motherboard 12 V, 5.5 A Maximum DC INPUT 19 V LTC3855 Dual Channel Controller Ideal Diode Multiplexer 12 V, 8.651 A 0.220 A Ideal Diode Multiplexer 3.3 V, 2.451 A LTC3880 Switching Regulator (+/- 3%) RSENSE LT3029 Channel 1 LDO LT3029 Channel 2 LDO PCIe Motherboard 3.3 V, 3.0 A Maximum Ideal Diode Multiplexer LTC3025-1 0.5 A Linear Regulator 12V_ATX 12V_ATX, 5.971 A LTM4601 12 V, 2.971 A Switching Regulator 1.1 V, 29.902 A A5_VCCINT FPGA VCC BEAD 5.0 V, 0.018 A A5_VCCP FPGA VCCP 5.0 V Character LCD, MAX3378, Regulator Bias 5.37 V, 0.220 A ADC_MONITOR LT2418 x 2 3.3 V, 2.198 A 3.3 V ICS8543 CLK Buffer, EZ-USB, SDI, OSC, Display Port 1.0 V, 0.253 A 1.0 V ENET_DVDD 12 V, 3.0 A 3.3 V, 9.4 A 12V_ATX HSMA, HSMB, FMC 3.3V_ATX HSMA. HSMB, SFP+, FMC Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components Power Supply 275 Power Measurement There are 16 power supply rails that have on-board voltage, current, and wattage sense capabilities using 24-bit differential ADC devices. Precision sense resistors split the ADC devices and rails from the primary supply plane for the ADC to measure voltage and current. A SPI bus connects these ADC devices to the MAX II CPLD EPM2210 System Controller as well as the Arria V GX FPGA. Figure 212 shows the block diagram for the power measurement circuitry. Figure 212. Power Measurement Circuit Supply #0-14 Feedback R SENSE Power Supply Load #0-14 Embedded USB-Blaster EPM570 To User PC Power GUI USB PHY JTAG Chain E RW 14-pin RS 2x16 LCD D(0:7) EPM2210 Arria V FPGA SCK DSI 8 Ch. DSO CSn LTC2418 SCK 8 Ch. DSI DSO CSn Table 262 lists the targeted rails. The schematic signal name column specifies the name of the rail being measured while the device pin column specifies the devices attached to the rail. If no subnet is named, the power is the total output power for that voltage. Table 262. Power Measurement Rails (Part 1 of 3) Switch Schematic Signal Name GUI Name A5A_VCCR_VCCL_GXB 1 A5A_VCCT_GXB A5A_XCVR_GXB 2 A5A_VCCA_2.5V A5A_VCCA Voltage 1.1V 1.1V 2.5V 2.5V Device Pin VCCR_GXB, VCCL_GXB VCCT_GXB VCCA_FPLL VCC_AUX, VCCA_GXB Description XCVR analog receive and clock network XCVR transmitter power PLL analog power Auxiliary November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 276 Chapter 2: Board Components Power Supply Table 262. Power Measurement Rails (Part 2 of 3) Switch Schematic Signal Name GUI Name 3 A5A_VCCPD_PGM_IO_2.5V A5A_VCCPD/PGM 4 A5A_VCCINT 5 A5A_VCCIO_1.5V A5A_VCCINT A5A_VCCIO_1.5V 6 A5A_VCCD_PLL_1.5V A5A_VCCD_PLL 7 A5A_VCCIO_1.8V A5A_VCCIO_1.8V A5B_VCCR_VCCL_GXB 8 A5B_VCCT_GXB 9 A5B_VCCA_2.5V A5B_XCVR_GXB A5B_VCCA 10 A5B_VCCPD_PGM_IO_2.5V A5B_VCCPD/PGM 11 A5B_VCCINT 12 A5B_VCCIO_1.5V A5B_VCCINT A5B_VCCIO_1.5V Voltage 2.5 V 2.5 V 2.5 V 1.1 V 1.5 V 1.5 V Device Pin VCCPD VCCPGM VCCIO_4A, VCCIO_4B, VCCIO_4C, VCCIO_4D, VCCIO_7A, VCCIO_7B, VCCIO_7C, VCCIO_7D VCC, VCCP VCCIO_8A, VCCIO_8B, VCCIO_8C, VCCIO_8D VCCD_FPLL 1.5 V VCCH_GXB 1.8 V 1.1 V 1.1 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 1.1 V 1.5 V VCCIO_3A, VCCIO_3B, VCCIO_3C, VCCIO_3D VCCR_GXB, VCCL_GXB VCCT_GXB VCCA_FPLL VCC_AUX VCCPD VCCPGM VCCIO_3A, VCCIO_3B, VCCIO_7A, VCCIO_7B, VCCIO_7C, VCCIO_7D VCC VCCIO_8A, VCCIO_8B, VCCIO_8C, VCCIO_8D Description I/O pre-drivers Configuration I/O VCC I/O banks 4 and 7 FPGA core and periphery power VCCIO bank 8 (DDR3A) PLL digital power XCVR block level transmit buffers VCC I/O bank 3 (QDRII+) XCVR analog receive and clock network XCVR transmitter power PLL analog power Auxiliary I/O pre-drivers Configuration I/O VCC I/O banks 3A, 3B and 7 FPGA core and periphery power VCCIO bank 8 (DDR3A) Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Chapter 2: Board Components Statement of China-RoHS Compliance 277 Table 262. Power Measurement Rails (Part 3 of 3) Switch Schematic Signal Name GUI Name 13 A5B_VCCD_PLL_1.5V A5B_VCCD_PLL 14 A5_VCCIO_FMC A5_VCCIO_FMC Voltage 1.5 V 1.5 V 1.5 V/ 1.8 V/ 2.5 V/ 3.3 V Device Pin VCCD_FPLL VCCH_GXB VCCIO_3C, VCCIO_3D, VCCIO_4A, VCCIO_4C, VCCIO_4D Description PLL digital power XCVR block level transmit buffers I/O supply bank (FMC port) Table 263 lists the power measurement ADC component reference and manufacturing information. Table 263. Power Measurement ADC Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website U29, U31 8-channel differential 24-bit ADC Linear Technology LTC2418CGN#PBF www.linear.com Statement of China-RoHS Compliance Table 264 lists hazardous substances included with the kit. Table 264. Table of Hazardous Substances' Name and Concentration Notes (1), (2) Part Name Lead (Pb) Cadmium (Cd) Hexavalent Chromium (Cr6+) Mercury (Hg) Polybrominated biphenyls (PBB) Polybrominated diphenyl Ethers (PBDE) Arria V development board X* 0 0 0 0 0 12 V power supply 0 0 0 0 0 0 Type A-B USB cable 0 0 0 0 0 0 User guide 0 0 0 0 0 0 Notes to Table 264: (1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the SJ/T11363-2006 standard. (2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS. November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual 278 Chapter 2: Board Components Statement of China-RoHS Compliance Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation Additional Information This chapter provides additional information about the document and Altera. Document Revision History The following table lists the revision history for this document. Date November 2013 July 2012 Version Changes Revised the I/O standard for PCI Express pin assignments in Table 241. 1.1 Revised the I/O standard for SFP+ module interface pin assignments in Table 248. Revised the FPGA pin numbers for the user-defined LED in Table 229. 1.0 Initial release. How to Contact Altera To locate the most up-to-date information about Altera products, refer to the following table. Contact (1) Contact Method Address Technical support Website www.altera.com/support Technical training Website Email www.altera.com/training custrain@altera.com Product literature Website www.altera.com/literature Nontechnical support (general) Email nacomp@altera.com (software licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Bold Type with Initial Capital Letters bold type Italic Type with Initial Capital Letters Meaning Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI. Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file. Indicate document titles. For example, Stratix IV Design Guidelines. November 2013 Altera Corporation Downloaded from Arrow.com. Arria V GX FPGA Development Board Reference Manual Info2 Visual Cue italic type Initial Capital Letters "Subheading Title" Courier type r 1., 2., 3., and a., b., c., and so on 1 h f m c w Additional Information Typographic Conventions Meaning Indicates variables. For example, n + 1. Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file. Indicate keyboard keys and menu names. For example, the Delete key and the Options menu. Quotation marks indicate references to sections in a document and titles of Quartus II Help topics. For example, "Typographic Conventions." Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. The suffix n denotes an active-low signal. For example, resetn. Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI). An angled arrow instructs you to press the Enter key. Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets indicate a list of items when the sequence of the items is not important. The hand points to information that requires special attention. The question mark directs you to a software help system with related information. The feet direct you to another document or website with related information. The multimedia icon directs you to a related multimedia presentation. A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document. Arria V GX FPGA Development Board Reference Manual Downloaded from Arrow.com. November 2013 Altera Corporation