 | Altera Nios II Flash Programmer User Guide This user guide provides comprehensive instructions for developers utilizing the Altera Nios II Flash Programmer. It details the process of programming flash memory with various types of data, including software executables (.elf files), FPGA configuration data (.sof files), and arbitrary binary files. The document also covers critical aspects such as understanding flash programmer design, configuring target boards, and utilizing command-line utilities for efficient flash programming. |
 | Nios® V Embedded Processor Design Handbook A comprehensive guide for designing and developing embedded systems with the Nios® V processor using Intel FPGA tools like Quartus Prime and Platform Designer. Covers hardware integration, software development, debugging, and booting methods. |
 | Altera Embedded Peripherals IP User Guide for Intel FPGAs Explore Altera's comprehensive Embedded Peripherals IP User Guide for Intel FPGAs. Covers Avalon-ST, SPI, eSPI, DMA, UART, FIFO, Memory Cores, and more, integrated with Platform Designer. |
 | Nios® V Embedded Processor Design Handbook A comprehensive guide to designing, configuring, and debugging embedded systems using the Nios® V processor with Altera FPGA technology, covering hardware and software development flows with Quartus® Prime and Platform Designer. |
 | Nios II Simple Socket Server on CVGT FPGA Development Kit Guide A guide to setting up and running the Nios II Simple Socket Server on the Altera Cyclone V GT FPGA Development Kit, demonstrating embedded system development with NicheStack TCP/IP and MicroC/OS-II. |
 | FPGA AI Suite: Getting Started Guide This guide provides an overview of the FPGA AI Suite, installation instructions, prerequisites, and a tutorial for running AI inference on FPGAs. It covers topics like setting up the development environment, using the compiler, and deploying AI models. |
 | Agilex 5 FPGAs and SoCs: External Memory Interfaces (EMIF) IP User Guide This user guide provides comprehensive information on the Agilex 5 FPGA External Memory Interfaces (EMIF) IP, detailing its architecture, protocols, and design flow. It covers support for DDR4, LPDDR4, and LPDDR5 memory protocols, along with guidance on pin assignments, simulation, timing closure, and debugging. Essential for engineers working with high-speed memory interfaces on Agilex 5 devices. |
 | Agilex 7 M-Series FPGA Network-on-Chip (NoC) User Guide This user guide provides comprehensive information on the Network-on-Chip (NoC) subsystem integrated into Intel's Agilex 7 M-Series FPGAs. It details the architecture, design flow, and usage of the NoC for high-bandwidth data movement between FPGA fabric and memory resources like HBM2e and DDR5, utilizing the Quartus Prime Pro Edition software. |