ADRF5051 Silicon SP4T Switch, Nonreflective, 9kHz to 20GHz

Features

• Wideband frequency range: 9kHz to 20GHz
• Nonreflective design with on-chip 50Ω terminations
• Low insertion loss: 0.7dB typical to 6GHz, 0.9dB typical to 12GHz, 1.2dB typical to 20GHz
• High isolation: 53dB typical to 6GHz, 49dB typical to 12GHz, 47dB typical to 20GHz
• High linearity: Input P0.1dB: 34dBm typical, Input IP3: 55dBm typical
• High RF power handling: Through path: 33dBm up to 20 GHz, Terminated path: 18dBm up to 20 GHz
• Switching on and off time: 8.5µs
• 0.1dB settling time: 15µs
• All off-state control
• Logic select control
• Single-supply operation with derated power handling
• No low frequency spurs, and no internal voltage generation
• 24-terminal, 3mm × 3mm, land grid array (LGA) package
• Pin compatible with ADRF5042, ADRF5043, ADRF5048, ADRF5049, and ADRF5050

Applications

• Test instrumentation
• Military radios, radars, and electronic counter measures (ECMs)
• Microwave radios and very small aperture terminals (VSATs)

Functional Block Diagram

A block diagram illustrates the ADRF5051 with its internal components including a driver, 50Ω terminations, and RF ports (EN, V1, V2, RFC, RF1, RF2, RF3, RF4, VDD, VSS, GND).

General Description

The ADRF5051 is a nonreflective SP4T switch manufactured using a silicon on insulator (SOI) process. It operates from 9kHz to 20GHz with low insertion loss and high isolation. The device offers high RF input power handling capabilities. It can operate with a dual-supply voltage (+3.3V and -3.3V) or a single positive supply voltage (VDD) with VSS tied to ground, though performance may be derated in single-supply mode. The ADRF5051 features complimentary metal-oxide semiconductor (CMOS) and low voltage transistor-to-transistor logic (LVTTL)-compatible controls, including Enable (EN) and Logic Select (LS) pins. The EN pin activates an all-off state, while the LS pin inverts the throw port selection logic. The device is supplied in a 24-terminal, 3mm × 3mm, RoHS-compliant land grid array (LGA) package and operates from -40°C to +105°C.

Specifications

Key specifications include:

Frequency Range

0.009 MHz to 20000 MHz

Insertion Loss (RFC to RFx, On)

• 9kHz to 6GHz: 0.7dB typical
• 6GHz to 12GHz: 0.9dB typical
• 12GHz to 20GHz: 1.2dB typical

Isolation (RFC to RFx, Off)

• 9kHz to 6GHz: 55dB typical
• 6GHz to 12GHz: 54dB typical
• 12GHz to 20GHz: 48dB typical

Isolation (RFx to RFx)

• 9kHz to 6GHz: 53dB typical
• 6GHz to 12GHz: 49dB typical
• 12GHz to 20GHz: 47dB typical

Return Loss

• RFC: 23dB typical (9kHz to 6GHz)
• RFx (On): 23dB typical (9kHz to 6GHz)
• RFx (Off): 20dB typical (9kHz to 6GHz)

Switching

• Rise and Fall Time: 3µs
• On and Off Time: 8.5µs
• 0.1dB Settling Time: 15µs

Input Linearity

• 0.1dB Power Compression (P0.1dB): 34dBm typical
• Third-Order Intercept (IP3): 55dBm typical
• Second-Order Intercept (IP2): 105dBm typical

Supply Current

• Positive Supply Current (IDD): 160µA typical
• Negative Supply Current (Iss): 540µA typical

Digital Control Inputs

• Voltage Low (VINL): 0V to 0.8V
• Voltage High (VINH): 1.2V to 3.3V
• Current Low (IINL): <1µA
• Current High (IINH): 2.8µA (V1, V2), 40µA (EN), 37µA (LS)

Recommended Operating Conditions

• Supply Voltage (VDD): 3.15V to 3.45V
• Supply Voltage (VSS): -3.45V to -3.15V
• RF Power Handling (Through Path): 33dBm typical (at 1MHz to 20GHz, TCASE = 85°C)
• RF Power Handling (Terminated Path): 18dBm typical (at 1MHz to 20GHz, TCASE = 85°C)
• Hot Switching (RFC): 30dBm typical
• Hot Switching (RFx): 18dBm typical
• Case Temperature: -40°C to +105°C

Note: RF power handling derates at higher temperatures. For detailed derating information, refer to Figure 2.

Absolute Maximum Ratings

Exceeding these ratings may cause permanent damage:

• Supply Voltage (VDD): -0.3V to +3.6V
• Supply Voltage (VSS): -3.6V to +0.3V
• Digital Control Inputs Voltage: -0.3V to VDD + 0.3V
• Digital Control Inputs Current: 3mA
• RF Input Power (Through Path): 33.5dBm
• RF Input Power (Terminated Path): 18.5dBm
• RF Input Power (Hot Switching RFC): 30.5dBm
• RF Input Power (Hot Switching RFx): 18.5dBm
• Junction Temperature (TJ): 135°C
• Storage Range: -65°C to +150°C
• Reflow Temperature: 260°C

Electrostatic Discharge (ESD) Ratings

The ADRF5051 is an ESD-sensitive device. Proper ESD precautions are necessary.

• Human Body Model (HBM): 3000V (RFx and RFC Pins), 3500V (Supply and Control Pins)
• Charged Device Model (CDM): 500V

Pin Configuration and Function Descriptions

The ADRF5051 has a 24-terminal LGA package. Key pins include:

• EN: Enable Input
• LS: Logic Select Input
• V1, V2: Control Inputs
• RFC: RF Common Port
• RF1, RF2, RF3, RF4: RF Throw Ports
• VDD: Positive Supply Voltage
• VSS: Negative Supply Voltage
• GND: Ground
• EPAD: Exposed Pad (connect to RF and DC ground)

The EPAD must be connected to the RF and DC ground of the PCB.

Interface Schematics

Schematics are provided for the RFC/RF ports, V1/V2 control, EN control, LS control, VDD supply, and VSS supply pins, illustrating typical internal circuitry and recommended external components like capacitors and resistors.

Typical Performance Characteristics

Performance graphs illustrate:

• Insertion Loss for RFC to RFx (On) vs. Frequency
• Insertion Loss for RFC to RF1 (On) vs. Frequency over Temperature
• Return Loss for RFC vs. Frequency
• Return Loss for RFx (On) vs. Frequency
• Return Loss for RFx (Off) vs. Frequency
• Isolation for RFC to RFx (Off) vs. Frequency
• Isolation for RFC to RFx (Off) vs. Frequency (RF3 On)
• Isolation for RFC to RFx (Off) vs. Frequency (RF4 On)
• Channel to Channel Isolation (RFx to RFx) vs. Frequency
• Input P0.1dB vs. Frequency
• Input IP3 vs. Frequency

Theory of Operation

The ADRF5051 utilizes CMOS-/LVTTL-compatible control inputs (EN, LS, V1, V2) to manage the RF paths. The logic levels on V1 and V2 determine the selected RF throw port, while other ports are in isolation. The LS pin offers logic inversion for port selection. When the EN pin is high, all RF paths are in isolation, and the RFx ports are terminated internally to 50Ω, making RFC reflective. The device supports both dual-supply and single-supply operation. For dual-supply, VDD and VSS are required. For single-supply, VDD is used, and VSS is connected to ground, with potential derating in performance.

Power Supply Recommendations:

1. Connect GND to ground.
2. Power up VDD and VSS, with VSS powered after VDD to manage current transients.
3. Apply control voltages to digital inputs (EN, LS, V1, V2) after VDD is powered. Avoid powering control inputs before VDD to prevent damage to ESD structures. Use series resistors for current limiting if necessary. Consider pull-up or pull-down resistors for control pins if the controller output is in a high impedance state.
4. Apply RF input signal.

The power-down sequence is the reverse of the power-up sequence.

Applications Information

The ADRF5051 requires VDD and VSS supply pins, along with four control pins (LS, EN, V1, V2). Decoupling capacitors (100pF) are recommended for supply and control pins, placed close to the device. DC blocking capacitors may be needed on RF pins if they are biased differently from 0V. The device is designed for 50Ω characteristic impedance CPWG on PCBs. Recommended PCB trace design involves specific widths and clearances for optimal RF and thermal performance. Alternate PCB stack-ups can be accommodated with consultation from Analog Devices, Inc. Technical Support.

Back-to-Back Application

A back-to-back configuration can be achieved by connecting the V1 and V2 control pins together and hardwiring the LS pin of one device to GND and the LS pin of the other device to VDD. This setup allows for sequential switching operations.

Outline Dimensions

The device is available in a 24-terminal LGA package (CC-24-16), measuring 3mm × 3mm.

Ordering Guide

Note: Z = RoHS-Compliant Part.

Evaluation Boards