Objective
This code example demonstrates the functionality of the Capture feature of the Timer User Module of PSoC® 1.
Overview
Pulse width measurement is a feature needed in many embedded systems. There are several reasons to find the width of a given pulse. For example, one reason can be to measure the duration of a given event or to find the interval between the occurrences of two events.
There are different methods of Pulse Width Measurement, such as:
- The timer capture method, which is discussed in this code example.
- GPIO: Based on the GPIO interrupt that is generated whenever there is change in the GPIO state from last read by CPU.
- Loads/starts the timer in the assembly code of GPIO_ISR while the next read stops the timer. Thereby, the pulse width can be calculated based on these values.
As shown in Figure 1, the instances at which positive and negative edges occur for the test signal are recorded. The pulse width is calculated by finding the difference between these two values.
Principle
The principle of Pulse Width measurement can be understood by the simple state diagram shown in Figure 2. As seen from the figure, the system can be in any of the two states based on the edge of the test signal detected.
The 16-bit Timer is initially interrupted by the positive edge (which is the capture edge) of the test signal in State 1. The capture value is then stored and the edge is changed to negative edge (Negative edge detection by Timer). During the subsequent negative edge, which follows when the FSM is in State 2, the capture value corresponding to the negative edge is stored and the difference is the pulse width of the signal. The Timer is now changed to positive edge capture and the cycle follows by going to State 1 on the next positive edge.
User Module List and Placement
This table lists the user modules used in this example and the hardware resources occupied by each user module.
| User Module | Placement |
|---|---|
| Timer (16-bit) | DBB00 and DBB01 |
| PWM (optional) | DCB02 |
| LCD | Software |
User Module Parameter Settings
These tables show the user module parameter settings for each user module used in the example.
Timer Parameters
| Parameter | Value | Comments |
|---|---|---|
| Clock | VC2 | VC2 is used to generate a 1-MHz clock input to the Timer. This results in a resolution of measurement of 1 μs. |
| Period | 65535 | The period is set to 65535 to avoid any underflow between the two instances. |
| Capture | Row0 Input 2 | The input signal is routed to the capture input from P0[2] through Row0_Input2. |
| Interrupt Type | Capture | The timer generates an interrupt on a capture event. |
| ClockSync | Sync to SysClk | As the clock to the timer is derived from SysClk, the clock sync is set to "SyncToSysClk". |
PWM Parameters
| Parameter | Value | Comments |
|---|---|---|
| Clock | VC2 | Clock source for PWM is VC2. |
| Period | 250 | The period of the PWM generated signal set to 250, so that the output frequency is around 4 kHz. This is the test signal whose pulse width needs to be measured. |
| Pulsewidth | 100 | Test the pulse-width to be measured for verification. |
| Compare type | Less than | Compare value should be less than the set threshold. |
| ClockSync | Sync to SysClk | Clock should be synchronized to SysClk. |
LCD Parameters
| Parameter | Value | Comments |
|---|---|---|
| LCDPort | Port2 | Port 2 is used for LCD connection. |
| BarGraph | Disable | Bar graph feature is disabled. |
Notes
- Any of the associated part numbers for this example support the above resources and hence can be used to implement this design.
- The PWM is used only to generate a test signal to verify the operation. This can be avoided and a generic test signal from an external function generator can be used to feed input at P0.2. However, make sure the frequency of such a signal is within the measurable range (here the timer is fed by VC2 = 1 MHz, therefore the pulse frequency should be less than 1 MHz).
Global Resources
Important Global Resources:
| Parameter | Value | Comments |
|---|---|---|
| VC1 | 12 | VC1 = 24 MHz/12 = 2 MHz |
| VC2 | 2 | VC2 = VC1 / 2 = 1 MHz |
| CPU Clock | 24 MHz | Sets CPU clock to 24 MHz. |
Chip View under PSoC Designer™
The Chip View diagram shows the interconnection of various user modules (Timer, PWM, DCB) and global resources within the PSoC architecture, including external wire connections.
Hardware Connections
The Capture input to the Timer User Module is provided from P0.2. The test signal whose pulse width is to be measured is provided on P0.1 from the PWM User Module or by an external signal source.
The example is tested on the CY3210 – PSoC Eval1 board.
The hardware connection comprises of the following:
- Connect wire between P0.1 to P0.2, which feeds the test signal generated in PSoC to the Timers for measurement.
Notes
- The CPU system clock frequency should be high when compared to the range of pulse width to be measured. This is because the edges from the test signal can be missed when the controller is servicing the Timer Capture ISR. Therefore, note that when this example is cloned for another chip, the CPU_clock should be fixed to SysClk/1.
The following schematic diagram shows the Pulse Width Measurement.
Operation
Rising Edge Operation
Using the API Timer_wReadCompareValue(), the timer value at the moment of the rising edge is stored in the variable CapturePosEdge.
Using the statement, Timer_FUNC_LSB_REG |= 0x80;, we set the 7th bit of the function register of the timer. By doing this, we change the capture type to falling edge. The falling edge flag is also set. Hence, the next time the interrupt is generated, the falling edge state is visited.
Falling Edge Operation
Using the API Timer_wReadCompareValue(), the timer value at the moment of the falling edge is stored into the variable CaptureNegEdge.
Using the statement, Timer_FUNC_LSB_REG &= ~0x80;, we clear the 7th bit of the Function register of the timer. By doing this, we change the capture type to rising edge. The falling edge flag is cleared, the pulse width is calculated, and the data available flag is set.
Conclusion
The pulse width of the test signal is displayed on the LCD. In this example, a value of 064 (hex equivalent of 100) is displayed on the LCD. To test the validity, one can vary the pulse width in the PWM User Module and reprogram the PSoC. This results in a new value being updated on the LCD during the next operation. Alternatively, any test signal whose pulse width needs to be measured can be fed to P0.2.
Upgrade Information
As the ljmp instruction to the C ISR for the Timer16 User Module is placed inside the user code markers within the TimerINT.asm file, this change is preserved when the project is generated and built. If the source file for the TimerINT.asm file changes in a future release of PSoC Designer, this instruction may get overwritten. So, if you have upgraded PSoC Designer and find that this example is not working, check the following:
Open the TimerINT.asm file and check if there is an ljmp _TimerCaptureISR instruction present in the user code area in the _Timer_ISR function. If not, add this instruction within the user code markers.
Document History
| Revision | ECN | Orig. of Change | Submission Date | Description of Change |
|---|---|---|---|---|
| ** | 2819817 | PRKR | 12/02/2009 | New example project. 1. Figure 1 and Overview section were added. 2. State Diagram explaining the two functional states were shown in Figure 2. 3. A new chip view in PSoC Designer was added. 4. Figure 3 shows the Functional Diagram of the project. |
| *A | 3110066 | UMRK | 12/13/2010 | 1. Explanation of different methods to measure pulse width and the reason for the choice of method in the given example project. 2. Inclusion of state diagram which explains the flow of the project. 3. Inclusion of waveforms and modification of diagrams for better clarity in setup. |
| *B | 3242304 | UMRK | 04/27/2011 | Obsolete document. |
| *C | 3598234 | KUK | 01/16/2013 | Change status from Obsolete to Active. Updated Software Version as "PSoC® Designer™ 5.3". Removed attachment file “Pulse_Width_Measurement”. |
| *D | 3972748 | KUK | 04/18/2013 | Updated PD version to 5.4. |
| *E | 4274584 | MSUR | 02/07/2014 | Updated template. |
| *F | 5669200 | DIMA | 03/23/2017 | Updated template. |
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