CE95400 - Watchdog Timer Reset and Interrupt for PSoC® 41xx/42xx Devices
Objective
This example demonstrates how to use the watchdog timer in PSoC 41xx/42xx devices to both reset the system and wake up from the Deep Sleep low power mode.
Overview
There are three examples that can run on the CY8CKIT-042 Pioneer kit; however, these can be ported to other boards that contain LEDs and buttons.
- Project #1 shows how to reset the system when the program is out-of-control due to unexpected inputs or conditions. It also shows how to store log data into flash before reset, which can be read with PSoC Programmer™ for fault analysis.
- Project #2 shows how to wake the system from deep sleep, which is a critical function for low-power application design.
- Project #3 combines functions of above two projects to demonstrate the cascade feature of the watchdog timer.
Description of Figure 1: Watchdog Block Diagram for PSoC 4100/4200 Devices. This diagram illustrates the watchdog timer architecture, showing three cascaded watchdog timers (WDT0, WDT1, WDT2) connected to the LFCLK. WDT0 and WDT1 are 16-bit counters, while WDT2 is a 32-bit counter. Each timer has a counter, match value, mode configuration, and generates interrupt or reset signals. Cascade connections between timers are shown, leading to final INTERRUPT and RESET outputs.
Requirements
- Tool: PSoC Creator 3.0 SP2 or later version.
- Programming Language: C (GCC 4.7.3), ARM® Cortex®-M0 Assembler
- Associated Parts: PSoC 4100/4200 family
- Related Hardware: CY8CKIT-042
Design
For PSoC 41xx/42xx devices, the watchdog timer (WDT) counts the 32-kHz internal clock "LFCLK". When the counter value equals the MATCH register value, the WDT generates an interrupt. If the counter is cleared before reaching the match value, the interrupt is prevented. This is known as "clearing the watchdog counter".
Rules for clearing the watchdog counter:
- Clearing must occur before the counter reaches its match value. For long functions, multiple clearing operations might be needed.
- Clearing should NOT be done within the Interrupt Service Routine (ISR). Doing so can lead to an out-of-control main loop while the interrupt still triggers periodically, and the ISR clearing the interrupt flag prevents a system reset.
Clearing the watchdog counter may require a short settling time, detailed in the device datasheet or technical reference manual. If clearing halts due to a fault (e.g., an infinite loop), the watchdog generates an interrupt. For PSoC 41xx/42xx devices, a system reset occurs after the third continuous unhandled interrupt. The system reset can be disabled to use the WDT for periodic interrupts, useful for waking the system from deep sleep.
Project #1 - Using Watchdog Timer to Reset the System
The watchdog timer is configured to generate an interrupt every second. The counter is cleared periodically in the main loop. If the SW2 button is pressed (simulating a fault), clearing stops. After three seconds (third unhandled interrupt), the system resets. The first watchdog interrupt stores log data (0-127) in the last row of internal flash for fault analysis via PSoC Programmer.
Three LEDs indicate system status:
- Green LED: ON when the system is working normally (SW2 not pressed).
- Blue LED: ON while SW2 is pressed.
- Red LED: ON for one second to indicate a watchdog timer reset.
Description of Figure 2: Creator Schematic for Project #1. This schematic shows the hardware connections for Project #1, including LEDs (Red, Green, Blue) connected to GPIO pins via resistors, and the SW2 button connected to a GPIO pin. The Watchdog Timer interrupt (WDT INT) is shown connected to an interrupt component.
Description of Figure 3: Firmware Flow for Project #1. This flowchart details the program logic. The main function handles power-up, button scanning (SW2), LED control (Green, Blue, Red based on status), watchdog initialization, clearing the watchdog counter, and enabling interrupts. The Watchdog ISR handles the interrupt, checks for log data storage, and exits. A system reset occurs if the watchdog is not cleared.
Project #2 - Wakeup from Deep Sleep
The watchdog timer is configured to generate an interrupt every 250 milliseconds, waking the system from deep sleep. The system then delays for 500 milliseconds using CyDelay functions before re-entering deep sleep.
Two LEDs indicate system status: The Green LED is ON during deep sleep. After waking by a watchdog interrupt, the Red LED turns ON during the firmware delay, then the Green LED turns ON again as the system enters deep sleep.
Description of Figure 4: Creator Schematic for Project #2. This schematic displays the hardware setup for Project #2, similar to Project #1, showing connections for Red, Green, and Blue LEDs, and the SW2 button to GPIO pins, along with the WDT INT signal.
Description of Figure 5: Firmware Flow for Project #2. This flowchart outlines the program logic for Project #2. The main function manages power-up, turning on the Green LED, initializing the watchdog, enabling interrupts, entering deep sleep, and turning on the Red LED upon wake-up. The Watchdog ISR handles interrupts, clears the flag, and exits.
Project #3 - Wakeup from Sleep with System Reset Enabled
The watchdog timer in PSoC 41xx/42xx devices features three 16-bit counters. Counter 0 and Counter 1 can be cascaded. Counter 0 generates an interrupt (no reset) on a match event. Counter 1 counts Counter 0's match events and generates an interrupt when its value matches its own match value. Three continuous unhandled interrupts trigger a system reset.
This example combines system reset and sleep wake-up. Counter 0 is set for a 250 ms interrupt to wake from deep sleep. Counter 1 is set for a 1-second interrupt. If not handled for three consecutive times, the system resets and logs data. LED indications are similar to Project #1.
Description of Figure 6: Creator Schematic for Project #3. This schematic shows the hardware configuration for Project #3, including connections for LEDs (Red, Green, Blue) and the SW2 button to GPIO pins, and the WDT INT signal.
Description of Figure 7: Firmware Flow for Project #3. This flowchart illustrates the program logic for Project #3. The main function handles power-up, reset checks, LED control, button scanning, clearing watchdog counters (0 and 1), entering deep sleep, and waking up. The Watchdog ISR handles interrupts from Counter 0 and Counter 1, checks for log data storage, and exits. The system's behavior depends on the SW2 button state.
Design Considerations
The pull-up resistor for the SW2 button is integrated within the chip's GPIO block; no external resistor is required. The CY8CKIT-042 uses a three-in-one LED package (Red, Green, Blue), which may be separated or replaced in other kits.
Hardware Setup
For basic kit board setup, refer to the corresponding Kit Guide. For specific kit setups:
- CY8CKIT-042: No special settings are required.
- CY8CKIT-038: This kit works with CY8CKIT-001 for PSoC 4 evaluation. Three of the four LEDs on CY8CKIT-001 can replace the RGB LED on CY8CKIT-042. Connect LEDs to pin sockets on CY8CKIT-001. SW1 or SW2 on CY8CKIT-001 can replace SW2 on CY8CKIT-042; connect them to pin sockets on CY8CKIT-001. Refer to the CY8CKIT-001 user guide for details.
Software Setup
No special software setup is required. All supported compilers can be used with any optimization.
Components
Table 1 lists the PSoC Creator Components used in this example and their hardware resources.
| Component | Hardware Resources |
|---|---|
| Digital Output Pin | Three PSoC 4 GPIO configured as digital output without pull-up or pull-down resistors |
| Digital Input Pin | One PSoC 4 GPIO configured as digital input with a pull-up resistor |
| Interrupt | One interrupt service routine with the highest priority |
| Global Signal | Connect the WDT interrupt to the Interrupt Component |
| Pin | Three pins for LED indicators; one pin for switch button detection |
Parameter Settings
Digital Output Pins:
Clear the "HW Connection" option to prevent build errors.
Description of Figure 8: Uncheck HW Connection. This figure shows a PSoC Creator interface element where the 'HW Connection' option for a digital output pin should be unchecked.
Digital Input Pins:
- Clear the "HW Connection" option to prevent build errors.
- Set the drive mode as "Resistive Pull Up" in the General Tab.
Description of Figure 9: Set Pull-up Resistor Drive Mode. This figure shows the PSoC Creator interface for setting the drive mode of a digital input pin to 'Resistive Pull Up'.
Design-Wide Resources
Figures 10 and 11 show the pin assignments for each example. No other design-wide resource needs to be changed from its default setting.
Description of Figure 10: Pin Assignment for Project #1 and Project #3. This figure displays a table mapping component names (LED_Blue, LED_Green, LED_Red, SW2) to their respective Port and Pin assignments for Projects #1 and #3.
Description of Figure 11: Pin Assignment for Project #2. This figure displays a table mapping component names (LED_Blue, LED_Green, LED_Red) to their respective Port and Pin assignments for Project #2.
Operation
Project #1 - Using the Watchdog Timer to Reset the System
- In the Workspace Explorer, right-click the “Project '1-Reset_System'” and select "Set As Active Project". See Figure 12.
- Build the project to generate the hex file.
- Connect the PC to CY8CKIT-042 J10 with the USB cable.
- Download the hex file to the PSoC 4 chip.
- Keep the USB cable connection for power supply.
- Observe LED status:
- Pressing the Reset button: Green LED blinks then turns ON, indicating system reset and normal operation.
- Pressing SW2: Green LED turns OFF, Blue LED turns ON. Releasing SW2 turns Green ON and Blue OFF. Blue LED indicates SW2 pressed.
- Holding SW2 for >3 seconds: Blue LED is ON, then Red LED turns ON for ~1 second, then Blue LED turns ON again. Red LED indicates a watchdog reset due to uncleared counter.
- Releasing SW2: Green LED turns ON.
- Holding SW2 again: Red LED turns ON periodically, indicating continuous resets.
- Launch PSoC Programmer from the Start menu (see Figure 13).
- In PSoC Programmer, click the "Read" button to read flash data (Figure 14).
- Scroll to the end of flash data to view logged data (Figure 16), which are incremental integers from 0 to 128, stored when a watchdog reset occurred.
Description of Figure 12: Choose Project #1 as Active Project. This figure shows a screenshot of the PSoC Creator Workspace Explorer with a right-click context menu displaying the option to 'Set As Active Project'.
Description of Figure 13: Launch PSoC Programmer. This figure shows the Windows Start menu with 'PSoC Programmer 3.21.1' highlighted.
Description of Figure 14: Read Operation in PSoC Programmer. This figure displays the PSoC Programmer interface, highlighting the 'Read' button and settings for reading flash data.
Description of Figure 15: Data in Beginning Rows of Flash. This figure shows a screenshot of the PSoC Programmer results window displaying hexadecimal data from the flash memory.
Description of Figure 16: Log Data after Watchdog Reset Happens. This figure shows the PSoC Programmer results window displaying logged data in hexadecimal format, typically incremental integers, stored in flash after a watchdog reset.
Project #2 - Wakeup from Deep Sleep
- In the Workspace Explorer, right-click “Project '2-Sleep_Wakeup'” and select "Set As Active Project" (see Figure 17).
- Build the project to generate the hex file.
- Connect the PC to CY8CKIT-042 J10 with the USB cable.
- Download the hex file to the PSoC 4 chip.
- Keep the USB cable connection for power supply.
- Observe LED status:
- Pressing the Reset button: Green LED blinks then turns ON, indicating system reset and normal operation.
- Later, Green LED turns OFF, Red LED turns ON. This repeats indefinitely. The Red LED indicates the system has woken from deep sleep via a watchdog interrupt.
Description of Figure 17: Choose Project #2 as Active Project. This figure shows a screenshot of the PSoC Creator Workspace Explorer with a right-click context menu displaying the option to 'Set As Active Project'.
Project #3 - Wakeup from Sleep with System Reset Enabled
- In Workspace Explorer, right-click “Project '3-Sleep_Wakeup_and_Reset_System'” and select "Set As Active Project" (see Figure 18).
- Build the project to generate the hex file.
- Connect the PC to CY8CKIT-042 J10 with the USB cable.
- Download the hex file to the PSoC 4 chip.
- Keep the USB cable connection for power supply.
- Observe LED status:
- Pressing the Reset button: Green LED blinks then turns ON, indicating system reset and normal operation.
- If SW2 is not pressed, the system behaves as in Project #2.
- If SW2 is pressed, the system behaves as in Project #1.
Description of Figure 18: Choose Project #3 as Active Project. This figure shows a screenshot of the PSoC Creator Workspace Explorer with a right-click context menu displaying the option to 'Set As Active Project'.
Upgrade Information
N/A
Related Documents
Table 2 lists relevant application notes, code examples, knowledge base articles, device datasheets, and Component datasheets.
| Document | Title | Comment |
|---|---|---|
| AN79953 | Getting Started with PSoC® 4 | Introduces PSoC® 4, an ARM® Cortex™-M0 MCU based programmable system-on-chip. It helps explore the architecture and Creator development tools. |
| AN86439 | PSoC® 4 - Using GPIO Pins | Explains how to use PSoC® 4 GPIO pins effectively and take full advantage of their features, including basics, configuration options, mixed-signal use, registers, interrupts, and low-power behavior. |
| AN90114 | PSoC® 4000 Family Low-Power System Design Techniques | Introduces the low-power modes of the PSoC® 4000 family and methods for designing low-power systems. |
| AN90799 | PSoC® 4 Interrupts | Explains the interrupt architecture in PSoC 4 and its configuration in PSoC Creator™ IDE with three example projects. |
| AN89610 | PSoC® 4 and PSoC 5LP ARM Cortex Code Optimization | Shows how to optimize C and assembler code for ARM Cortex CPUs in PSoC® 4 and PSoC 5LP, supporting Gcc and Keil MDK C compilers. |
| 001-94480 | System Reference Guide | Describes functions supplied by the PSoC Creator cy_boot component, providing system functionality for projects and access to chip resources. |
| KBA91373 | Watchdog Timer in the PSoC® 4000 Family | Explains the differences between the PSoC® 4000 family WDT and the PSoC 4100/4200 family WDT, and how to generate a periodic ISR using the PSoC 4000 WDT. |
| PSoC 4 Datasheets | PSoC 4 Technical Reference Manuals | |
| Development Kit (DVK) Documentation | PSoC 4 Kits |
Document History
Document Title: CE95400 - Watchdog Timer Reset and Interrupt for PSoC® 41xx/42xx Devices
Document Number: 001-95400
| Revision | ECN | Orig. of Change | Submission Date | Description of Change |
|---|---|---|---|---|
| ** | 4644987 | BOBH | 05/12/2015 | New spec |
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