ℹ️ Document Conversion Notice: This document has been converted from PDF and formatted to fit this screen. Diagrams and images may be available only in the original here.

Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series

This document provides essential migration guidelines for Altera's Agilex™ 3 C-Series devices. It is designed to assist engineers in planning their Quartus® Prime software and board designs to ensure a smooth transition between different devices within the same package.

Key Topics Covered:

Supported packages and migration scenarios (Vertical and Conditional).
Detailed considerations for migration planning across various packages (M12A, M16A, B18A, B18B, B23C).
Functional area analysis, including I/O, LVDS SERDES, Configuration, External Memory Interface, MIPI D-PHY, HPS, Transceiver, Power, and Sensor.
Guidance on migrating designs using the Quartus Prime software.

By understanding these guidelines, users can effectively plan and execute device migrations, optimizing their hardware designs and software implementations.

Models: B23C, M12A, M16A, B18A, B18B, Agilex 3 FPGAs and SoCs C-Series Development Kit, Agilex 3 FPGAs and SoCs C-Series, Development Kit, Kit

File Info : application/pdf, 30 Pages, 984.11KB

an-848793-848794 Antenna House PDF Output Library 6.6.1359 (Linux64)

Related Documents

	Altera Agilex 3 FPGA and SoC Pin Connection Guidelines Comprehensive guide detailing pin functions and connection recommendations for Altera Agilex 3 FPGAs and SoCs, covering core, HPS, and transceiver pins, along with power supply sharing.
	Agilex 7 M-Series FPGA Network-on-Chip (NoC) User Guide This user guide provides comprehensive information on the Network-on-Chip (NoC) subsystem integrated into Intel's Agilex 7 M-Series FPGAs. It details the architecture, design flow, and usage of the NoC for high-bandwidth data movement between FPGA fabric and memory resources like HBM2e and DDR5, utilizing the Quartus Prime Pro Edition software.
	Agilex 5 FPGAs and SoCs: External Memory Interfaces (EMIF) IP User Guide This user guide provides comprehensive information on the Agilex 5 FPGA External Memory Interfaces (EMIF) IP, detailing its architecture, protocols, and design flow. It covers support for DDR4, LPDDR4, and LPDDR5 memory protocols, along with guidance on pin assignments, simulation, timing closure, and debugging. Essential for engineers working with high-speed memory interfaces on Agilex 5 devices.
	FPGA AI Suite: Getting Started Guide This guide provides an overview of the FPGA AI Suite, installation instructions, prerequisites, and a tutorial for running AI inference on FPGAs. It covers topics like setting up the development environment, using the compiler, and deploying AI models.
	Quartus Prime Pro Edition User Guide: Design Compilation Comprehensive guide to the Quartus Prime Pro Edition Compiler, detailing design compilation stages, optimization techniques, and analysis flows for Altera FPGA development.
	Agilex 5 FPGA EMIF IP User Guide: External Memory Interfaces Explore Altera's Agilex 5 FPGA External Memory Interfaces (EMIF) IP User Guide. This document details the EMIF IP's architecture, features, and support for DDR4, LPDDR4, DDR5, and LPDDR5 memory protocols, crucial for high-performance FPGA designs.
	Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Comprehensive guide to the Altera Agilex 5 FPGA E-Series 065B Premium Development Kit, detailing hardware, software, setup, and features for advanced FPGA development.
	Agilex 7 M-Series FPGA EMIF IP User Guide for External Memory Interfaces Comprehensive user guide for Intel's Agilex 7 M-Series FPGA External Memory Interfaces (EMIF) IP, detailing support for DDR4, DDR5, and LPDDR5 protocols, architecture, pin planning, and simulation.