FPGA AI Suite: Getting Started Guide

Introduction

The FPGA AI Suite Getting Started Guide offers a comprehensive introduction to accelerating Artificial Intelligence (AI) workloads on Intel FPGAs. This document details the suite's components, installation procedures, and essential prerequisites. It includes a practical tutorial guiding users through the process of running inference on a ResNet-50 graph, covering performance and area estimation.

The guide also outlines the different documentation resources available for the FPGA AI Suite, helping users locate specific information related to release notes, IP reference, compiler usage, and design examples for various FPGA platforms like Arria 10 and Agilex 7.

For users looking to implement AI solutions, familiarity with the Intel Distribution of OpenVINO toolkit is recommended, as the FPGA AI Suite requires version 2022.3.1 LTS.

Key Features and Components

FPGA AI Suite IP: An RTL-instantiable IP with AXI interfaces for integration into FPGA systems.
Compiler (dla_compiler): A versatile tool for generating AI model architectures, estimating IP performance and resource consumption, and creating ahead-of-time compiled graphs.
IP Generation Tool: Customizes FPGA AI Suite IP based on input architecture files.
Example Designs: Demonstrations of how to use the FPGA AI Suite IP with various hardware platforms, including PCIe-based and SoC designs for Arria 10 and Agilex 7 devices.

Installation Overview

The installation process for the FPGA AI Suite can vary depending on the chosen design example. Users can install the compiler, IP, and associated tools separately or as part of a full design example setup. The guide provides detailed steps for installing on different operating systems, including Red Hat Enterprise Linux and Ubuntu, and also covers installation within a Windows Subsystem for Linux 2 (WSL 2) environment.

Key installation steps include:

Reviewing supported FPGA families.
Ensuring operating system prerequisites are met.
Installing the FPGA AI Suite package.
Installing the OpenVINO Toolkit.
Installing Quartus Prime Pro Edition (required for example designs).
Setting environment variables.

	Agilex 7 M-Series FPGA Network-on-Chip (NoC) User Guide This user guide provides comprehensive information on the Network-on-Chip (NoC) subsystem integrated into Intel's Agilex 7 M-Series FPGAs. It details the architecture, design flow, and usage of the NoC for high-bandwidth data movement between FPGA fabric and memory resources like HBM2e and DDR5, utilizing the Quartus Prime Pro Edition software.
	Quartus Prime Pro Edition User Guide: Design Compilation Comprehensive guide to the Quartus Prime Pro Edition Compiler, detailing design compilation stages, optimization techniques, and analysis flows for Altera FPGA development.
	Agilex 5 FPGAs and SoCs: External Memory Interfaces (EMIF) IP User Guide This user guide provides comprehensive information on the Agilex 5 FPGA External Memory Interfaces (EMIF) IP, detailing its architecture, protocols, and design flow. It covers support for DDR4, LPDDR4, and LPDDR5 memory protocols, along with guidance on pin assignments, simulation, timing closure, and debugging. Essential for engineers working with high-speed memory interfaces on Agilex 5 devices.
	GTS Transceiver Dual Simplex Interfaces User Guide A comprehensive user guide from Altera (Intel) detailing the implementation of Dual Simplex (DS) mode for Agilex 5 GTS transceivers. It covers planning, IP generation, assignment, connection, and verification steps using Quartus Prime Pro Edition.
	Agilex 7 M-Series FPGA EMIF IP User Guide for External Memory Interfaces Comprehensive user guide for Intel's Agilex 7 M-Series FPGA External Memory Interfaces (EMIF) IP, detailing support for DDR4, DDR5, and LPDDR5 protocols, architecture, pin planning, and simulation.
	Agilex 5 FPGA EMIF IP User Guide: External Memory Interfaces Explore Altera's Agilex 5 FPGA External Memory Interfaces (EMIF) IP User Guide. This document details the EMIF IP's architecture, features, and support for DDR4, LPDDR4, DDR5, and LPDDR5 memory protocols, crucial for high-performance FPGA designs.
	Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Comprehensive guide to the Altera Agilex 5 FPGA E-Series 065B Premium Development Kit, detailing hardware, software, setup, and features for advanced FPGA development.
	Altera Embedded Peripherals IP User Guide for Intel FPGAs Explore Altera's comprehensive Embedded Peripherals IP User Guide for Intel FPGAs. Covers Avalon-ST, SPI, eSPI, DMA, UART, FIFO, Memory Cores, and more, integrated with Platform Designer.

Introduction

Key Features and Components

Installation Overview

Related Documents