ℹ️ Document Conversion Notice: This document has been converted from PDF and formatted to fit this screen. Diagrams and images may be available only in the original here.

AN5864: Aurora Reference Design

A Microchip Technology Application Note

This document provides comprehensive instructions for utilizing the Aurora 8B/10B Intellectual Property (IP) on the Microchip PolarFire Evaluation Board, as detailed in the AN5864 reference design.

It guides users through configuring the PolarFire high-speed transceiver (PF_XCVR_ERM) in PCS 8B10B mode, alongside the Aurora 8B/10B IP. The design incorporates AURORA_TX_GENERATOR and AURORA_RX_CHECKER modules to facilitate data generation and verification through the AXI4-Stream interface.

The reference design supports both SFP+ and SMA interfaces, enabling full-duplex data transfer when deployed across two Microchip PolarFire boards. Key aspects covered include design specifications, module overviews, Libero project setup, simulation, and debugging procedures.

For further assistance or information, consult Microchip's support resources:

Models: AN5864, AN5864 PolarFire Mid Range FPGAs, AN5864, PolarFire Mid Range FPGAs, Range FPGAs, FPGAs

File Info : application/pdf, 18 Pages, 1.54MB

an5864 aurora reference design

References

Antenna House PDF Output Library 7.4.1889

Related Documents

	Microchip PolarFire FPGA and PolarFire SoC FPGA PCI Express User Guide Explore the PCI Express (PCIe) subsystem in Microchip's PolarFire® and PolarFire SoC FPGAs with this comprehensive user guide. Learn about its architecture, features, implementation, configuration, and performance for high-speed serial communication.
	Microchip DDR AXI4 Arbiter v2.2 User Guide This user guide provides comprehensive details on the Microchip DDR AXI4 Arbiter IP core (v2.2), covering its introduction, features, implementation in Libero SoC, device utilization, interface signals, and testbench procedures for efficient DDR memory access in video and graphics applications.
	Libero SoC Tcl Command Reference Guide Comprehensive guide to Tcl commands for the Microchip Libero System-on-Chip (SoC) design suite, covering device families, scripting, and various command categories for efficient FPGA and SoC FPGA design.
	Libero SoC v2025.1 Release Notes - Microchip Technology Detailed release notes for Microchip's Libero SoC Design Suite v2025.1, covering new features, enhancements, resolved issues, and known limitations for FPGA and SoC device design.
	PolarFire FPGA and PolarFire SoC FPGA Power-Up and Resets User Guide This user guide details the power-up and reset procedures for Microchip's PolarFire FPGA and PolarFire SoC FPGA families. It covers essential steps like Power-On, Device Boot, Design and Memory Initialization, and various reset schemes, providing a comprehensive understanding of device initialization and operation.
	PolarFire FPGA and PolarFire SoC FPGA Power-Up and Resets User Guide This user guide details the power-up and reset procedures for Microchip's PolarFire FPGA and PolarFire SoC FPGA devices. It covers essential steps like Power-On, Device Boot, Design and Memory Initialization, and various reset schemes, providing a comprehensive understanding of device startup and configuration.
	Libero SoC Design Flow User Guide Comprehensive guide to Microchip's Libero SoC design suite, covering FPGA design flow, tools, constraints management, implementation, and debugging for devices like PolarFire, PolarFire SoC, SmartFusion 2, IGLOO 2, and RTG4.
	PDC Commands Reference Guide for PolarFire and PolarFire SoC FPGAs This guide provides a comprehensive reference for PDC (Physical Design Constraints) commands used in the Libero SoC Design Suite for PolarFire and PolarFire SoC FPGAs. It details syntax, arguments, and examples for various commands related to I/O configuration, floorplanning, and post-layout editing, enabling users to effectively manage FPGA design constraints.