UT986 GNSS All-constellation Multi-frequency High Precision Timing Module

Revision History

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Foreword

This manual provides information about the product characteristics, installation and use, performance indicators and hardware design of the UT986 module.

Target Readers

This manual applies to technicians who have certain knowledge in GNSS modules.

1 Product Introduction

UT986 is a new generation of GNSS high precision timing module supporting all constellations and multiple frequencies. It is based on the RF-baseband integrated GNSS SoC - NebulasIV™, and is mainly used in power grids and telecom base station timing.

UT986 has 1408 super channels, supporting BDS (including BDS-3 signals), GPS, GLONASS and Galileo multi-system joint timing and single system standalone timing, which users can flexibly configure. It also supports QZSS and DGPS function.

UT986 module integrates filters and linear amplifiers, and has optimized radio frequency structure and interference suppression capability. With the built-in JamShield adaptive anti-jamming technology and U-AutoAlign multi-path suppression technology, it can detect interference as well as spoofing, ensuring a good performance even in complex electromagnetic environments.

UT986 module can provide nanosecond-level PPS accuracy, support fixed-location timing, optimized-location timing, and positioning timing, and remain good timing accuracy even in complex signal environments.

UT986 features a compact size of 17.0 mm × 22.4 mm × 2.4 mm. It adopts SMT pads, supports standard pick-and-place and fully automated integration of reflow soldering, and is compatible with previous generation of timing products as well as mainstream products on the market.

Figure 1-1: Image of the UT986 Module.

1.1 Features

1.2 Performance

Key Performance/Specifications

TTFF

Cold Start: 30 s

Reacquisition: 3 s

Positioning Accuracy (CEP)

1.5 m (Dual-system horizontal, open sky)

2.5 m (Dual-system vertical, open sky)

Velocity Accuracy (RMS)

0.03 m/s (Dual-system horizontal, open sky)

Sensitivity

1PPS Accuracy

5 ns (1σ)

Data Update Rate

1 Hz

Data Format

NMEA 0183: Input/Output, ASCII, NMEA4.10, NMEA4.11 (by default)

Unicore Protocol: Input/Output, ASCII, Unicore Protocol

RTCM: Input, RTCM3.2

¹ All satellites C/N0 at 41dB

² Depends on atmospheric (ionosphere) conditions, GNSS antenna, multipath conditions, satellite visibility and geometry

³ Tested with a good external LNA at room temperature

⁴ Open sky; fixed coordinate system; depends on temperature, atmospheric (ionosphere) conditions, GNSS antenna, multipath conditions, satellite visibility and geometry

⁵ Refer to GNSS Timing Products Protocol Specification

1.3 Block Diagram

Figure 1-2: Block diagram showing the UT986 module's internal components including RF Part, NebulasIV SoC, and external interfaces connected to VCC, GND, etc.

RF Part

The receiver gets filtered and enhanced GNSS signal from the antenna via a coaxial cable. The RF part converts the RF input signals into the IF signals, and converts IF analog signals into digital signals required for NebulasIV™ chip.

NebulasIVTM SoC

NebulasIV™ is UNICORECOMM's new generation high precision GNSS SoC with 22 nm low power design, supporting all constellations, multiple frequencies and 1408 super channels. It integrates a dual-core CPU, a high speed floating point processor and an RTK co-processor, which can fulfill the high precision baseband processing and RTK positioning independently.

External Interfaces

The external interfaces of UT986 include UART, PPS, nRESET, etc.

1.3.1 Pulse per Second (1PPS)

UT986 provides one 1PPS signal output with adjustable pulse width and polarity, which can be configured and queried through the CFGTP command. TIMTP is used to describe the related 1PPS information including the corresponding time and time accuracy indicators.

The 1PPS signal of UT986 is the output for timing, which is an important functional signal, and needs to be connected to the time scale input interface of the host. The output period of 1PPS is 1 s, and the default duty cycle is 10%.

1.3.2 Serial Port

The two serial ports of UT986 are LVTTL, which need to be converted through RS232 level if connected to a PC.

The UART1 is the master port. It supports the data transmission and firmware upgrade. The default baud rate is 460800 bps, and it can be configured by users. When designing products, make sure that UART1 is connected to a PC or external processor to support firmware upgrade.

The UART2 is an optional port, only for backup. It only supports data transmission and is unavailable for firmware upgrade. The port can be connected or unconnected depending on the situation.

It is recommended to reserve a test point for UART2 as the debug port.

If there is data input at the digital IO (including RXD1, TXD1, RXD2, TXD2, TIME PULSE, and nRESET) when the module is not powered on, it will form a leakage on the VCC. And if the leakage voltage is higher than 0.4 V, it may cause a start failure when the module is powered on. Therefore, in order to prevent the leakage, ensure that the IO ports connected to the module are in high impedance or low level before the module is powered on.

1.3.3 Clock

The industrial VCTCXO is built in UT986 to ensure the stability of the clock system and the ability to capture signals quickly in weak signal environments.

1.3.4 nRESET Timing Requirement

The module's reset pin nRESET and power supply VCC should meet the following requirement of time sequence when powering up. During its normal operation, pulling down the nRESET pin for more than 2.5 ms can also reset the UT986 module.

The reset pin nRESET is effective when lower than 0.3 V.

Figure 1-3: Diagram illustrating the UT986 Reset Signal timing, showing VCC and nRESET levels over time, with a requirement of > 2.5 ms.

1.3.5 Antenna

The filter and linear amplifier are built in the UT986 module. It is recommended to use an active antenna to provide better performance.

The antenna should support signal frequencies ranging from 1160 MHz to 1230 MHz and 1555 MHz to 1610 MHz, support right-handed circular polarization, and the output VSWR should be ≤ 2.0, gain range should be within 5 dB to 35 dB, in-band flatness < 1.5, out-of-band suppression >50 dB @2G3G4G5G communication frequencies.

1.4 Precision Timing and Raw Data Output

UT986 supports fixed-location timing, optimized-location timing, and positioning timing. Switch or query the above timing modes through CFGTM command. The module can simultaneously track all the four GNSS systems including GPS, BDS, GLONASS and Galileo, and can be switched back and forth between these four systems using CFGGNSS command.

The default mode of UT986 module is optimized-location timing. It outputs information of the dynamic position and fixed position, which can be queried by TIMPOS command. Refer to Unicore Timing Products Protocol Specification for more details.

Fixed-location Timing

Fixed-location timing mode only applies to static scenes. In this mode, users are required to input the exact position of the receiver's antenna center through the CFGTM command. UT986 uses this position to calculate the distance between the antenna and satellites, and calculate time to provide timing service.

Optimized-location Timing

Optimized-location timing mode also applies to static scenes. In this mode, the receiver collects a number of positioning points (within observation time) and calculates the exact position of the antenna. After that, the position is locked down, the timing mode is switched to fixed-location timing, and the receiver provides timing based on the locked position.

The observation time and accuracy are configured through CFGTM command. The fixed-location timing mode is activated only after both of them are configured. Query the observation status through TPFINFO command.

Using the CFGTM command, the calculated position of the antenna can be saved or not. For the former, the position estimation process only needs to be done once after UT986 is installed; and for the latter, the process does again after the restart. After the optimization of the position, the timing mode of the receiver automatically switches to the fixed-location timing mode.

If the position of UT986 antenna changes, the command CFGTM must be sent again to switch the timing mode back to the optimized-location timing mode to recalibrate the antenna position. Refer to GNSS Timing Products Protocol Specification for more details.

Positioning Timing

In the positioning timing mode, UT986 calculates the antenna position and time in real time. It is the only mode that supports dynamic timing, and the timing quality depends on the satellite environment, which makes it difficult to guarantee the timing accuracy.

1.5 Protocols

⁶ For more information, please refer to GNSS Timing Products Protocol Specification

2 Installation for Test

This section describes how to use the EVK to test and evaluate the performance of the UT986 module.

To ensure a successful installation, please prepare the following accessories in advance:

• UT986 EVK (including a power supply)
• Matching antenna
• Antenna cable
• Straight-through cable
• Desktop or laptop computer with serial port and UPrecise.

Please keep the packing box and antistatic box for storage and handling.

2.1 Attentions

⚠️ Many components on the UT986 module are static sensitive devices (SSD). Therefore, it is necessary to provide ESD protection for IC circuits and other SSD. Please obey all the ESD precautions and procedures.

⚠️ Electrostatic discharge (ESD) may cause damage to the device. All operations mentioned in this chapter should be carried out on an antistatic workbench using an antistatic wrist strap and conductive foam pad. If there is no antistatic workbench, wear an antistatic wrist strap and connect the other end of the strap to the metal frame to avoid electrostatic damages.

Hold the edge of the evaluation board, and do NOT touch the components directly.

Carefully check the board to make sure that there is no apparent loose or damaged components. If you have any questions, please contact Unicore or the local distributors.

2.2 Installation

Figure 2-1: Diagram showing typical installation of UT986 EVK connecting Antenna, PC, and UT986 EVK/receiver.

1. Ensure adequate antistatic measures, such as wearing a grounded antistatic wrist strap, using a grounded workbench, etc.
2. Open UT986 EVK and take out the evaluation board.
3. Select the GNSS antenna with appropriate gain (the system frequency supported by the antenna should be consistent with the module), fix it in a non-occluded area, and use the appropriate cable to connect the antenna with the UT986 evaluation board.
4. Connect PC to COM1 or COM2 of the evaluation board with a straight-through cable.
5. Power on the evaluation board and initialize UT986.
6. Open the UPrecise software.
7. Control the receiver via UPrecise to display constellations view, messages, the receiver's status, etc.

3 Hardware

3.1 Pin Definition

Figure 3-1: UT986 Pin Assignment diagram showing pin numbers, names, I/O, and electrical levels.

⁷ Not supported currently; future versions will support.

3.2 Electrical Specifications

3.2.1 Absolute Maximum Ratings

3.2.2 Operational Conditions

3.2.3 IO Threshold Values

3.2.4 Antenna Characteristics

3.3 Dimensions

Figure 3-2: Mechanical Layout diagrams showing dimensions and pad details for the UT986 module.

4 Hardware Design

4.1 Recommended Minimal Design

Figure 4-1: Schematic diagram of the UT986 Minimal Design, showing connections to ANT, VCC, GND, HOST, etc., with component recommendations (L1, C1, C2, C3, R1).

Remarks:

• L1: 68 nH RF inductor in 0603 package is recommended
• C1: 100 nF + 100 pF capacitors connected in parallel is recommended
• C2: 100 pF capacitor is recommended
• C3: n × 10 µF + 1 × 100 nF capacitors connected in parallel is recommended, and the total inductance should be no less than 30 µF
• R1: 10 kΩ resistor is recommended

4.2 Antenna Feed Design

UT986 supports feeding the antenna from the outside of the module rather than from the inside. It is recommended to use devices with high power and that can withstand high voltage. Gas discharge tube, varistor, TVS tube and other high-power protective devices may also be used in the power supply circuit to further protect the module from lightning strike and surge.

If the antenna feed supply ANT_BIAS and the module's main supply VCC use the same power rail, the ESD, surge and overvoltage from the antenna will have an effect on VCC, which may cause damage to the module. Therefore, it is recommended to design an independent power rail for the ANT_BIAS to reduce the possibility of module damage.

Figure 4-2: UT986 Reference Circuit diagram illustrating antenna feed design with components like L1, C1, C2, C3, D1, D2.

Remarks:

• L1: feed inductor, 68 nH RF inductor in 0603 package is recommended. The rated current of the L1 inductor should be larger than the operating current of the selected antenna, and leave enough design margin
• C1: decoupling capacitor, recommended to connect two capacitors of 100 nF/100 pF in parallel
• C3: DC blocking capacitor, recommended 100 pF capacitor
• D1: ESD diode, choose the ESD protection device that supports high frequency signals (above 1000 MHz)
• D2: TVS diode, choose the TVS diode with appropriate clamping specification according to the requirement of feed voltage and antenna voltage
• RF_IN does not feed the antenna. You need to design the antenna feed circuit according to the antenna you choose.

4.3 Power On and Power Off

VCC

• The VCC initial level when power-on should be less than 0.4 V.
• The VCC ramp when power-on should be monotonic, without plateaus.
• The voltages of undershoot and ringing should be within 5% VCC.
• VCC power-on waveform: The time interval from 10% rising to 90% must be within 100 µs to 1 ms.
• Power-on time interval: The time interval between the power-off (VCC < 0.4 V) to the next power-on must be larger than 500 ms.
• It is recommended to use the same power supply for the VCC of UT986 and the IO of the host, so as to avoid abnormal startup caused by the IO leakage between UT986 and the host. The power supply of UT986 VCC ranges from 3.0 V to 3.6 V, and the input decoupling capacitor C2 (see Figure 4-2) needs to be more than 10 µF. Other capacitors, such as 1 µF/100 nF/ 100 pF, can be connected in parallel.

V_BCKP

• The V_BCKP initial level when power-on should be less than 0.4 V.
• The V_BCKP ramp when power-on should be monotonic, without plateaus.
• The voltages of undershoot and ringing should be within 5% V_BCKP.
• V_BCKP power-on waveform: The time interval from 10% rising to 90% must be within 100 µs to 1 ms.
• Power-on time interval: The time interval between the power-off (V_BCKP < 0.4 V) to the next power-on must be larger than 500 ms.

4.4 Grounding and Heat Dissipation

Figure 4-3: Diagram showing pads for grounding and heat dissipation on the UT986 module.

There are 35 pads in the middle rectangle area of UT986 module, which are used for grounding and heat dissipation. When designing PCB, connect the pads to a large size of ground to facilitate heat dissipation.

4.5 Recommended PCB Package Design

See the following figure for the recommended PCB package design of the module UT986.

Figure 4-4: Diagram illustrating the recommended PCB package design for the UT986 module, with dimensions and detail views of pads.

Remark:

• For the convenience of testing, the soldering pads of the pins are designed long, exceeding the module border much more. For example: The pads denoted as detail C are 1.79 mm longer than the module border. The pad denoted as detail A is 0.77 mm longer than the module border. It is relatively short as it is an RF pin pad, so we hope the trace on the surface is as short as possible to reduce the impact of interference.
• In order to effectively reduce the possibility of solder bridge during the soldering, the pin pads are designed narrower than the pins. However, the pad denoted as detail A has the same width as the pin, as we hope the resistance is as continuous as possible at the RF pin.

4.6 Layout Recommendation

• Power supply: Stable and low ripple power is necessary for good performance. Make sure the peak-to-peak ripple voltage does not exceed 50 mV.
  - Use LDO to ensure the purity of power supply
  - Place LDO as close to the module as possible in layout
  - Widen the power circuit wiring or use split copper surface to transmit current
  - Keep away from any high power or high inductance devices such as a magnetic coil.
• Antenna link: The antenna link requires 50 Ω impedance matching. The RF routing connecting RF_IN and the antenna should have 50 Ω impedance, as short and smooth as possible, and avoid acute angles.
• Antenna location: In order to obtain a good signal-to-noise ratio, ensure that the antenna is well isolated from electromagnetic radiation sources, especially electromagnetic radiation in the frequency range of 1100 MHz to 1610 MHz. Try to avoid circuits below UT986 module.
• UT986 is a temperature sensitive device and rapid temperature changes can result in reduced performance. Keep it away as far as possible from any high-temperature air and high-power heating devices.
• Connect all the GND pins of UT986 to the ground.
• All the RSV pins are reserved and it is recommended to keep them floating.
• The thermal pad of UT986 must be connected to a large area of grounding copper to effectively dissipate heat.

5 Production Requirement

5.1 Disassembly

⚠️ When disassembling the module, it is recommended to melt the soldering tin of the pins on both sides of the module with an electric soldering iron and remove the module with a tweezer. Do NOT use other means to remove the module (for example, blow off the module with a hot air gun), which may damage the module.

5.2 Clean

Do NOT use alcohol or other organic solvents to clean the module, or it may lead to flux residues entering into the shielding shell, causing mildew and other problems.

5.3 Reflow Soldering

⚠️ In order to prevent falling off during soldering of the module, do not solder it on the back of the board during design, and it is not recommended to go through soldering cycle twice.

• The setting of soldering temperature depends on many factors of the factory, such as board type, solder paste type, solder paste thickness, etc. Please also refer to the relevant IPC standards and indicators of solder paste.
• Since the lead soldering temperature is relatively low, if using this method, please give priority to other components on the board.
• The opening of the stencil needs to meet your design requirement and comply to the examine standards. The thickness of the stencil must be larger than 0.15 mm and it is recommended to be larger than 0.18 mm.

Figure 5-1: Reflow Soldering Temperature Curve graph showing temperature stages (Rising, Preheating, Reflux, Cooling) over time.

Temperature Rising Stage

• Rising slope: Max. 3 °C/s
• Rising temperature range: 50 °C to 150°C

Preheating Stage

• Preheating time: 60 s to 120 s
• Preheating temperature range: 150 °C to 180 °C

Reflux Stage

• Over melting temperature (217 °C) time: 40 s to 60 s
• Peak temperature for soldering: No higher than 245 °C

Cooling Stage

• Cooling slope: Max 4 °C/s

6 Packaging

6.1 Product Label

Figure 6-1: Diagram of the UT986 Product Label, showing Product Name, PN, SN, and QR Code.

6.2 Packaging Description

UT986 module uses carrier tape and reel (suitable for mainstream surface mount devices), packaged in vacuum-sealed aluminum foil antistatic bags, with a desiccant inside to prevent moisture. When using reflow welding process to weld modules, please strictly comply with IPC standard to conduct humidity control on the modules. As packaging materials such as carrier tape can only withstand the temperature of 55 °C, modules should be removed from the package during baking.

Figure 6-2: Diagram illustrating the UT986 Packaging.

Reel Packaging Diagram

Figure 6-3: Carrier Tape Drawing and Reel Packaging Diagram showing dimensions and notes for reel packaging.

Note:

• The cumulative tolerance of 10 side holes should not exceed ±0.2 mm.
• Material: Black antistatic PS (surface impedance 10⁵-10¹¹ Ω) (surface static voltage <100 V), thickness: 0.35 mm.
• Total length of the 13-inch reel package: 6.816 m (Length of the first part of empty packets: 0.408 m, length of packets containing modules: 6 m, length of the last part of empty packets: 0.408 m).
• Total number of packets in the 13-inch reel package: 284 (Number of the first part of empty packets: 17; actual number of modules in the packets: 250; number of the last part of empty packets: 17).

All dimension designs are in accordance with EIA-481-C-2003.

The maximum bending degree of the carrier tape within the length of 250 mm should not exceed 1mm.

Company Information

Unicore Communications, Inc.

F3, No.7, Fengxian East Road, Haidian, Beijing, P.R.China, 100094

www.unicorecomm.com

Phone: 86-10-69939800

Fax: 86-10-69939888

info@unicorecomm.com