Unicore UT986 GNSS Timing Module

1.1 Overview

The UT986 is a new generation GNSS high-precision timing module supporting all constellations and multiple frequencies. It is based on the integrated RF-baseband GNSS SoC, NebulasIV™, and is primarily used for timing in power grids and telecom base stations. The module features 1408 super channels, supporting multi-system joint timing and single-system standalone timing for BDS (including BDS-3), GPS, GLONASS, and Galileo, with flexible configuration options. It also supports QZSS and DGPS. The UT986 integrates filters and linear amplifiers, featuring an optimized RF structure and interference suppression capabilities, including built-in JamShield adaptive anti-jamming and U-AutoAlign multi-path suppression technologies. This ensures good performance even in complex electromagnetic environments. The module offers nanosecond-level PPS accuracy and supports fixed-location timing, optimized-location timing, and positioning timing, maintaining high timing accuracy in challenging signal conditions. The UT986 has a compact size of 17.0 mm × 22.4 mm × 2.4 mm, utilizes SMT pads for pick-and-place and reflow soldering integration, and is compatible with previous timing products and mainstream market offerings.

Diagram Description: Figure 1-1 shows the UT986 Module.

1.2 Features

Table 1-1 lists the product features:

1.3 Block Diagram

Diagram Description: Figure 1-2 illustrates the UT986 Block Diagram, showing connections between RF input, LNA, SAW, VCTCXO, CLOCK, the NebulasIV SoC (RF, BB, PMU), and interfaces like UART1, UART2, nRESET, VCC, and V_BCKP.

1.4 Performance

Table 1-2 details the key performance and specifications:

¹ All satellites C/N0 at 41dB
² Tested with a good external LNA

1PPS Accuracy (RMS)³: 2.5 ns

Data Update Rate: 1 Hz

Data Format: NMEA 0183, Unicore Protocol, RTCM3.2

1.5 Precision Timing and Raw Data Output

The UT986 supports fixed-location timing, optimized-location timing, and positioning timing. These modes can be switched or queried using the CFGTM command. The module can simultaneously track GPS, BDS, GLONASS, and Galileo, and switch between them using the CFGGNSS command.

The default mode is optimized-location timing, outputting dynamic and fixed position information queried via the TIMPOS command. Refer to the UT986_Protocol Specification for details.

Fixed-location Timing: Applicable to static scenes. Users must input the exact antenna center position via CFGTM command. UT986 uses this position to calculate distances to satellites and provide timing.

Optimized-location Timing: Also for static scenes. The receiver collects positioning points to determine the antenna’s exact position. Once locked, it switches to fixed-location timing. Observation time and accuracy are configured via CFGTM. Fixed-location timing activates after both are configured. Observation status can be queried via TPFINFO. The calculated position can be saved or not. If saved, position estimation is done once; otherwise, it repeats after restart. After position optimization, the module automatically switches to fixed-location timing.

If the antenna position changes, the CFGTM command must be resent to switch back to optimized-location timing for recalibration. Refer to UT986_Protocol Specification.

Positioning Timing: Calculates antenna position and time in real-time. It supports dynamic timing, but accuracy depends on the satellite environment.

1.6 Pulse per Second (1PPS)

The UT986 provides a 1PPS signal output with adjustable pulse width and polarity, configurable and queryable via the CFGTP command. TIMTP describes 1PPS information and accuracy indicators.

1.7 Serial Port (UART)

The master serial port, UART1, supports data transmission and firmware upgrade via LVTTL signals. The default baud rate is 460800 bps. Ensure UART1 is connected to a PC or external processor for firmware upgrades. Serial port 2 supports data transmission only and is for backup.

1.8 Protocols

Table 1-3 lists supported interface protocols:

⁴ For more information, please refer to UT986_Protocol Specification.

1.9 Clock

The module features an industrial VCTCXO for clock system stability and quick signal capture in weak environments.

1.10 Antenna

The UT986 module includes built-in filters and linear amplifiers. An active antenna is recommended for optimal performance. The antenna should support frequencies from 1160 MHz to 1230 MHz and 1555 MHz to 1610 MHz, right-handed circular polarization, with VSWR ≤ 2.0, gain between 5 dB to 35 dB, in-band flatness < 1.5, and out-of-band suppression >50 dB for communication frequencies.

2.1 Attentions

The UT986 module contains static-sensitive devices (SSD). ESD protection is crucial for IC circuits and SSDs. Adhere to all ESD precautions and procedures.

[Warning] Electrostatic discharge (ESD) can damage the device. All operations in this chapter must be performed on an antistatic workbench with an antistatic wrist strap and conductive foam pad. If an antistatic workbench is unavailable, wear an antistatic wrist strap connected to a metal frame.

• Hold the evaluation board by its edges and avoid touching components directly.

Carefully inspect the board for loose or damaged components. Contact Unicore or local distributors for any questions.

2.2 Installation

Diagram Description: Figure 2-1 shows the typical installation of the UT986 EVK, illustrating connections between the antenna, UT986 EVK, and a PC.

Follow these steps for installation:

1. Ensure adequate antistatic measures, such as wearing a grounded antistatic wrist strap and using a grounded workbench.
2. Open the UT986 EVK and remove the evaluation board.
3. Select a GNSS antenna with appropriate gain, ensuring its frequency support matches the module. Mount it in an unobstructed area and connect it to the UT986 evaluation board using the appropriate cable.
4. Connect the PC to COM1 or COM2 of the evaluation board using a straight-through cable.
5. Power on the evaluation board and initialize the UT986.
6. Launch the UPrecise software.
7. Use UPrecise to control the receiver and view constellations, messages, and status information.

3.1 Absolute Maximum Ratings

Table 3-1 lists the absolute maximum ratings:

3.2 Operational Conditions

Table 3-2 outlines the operational conditions:

3.3 IO Threshold Values

Table 3-3 provides IO threshold values:

3.4 Antenna Characteristics

Table 3-4 details antenna characteristics:

3.5 Mechanical Specifications

Table 3-5 lists the mechanical dimensions:

Diagram Description: Figure 3-1 shows the Mechanical Layout of the UT986 module, indicating dimensions A through X.

3.6 Pin Definition

Diagram Description: Figure 3-2 shows the UT986 Pin Assignment, numbering pins from 1 to 28 and indicating their names.

Table 3-6 defines the pins:

⁵ Not supported by Firmware V1.0; future versions will support.

4.1 Hardware Reference Design

The UT986 supports feeding the antenna from an external source. It is recommended to use high-power, high-voltage-resistant components for protection against lightning strikes and surges, such as gas discharge tubes, varistors, and TVS diodes in the power supply circuit.

Diagram Description: Figure 4-1 shows the UT986 Reference Circuit, illustrating the connection of the antenna (ANT) via RF_IN to the UT986 module, along with power supply (VCC), serial ports (TXD1, RXD1, TXD2, RXD2), nRESET, TIME PULSE, and connections to a HOST device. It includes passive components like L1, C1, C2, C3, D1, and D2.

Remarks:

• L1: Feed inductor, 68 nH RF inductor in 0603 package recommended. Rated current should exceed the antenna's operating current with sufficient margin.
• C1: Decoupling capacitor, recommended to connect two 100 nF/100 pF capacitors in parallel.
• C3: DC blocking capacitor, recommended 100 pF.
• D1: ESD diode, choose a device supporting high-frequency signals (above 1000 MHz).
• D2: TVS diode, select with appropriate clamping specification based on feed and antenna voltage requirements.
• RF_IN: Does not feed the antenna; the antenna feed circuit must be designed according to the chosen antenna.

4.2 Power Supply VCC

For normal operation, the initial VCC voltage upon power-on should be less than 0.4 V and monotonic. Undershoot and ringing should be within 5% of VCC. The power-on waveform rise time (10% to 90%) should be between 1 ms and 10 ms. The interval between the last power-off (VCC < 0.4 V) and the next power-on should exceed 500 ms.

It is recommended to use the same power supply for UT986 VCC and the Host IO to prevent abnormal startup due to IO leakage. The UT986 VCC range is 3.0 V to 3.6 V. Input decoupling capacitor C2 should be at least 10 µF, with other capacitors (1 µF, 100 nF, 100 pF) connectable in parallel.

4.3 Serial Port

The UT986 has two serial ports (LVTTL) that require RS232 level conversion for PC connection. TXD1 and RXD1 are essential for Host UART communication. TXD2 and RXD2 are optional. It is recommended to reserve a test point for serial port 2 as a debug port.

[Information Symbol] If digital IO pins (RXD1, TXD1, RXD2, TXD2, TIME PULSE, nRESET) receive data when the module is unpowered, it can cause leakage to VCC. If this leakage voltage exceeds 0.4 V, it may lead to startup failure. To prevent this, ensure IO ports are in high impedance or low level before powering on the module.

4.4 nRESET Timing Requirement

The nRESET pin and VCC must meet specific timing sequences during power-up. Pulling the nRESET pin low for over 2.5 ms can reset the module during normal operation. The nRESET pin is active when below 0.3 V.

Diagram Description: Figure 4-2 shows the UT986 Reset Signal timing, indicating VCC and nRESET levels and the > 2.5 ms reset pulse duration.

4.5 TIME PULSE Output

The UT986 outputs a TIME PULSE signal, crucial for time scale input to the Host. The signal period is 1 s, with a default duty cycle of 10%.

4.6 Layout Recommendation

• Power Supply: Stable, low-ripple power is essential. Peak-to-peak ripple voltage should not exceed 50 mV. Use an LDO for power purity, place it close to the module, use wide traces or split copper for current, and keep away from high-power or high-inductance devices.
• Antenna Link: Requires 50 Ω impedance matching. RF routing for RF_IN and the antenna should maintain 50 Ω impedance, be as short and smooth as possible, and avoid acute angles.
• Antenna Location: Ensure good signal-to-noise ratio by isolating the antenna from electromagnetic radiation sources, especially in the 1100 MHz to 1610 MHz range. Avoid placing circuits directly below the UT986 module.
• The UT986 is temperature-sensitive; keep it away from high-temperature air and heating devices.
• Connect all GND pins to ground.
• RSV pins are reserved and should be left floating.
• The thermal pad of the UT986 must be connected to a large area of grounding copper for effective heat dissipation.

4.7 Grounding and Heat Dissipation

Diagram Description: Figure 4-3 illustrates the Pads for grounding and dissipation on the UT986 module.

The UT986 module has 35 pads in its central rectangular area dedicated to grounding and heat dissipation. When designing the PCB, connect these pads to a large ground plane to facilitate heat dissipation.

5.1 Product Label

Diagram Description: Figure 5-1 shows the Product Label, typically including Product Name, PN (Part Number), SN (Serial Number), and a QR Code.

5.2 Packaging Description

The UT986 module is supplied on carrier tape and reel, suitable for surface mount devices. It is packaged in vacuum-sealed aluminum foil antistatic bags with a desiccant to prevent moisture. For reflow welding, adhere to IPC standards for humidity control. Carrier tape can withstand temperatures up to 55 °C; modules should be removed from packaging before baking.

Diagram Description: Figure 5-2 shows the Packaging Diagram, depicting the reel, carrier tape, and antistatic bag.

Table 5-1 details packaging specifications:

The UT986 module is rated at MSL level 3. Refer to IPC/JEDEC J-STD-020 standards for packaging and handling precautions. The shelf life of modules in vacuum-sealed antistatic bags is one year.

Carrier Tape Drawing

Diagram Description: Figure 5-3 illustrates the Carrier Tape Drawing, showing dimensions and specifications for the tape used in reel packaging. It includes details on cumulative tolerance, material, total length, and number of packets per reel, adhering to EIA-481-C-2003 standards.

6.1 Disassembly

To disassemble the module, melt the solder tin on the pins using an electric soldering iron and remove the module with tweezers. Do not use methods like hot air guns, as they may damage the module.

6.2 Clean

Do not use alcohol or other organic solvents to clean the module, as flux residues may enter the shielding shell, causing mildew or other issues.

6.3 Reflow Soldering

• To prevent modules from falling off during soldering, do not solder on the back of the board and avoid a second soldering cycle.
• Soldering temperature settings depend on factory factors like board type, solder paste, and thickness. Refer to relevant IPC standards.
• For lead soldering, prioritize other components due to lower temperature requirements.
• Stencil openings must meet design requirements and standards. Stencil thickness should be greater than 0.15 mm, preferably larger than 0.18 mm.

Diagram Description: Figure 6-1 shows the recommended Reflow Soldering Temperature Curve (M705-GRN360), detailing the stages: Temperature Rising, Preheating, Reflux, and Cooling, with specified slopes, temperature ranges, and times.

• Temperature Rising Stage: Rising slope: Max. 3 °C/s; Temperature range: 50 °C to 150 °C.
• Preheating Stage: Preheating time: 60 s to 120 s; Temperature range: 150 °C to 180 °C.
• Reflux Stage: Over melting temperature (217 °C) time: 40 s to 60 s; Peak temperature: No higher than 245 °C.
• Cooling Stage: Cooling slope: Max 4 °C/s.