Intel Nios® V Processor Intel® FPGA IP Release Notes

Updated for Intel® Quartus® Prime Design Suite: 23.1

Document ID: 683098 | Version: 2023.04.10

1. Nios® V Processor Intel® FPGA IP Release Notes

The Intel® FPGA IP version (X.Y.Z) number can change with each Intel Quartus® Prime software version. A change in:

X indicates a major revision of the IP. If you update the Intel Quartus Prime software, you must regenerate the IP.
Y indicates the IP includes new features. Regenerate your IP to include these new features.
Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

Related Information

Nios V Processor Reference Manual: Provides information about the Nios V processor performance benchmarks, processor architecture, the programming model, and the core implementation (Intel Quartus Prime Pro Edition User Guide).
Nios II and Embedded IP Release Notes
Nios V Embedded Processor Design Handbook: Describes how to most effectively use the tools, recommends design styles, and practices for developing, debugging, and optimizing embedded systems using the Nios® V processor and Intel-provided tools (Intel Quartus Prime Pro Edition User Guide).
Nios® V Processor Software Developer Handbook: Describes the Nios® V processor software development environment, the tools that are available, and the process to build software to run on Nios® V processor (Intel Quartus Prime Pro Edition User Guide).

2. Nios® V/m Processor Intel FPGA IP (Intel Quartus Prime Pro Edition) Release Notes

2.1. Nios® V/m Processor Intel FPGA IP v22.4.3

Intel Quartus Prime Version	Description	Impact
23.1	Updated the Nios® V/m Processor Internal Timer interface.	-

2.2. Nios V/m Processor Intel FPGA IP v22.4.0

Intel Quartus Prime Version	Description	Impact
22.4	Migrated the Nios V processor example designs to the Intel FPGA Design Store. Enabled Zephyr RTOS in the Nios V/m processor.	-

2.3. Nios V/m Processor Intel FPGA IP v22.3.0

Intel Quartus Prime Version	Description	Impact
22.3	Enhanced prefetch logic. Updated the following performance and benchmark numbers: FMAX, Area, Dhrystone, CoreMark Remove exceptionOffset and exceptionAgent parameters from _hw.tcl. Note: Only impacted BSP generation. No impact on RTL or circuit. Changed debug reset: Added ndm_reset_in port Renamed dbg_reset to dbg_reset_out.	-

2.4. Nios V/m Processor Intel FPGA IP v21.3.0

Intel Quartus Prime Version	Description	Impact
22.2	Added a reset request interface Fixed debug reset issue: Removed unused signals that caused a latch interface, Updated the routing of ndmreset to prevent the debug module from resetting.	-

2.5. Nios V/m Processor Intel FPGA IP v21.2.0

Intel Quartus Prime Version	Description	Impact
22.1	Added new design examples in the Nios V/m Processor Intel FPGA IP core parameter editor: uC/TCP-IP IPerf Example Design, uC/TCP-IP Simple Socket Server Example Design Bug Fix: Addressed issues causing unreliable accesses to the MARCHID, MIMPID, and MVENDORID CSRs. Enabled reset capability from the debug module to allow the core to be reset through a debugger. Enabled support for trigger. The Nios V processor core supports 1 trigger. Addressed reported synthesis warnings and lint issues. Addressed an issue from the debug ROM that caused a corruption in the return vector. Fixed an issue which prevented access to GPR 31 from the debug module.	-

2.6. Nios V/m Processor Intel FPGA IP v21.1.1

Intel Quartus Prime Version	Description	Impact
21.4	Bug Fix: Trigger registers accessible but triggers were not supported issue fixed. Illegal instruction exception prompted when accessing trigger registers. Added new Design Example in the Nios V/m Processor Intel FPGA IP core parameter editor. GSFI Bootloader Example Design, SDM Bootloader Example Design	-

2.7. Nios V/m Processor Intel FPGA IP v21.1.0

Intel Quartus Prime Version	Description	Impact
21.3	Initial Release	-

3. Nios V/m Processor Intel FPGA IP (Intel Quartus Prime Standard Edition) Release Notes

3.1. Nios V/m Processor Intel FPGA IP v1.0.0

Intel Quartus Prime Version	Description	Impact
22.1std	Initial release.	-

4. Nios V/g Processor Intel FPGA IP (Intel Quartus Prime Pro Edition) Release Notes

4.1. Nios V/g Processor Intel FPGA IP v1.0.0

Intel Quartus Prime Version	Description	Impact
23.1	Initial release.	-

5. Archives

5.1. Nios V Processor Reference Manual Archives

For the latest and previous versions of this user guide, refer to Nios® V Processor Reference Manual. If an IP or software version is not listed, the user guide for the previous IP or software version applies.

IP versions are the same as the Intel Quartus Prime Design Suite software versions up to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.

5.2. Nios V Embedded Processor Design Handbook Archives

For the latest and previous versions of this user guide, refer to Nios® V Embedded Processor Design Handbook. If an IP or software version is not listed, the user guide for the previous IP or software version applies.

5.3. Nios V Processor Software Developer Handbook Archives

For the latest and previous versions of this user guide, refer to Nios® V Processor Software Developer Handbook. If an IP or software version is not listed, the user guide for the previous IP or software version applies.

	Intel Nios V/m Processor Quick Start Guide This Intel Nios V/m Processor Quick Start Guide (UG-20345) provides a comprehensive introduction to developing embedded systems on Intel FPGAs. It covers hardware and software setup for version 21.3 of Intel Quartus Prime, generating example designs, software development, programming, simulation, and debugging for the RISC-V based Nios V/m processor.
	Intel Nios II and Embedded IP Release Notes This document provides release notes for Intel's Nios II Embedded Design Suite (EDS), Nios II Processor IP, and Embedded IP cores, updated for the Intel Quartus Prime Design Suite version 21.3. It details changes and updates across various software versions.
	25G Ethernet Intel FPGA IP Release Notes Comprehensive release notes detailing updates, bug fixes, and new features for Intel's 25G Ethernet FPGA IP across Intel Agilex, Stratix 10, and Arria 10 device families, including versioning information and compatibility with Intel Quartus Prime software.
	F-Tile JESD204C Intel FPGA IP Design Example User Guide This user guide provides features, usage guidelines, and detailed descriptions for the F-Tile JESD204C Intel FPGA IP design examples using Intel Agilex devices. It covers quick start procedures, detailed component descriptions, clock and reset signals, interface signals, and control registers.
	Intel Agilex FPGA IP: Triple-Speed Ethernet Design Example User Guide This user guide from Intel provides detailed instructions for generating, simulating, and compiling design examples for the Triple-Speed Ethernet Intel Agilex FPGA IP. It covers essential steps for Ethernet MAC functionality, including simulation scripts, hardware testing, and functional descriptions for developers.
	F-Tile Interlaken Intel FPGA IP Design Example User Guide User guide detailing the F-Tile Interlaken Intel FPGA IP design example, covering its generation, simulation, compilation, and testing with Intel Quartus Prime software. Includes hardware and software requirements, directory structure, interface signals, register map, and reset sequences.
	Intel Quartus Prime Standard Edition 22.1std Software and Device Support Release Notes Release notes for Intel Quartus Prime Standard Edition Version 22.1std and 22.1std.1, detailing new features, changes to software behavior, operating system support, memory requirements, device support, EDA interface information, and known issues.
	F-Tile DisplayPort Intel FPGA IP Design Example User Guide This user guide provides instructions and examples for implementing the DisplayPort Intel FPGA IP on Intel Agilex F-tile devices. It covers design generation, simulation, compilation, and hardware testing, including parallel loopback examples with and without AXIS Video Interface.