Micron Technical Note TN-40-07: Calculating Memory Power for DDR4 SDRAM

Introduction

DDR4 SDRAM offers enhanced bandwidth and a lower operating voltage range compared to DDR3 SDRAM. It also features a word-line boost supply of 2.5V for more efficient power delivery. While this results in higher bandwidth with potentially lower or equal system power, accurately determining power consumption within a system application from data sheet specifications can be challenging. This technical note details how DDR4 SDRAM consumes power and provides tools for system designers to estimate power consumption in any specific system. It includes Micron's DDR4-2666 "Data Sheet Specifications" and a DDR4 Power Spreadsheet Usage Example.

Table 1 lists command abbreviations used throughout this document.

DRAM Operation

Estimating DDR4 SDRAM power consumption requires understanding its basic functionality. DRAM operation is primarily controlled by the clock enable (CKE) signal. When CKE is LOW, input buffers are off. For commands to be received, CKE must be HIGH, enabling input buffers and command/address propagation to the DRAM's logic/decoders.

The typical initial command is an ACT (Activate) command, which selects a bank and row address. Data from the selected row is transferred to sense amplifiers. Sixteen array banks (four per bank group) exist in x4 and x8 DDR4 SDRAM; x16 devices have eight banks across two bank groups. Each bank can be activated independently. A bank remains in the active state as long as its sense amplifiers hold data. A PRE (Precharge) command is required to restore data to the array and reset the bank, typically paired with an ACT command, unless a PRECHARGE ALL command is used.

Figure 1: 8Gb, x8 DDR4 SDRAM Functional Block Diagram. This diagram illustrates the internal architecture of a DDR4 SDRAM, showing key functional blocks such as command decoding, address registers, memory array, sense amplifiers, I/O gating, and data interfaces, highlighting the flow of data and control signals.

In the active state, DDR4 devices perform READs and WRITEs. A READ command decodes a column address, and data from sense amplifiers is driven through the I/O and READ latch to the output drivers. WRITE operations are similar but in reverse: data from DQ pins is latched, transferred to internal drivers, and then to sense amplifiers. DDR4 includes On-Die Termination (ODT) on data I/O pins, which consumes additional power when active and offers advanced mode register settings for system flexibility and signal integrity. DDR4 also incorporates a VPP supply for the internal word line boost. The majority of VPP current is drawn during ACT, PRE, or REF commands.

The DDR4 device calculation procedure accounts for VPP supply needs, mirroring VDD analysis. Standby currents are denoted as IPP2P, IPP2N, IPP3P, and IPP3N, with IPP3N often used for similar states. Read/write currents are IPP4R and IPP4W, while activate and refresh currents use IPP0 and IPP5B respectively.

Figure 2: Vpp Currents Command Dependant. This graph illustrates the current draw from the VPP supply across different command states, showing how current varies based on DRAM activity like Activate, Precharge, Write, Read, and Refresh.

DRAM Power Calculators

The IDD values referenced in this article are sourced from Micron's 8Gb DDR4-2666 data sheet. While specific values may vary between vendors and devices, the principles of power calculation remain consistent. It is crucial to verify all data sheet parameters before applying this information.

Methodology Overview

Calculating system power involves four key steps:

1. Calculate power subcomponents from data sheet specifications (Pds[XXX]).
2. Derate power based on system command scheduling (Psch[XXX]).
3. Derate power to the system's actual operating VDD and clock frequency (Psys[XXX]).
4. Sum all subcomponents under system operating conditions to find total DRAM power consumption.

Background Power

CKE acts as the primary on/off switch for DDR4 SDRAM. When CKE is LOW, inputs are disabled, resulting in the lowest power state. If all banks are precharged, this state is IDD2P; if any bank is open, it's IDD3P. CKE must be HIGH for commands like ACT, PRE, READ, and WRITE. When CKE goes HIGH, command decoders activate, increasing power consumption. This is specified as IDD2N (precharged banks) or IDD3N (active banks).

Figure 3: Effects of CKE on IDD Consumption. This diagram shows the relationship between the clock signal (CLK) and the CKE signal, illustrating how changes in CKE state (HIGH/LOW) affect the DRAM's current consumption (IDD), distinguishing between precharged (IDD2P/IDD2N) and active states.

Standby power calculations involve multiplying the IDD values by the applied voltage (VDD).

Data sheet specifications use worst-case VDD (1.260V) and VPP (2.75V) for DDR4. The following tables show calculations for maximum DDR4 standby powers based on these assumptions.

Background power is categorized into four types based on bank precharge status and CKE state. The ratio of these powers determines the total average background power. Table 6 lists the components used to determine these ratios.

Equation 9 calculates the ratio of data sheet background powers to system usage conditions based on CKE HIGH/LOW times.

Activate Power

To perform READ or WRITE operations, a DDR4 SDRAM requires an ACT command to select a bank and row, followed by a PRE command to close the row. The ACT command initiates data transfer from the array to sense amplifiers, consuming significant current. The DRAM remains active until the PRE command restores data and resets the bank.

Figure 4: IDD0 Current Profile. This graph illustrates the current profile (IDD0) during ACT and PRE command cycles. It shows the peak current during activation and the average current consumed while the row is active, distinguishing between the active state (IDD3N) and precharged state (IDD2N).

The data sheet specifies IDD0 averaged over the tRC interval between ACT commands. Background currents (IDD3N when active, IDD2N when precharged) are subtracted from IDD0 to isolate ACT/PRE command power.

Equation 10 calculates maximum power at minimum tRC. System operation often differs, requiring scaling based on tRRDscheduled (tRRDsch), the average scheduled row-to-row activate timing.

Figure 5: ACT-ACT Current with tRRDsch = 52.5ns. This graph displays the current profile for ACT commands with a tRRDsch of 52.5ns, illustrating how a longer interval between activations affects power consumption compared to the data sheet's tRC.

Changing tRRDsch from 46.16ns to 52.5ns reduces activation power from 10.6mW to 9.3mW. This calculation excludes background power.

Figure 6: ACT-ACT Current with tRRDsch = 23.08ns. This graph shows current profiles for interleaved banks with a tRRDsch of 23.08ns, illustrating the combined current from multiple active banks and highlighting the impact of shorter activation intervals.

For two interleaved banks, Psch(ACT) can increase from 10.6mW to 21.2mW due to doubled ACT/PRE power consumption. This methodology allows calculation for various bank interleaving scenarios.

Write Power

After a bank is active, data can be read or written. WRITE operations involve data transfer from DQ pins to internal drivers and then to sense amplifiers. Several WRITE commands can occur between ACT commands.

Figure 7: Current Profile – WRITES. This graph displays the current profile during WRITE operations, showing the impact of multiple WRITE commands and illustrating the difference between total current and the current attributable solely to WRITEs after subtracting standby current.

The current associated with WRITEs is IDD4W. To isolate WRITE power, IDD3N (standby current) is subtracted. Equation 13 shows the calculation for base write power.

Write bandwidth utilization (WRsch%) scales data sheet power to actual power. WRsch% is the ratio of clock cycles with write data on the bus to total clock cycles.

Scheduled WRITE power (Psch(WR)) is calculated from base write power and WRsch%.

Read Power

READ operations are similar to WRITEs, involving an ACT command, followed by READs, and then a PRE command. The current profile for READs closely resembles that of WRITEs, with IDD4R replacing IDD4W.

Figure 8: Current Profile – READs. This graph displays the current profile during READ operations, showing patterns similar to WRITEs but with IDD4R used for calculation. It illustrates the current consumed during sequences of ACT, READ, and PRE commands.

Read bandwidth utilization (RDsch%) scales data sheet power to actual power. RDsch% is the ratio of clock cycles with read data on the bus to total clock cycles.

Scheduled READ power (Psch(RD)) is calculated from base read power and RDsch%.

I/O Termination Power

Data sheet specifications typically exclude output driver and ODT power, which are system-dependent. DDR4 systems vary in density and form factor, influencing these power requirements. Figure 9 illustrates a typical system DQ termination for READ and WRITE I/O power.

Figure 9: Typical System DQ Termination. This figure presents circuit diagrams illustrating READ and WRITE I/O power configurations, showing the controller, DRAMs, and termination resistors (RON, RTT) involved in signal integrity.

The drivers have an impedance (RON) that pulls the bus towards VDDQ or VSSQ. On-die termination acts as a pull-up resistor. Table 25 outlines a simple termination scheme for an example system.

Power calculation for output drivers and ODT can be done via simulation or by calculating DC power. The I/O powers to consider are PdqRD (output driver power), PdqWR (write termination power), PdqRDoth (read termination power from another DRAM), and PdqWRoth (write termination power to another DRAM).

Figure 10: DRAM READ. This diagram shows the READ I/O power circuit and provides input fields for termination values (RTTuC, Rz1, RTTu2, Rs1, Rs2) and calculated output values (N3, N1, N2, RTTuC, Rz, RTTd2, Rs1, Rs2, pdqRD, pdqRDoth), illustrating the calculation of termination power for READ operations.

Figure 11: DRAM WRITE. This diagram shows the WRITE I/O power circuit and provides input fields for termination values (RzC, RTTu1, RTTu2, Rs1, Rs2) and calculated output values (N3, N1, N2, RzC, RTTPUd1, RTTPUd2, Rs1, Rs2, pdqWR, pdqWRoth), illustrating the calculation of termination power for WRITE operations.

To calculate total I/O and termination power, power per DQ is multiplied by the number of DQ and strobes (num_DQR). For write termination, data masks (num_DQW) are also included. VPP is not affected by I/O and termination power.

Equation 19 calculates DRAM power for four I/O buffer operations: Pds(DQ), Pds(termW), Pds(termRoth), and PPds(termWoth).

Using an x8 device example, num_DQR is 10 (8 DQ + 2 DQS) and num_DQW is 11 (includes data mask). Equation 20 shows the calculation of DC power values.

I/O and termination power must be derated by data bus utilization (RDsch% and WRsch%). Additional terms, termRDsch% and termWRsch%, are used for termination data to/from another DRAM. Power based on command scheduling is calculated in Table 29.

Refresh Power

Refresh is essential for maintaining data integrity in DDR4 memory cells. The specification for refresh is IDD5B, assuming continuous operation at minimum REFRESH-to-REFRESH command spacing (tRFC MIN). IDD5R may be used in some data sheets and can be converted to IDD5B.

IDD3N standby current is also consumed during refresh. Equation 22 subtracts IDD3N to calculate refresh power.

Derating refresh power to use conditions:

Power Derating

Power calculations thus far assume worst-case VDD and data sheet clock frequency. Psch(XXX) denotes this power. Actual systems may operate at different voltages or frequencies. Power components must be derated to actual system conditions, resulting in Psys(XXX).

Voltage Supply Scaling

Most applications use nominal VDD, not the maximum. Data I/O and termination power do not scale with VDD as system VDD is already factored in. Power is typically related to the square of the voltage (P = CV²f).

Frequency Scaling

Power components like Psch(PRE_PDN), Psch(ACT_PDN), etc., are frequency-dependent and scale with clock frequency. Psch(REF) does not scale with frequency, and Psch(ACT) depends on ACT command intervals.

Frequency-dependent power can be scaled using Equation 25.

The combination of VDD and clock frequency scaling is presented in Equation 26.

Calculating Total DRAM Power

All power subcomponents are summed to calculate total system power.

After compensating for all variables, the total power dissipation of a DDR4 device under specific system usage conditions is calculated.

DDR4 Power Spreadsheet

Calculating these equations manually can be extensive. Micron offers an online DDR4 SDRAM System-Power Calculator for simplification, available at micron.com/systemcalc. The tool requires inputting data sheet conditions on the "DDR4 Spec" tab, followed by selecting the DRAM configuration (density, I/O, speed grade, DBI) on the "DRAM Config" tab.

Figure 12: Spreadsheet – DRAM Configuration Tab. This screenshot shows the 'DRAM Config' tab of the Micron DDR4 Power Calculator spreadsheet, where users select DRAM density, speed grade, width, and DBI mode.

System operating conditions (VDD, clock frequency, bus utilization, CKE conditions) are then entered on the "System Config" tab.

Figure 13: Spreadsheet – System Configuration Tab. This screenshot displays the 'System Config' tab of the Micron DDR4 Power Calculator, detailing system parameters like VDD, VPP, clock frequency, burst length, I/O power values, and utilization percentages.

Figure 14: Mobile/Desktop System. This diagram illustrates a typical mobile/desktop system setup with two ranks of DDR4 SDRAM connected to a controller, highlighting the data bus and chip select signals.

Figure 15: DRAM Configuration. This is a repeat of Figure 12, showing the 'DRAM Config' tab for selecting DRAM parameters.

Figure 16: System Configuration. This is a repeat of Figure 13, showing the 'System Config' tab for inputting system parameters.

The spreadsheet calculates subcomponents of power and derates them to system conditions. For example, in a system with DDR4 DRAM, background operations might consume 85.5mW, row activation 153.9mW, and read/write operations 168.8mW per DRAM.

The total power for each DDR4 DRAM is approximately 408.3mW. For a system with multiple DRAMs, this value is multiplied accordingly.

Figure 17: Power Consumption Summary by Device. This table summarizes the total power consumption for DDR4 SDRAM, broken down by category (ACT, RD, WR, etc.) and voltage supply (VDD, VPP).

Figure 18: Power Consumption per Device. This bar chart visually represents the power consumption per device, differentiating between VDD and VPP contributions for background, RD/WR/Term, and Activate power.

Conclusion

Determining DDR4 device power consumption solely from a data sheet can be difficult. By understanding the data sheet and the device's power behavior, system designers can create power models based on system usage conditions. These models enable experimentation with memory access schemes, power-down strategies (CKE=LOW), and data access patterns (page hit percentages) to optimize power consumption. This approach allows for realistic power requirement estimation and adjustment of system power delivery and thermal budgets for improved performance.

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This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change as further product development and data characterization occur.