GW5AR-25 FPGA Device Pinout and Version History
Version History
| Date | Version | Description |
|---|---|---|
| 2023/9/8 | 1.0 | Initial version, supports UG256P package. |
| 2023/11/10 | 1.0.1 | Updated X16 information for TrueLVDS page. |
| 2023/12/7 | 1.0.2 | Removed MCKTEST, ADCINCLK, ADCOTEST pin configuration information. |
| 2023/12/14 | 1.0.3 | Optimized pin descriptions on the Pin Definitions page. |
| 2024/2/2 | 1.0.4 | Updated pin and power information for all pins in the UG256P package. |
| 2024/4/18 | 1.0.5 | Optimized pin direction descriptions on the Pin Definitions page. |
| 2024/5/22 | 1.0.6 | Removed X16 information. |
| 2024/6/7 | 1.0.7 | Updated comment for VCC_REG pin on the Pin Definitions page. |
| 2024/7/5 | 1.0.8 | Updated maximum voltage for VCC on the Power page. |
| 2025/2/7 | 1.0.9 | Updated maximum voltage for VCCX on the Power page. |
| 2025/3/7 | 1.1 | Optimized pin definition descriptions for MIPI D-PHY on the Pin Definitions page. |
| 2026/6/20 | 1.1.1 | Removed SDA and SCL pins for the UG256P package. |
Pin Definitions
This section details the pin functions and configurations for the GW5AR-25 FPGA.
| Pin Name | Direction | Description |
|---|---|---|
| IO[End][Row/Column Number][A/B] | I/O/LVDS | Provides pin location information within the device, including L(left), R(right), B(bottom), T(top). [Row/Column Number] provides row/column information. [A/B] indicates differential signal pairs. LVDS direction indicates the pin supports true LVDS output. |
| [pin]_[End][Row/Column Number][A/B] | I/O | Pin name and other information as above. For package pin shorting IO, sorted by number. The first IO uses the pin name, and subsequent shorted pins use the pin name with IO information removed and concatenated, e.g., IOR1A/IOB14A shorted, if the pin name is C1, then IOR1A corresponds to C1, and IOB14A corresponds to C1_B14A. |
| Multi-function Pins | Multi-function pins definition: /MMM indicates additional functions beyond the user I/O function. When these functions are not used, the pins can be used as user I/O. | |
| D00~D07 | I/O, internal weak pull-up | CPU Mode: Data input/output pins D00~D07 |
| D08~D15 | I/O, internal weak pull-up | CPU Mode: Data input pins D08~D15 |
| MIO | I/O, internal weak pull-up | MSPI Mode: Serial command and address output, and input pins for parallel data bit0 in X2, X4 mode, connecting to external Flash device DQ0/D/SI/IO0 pins. |
| MI1 | I/O, internal weak pull-up | MSPI Mode: Serial data input in X1 mode, input pins for parallel data bit1 in X2, X4 mode, connecting to external Flash device DQ1/Q/SO/IO1 pins. |
| MI2 | I/O, internal weak pull-up | MSPI Mode: Input pins for parallel data bit2 in X4 mode, connecting to external Flash device DQ2/W#/WP#/IO2 pins. |
| MI3 | I/O, internal weak pull-up | MSPI Mode: Input pins for parallel data bit3 in X4 mode, connecting to external Flash device DQ3/HOLD#/IO3 pins. |
| CCLK | I/O, internal weak pull-up | Configuration clock signal. When used as external input, it requires an external clock source. |
| EMCCLK | I/O, internal weak pull-up | Master Mode: EMCCLK is used for FPGA configuration logic and outputting the CCLK clock source. Slave Mode: EMCCLK has no association with slave mode. |
| MOSI | I/O, internal weak pull-up | MSPI Mode: Serial command and address output, and input pins for parallel data bit0 in X2, X4 mode, connecting to external Flash device DQ0/D/SI/IO0 pins. |
| MISO | I/O, internal weak pull-up | MSPI Mode: Serial data input in X1 mode, input pins for parallel data bit1 in X2, X4 mode, connecting to external Flash device DQ1/Q/SO/IO1 pins. |
| MCS_N | O, internal weak pull-up | MSPI Mode: Enable signal MCS_N, active low. |
| MODE[1:0] | Internal weak pull-up | MODE[1:0]: Internal weak pull-up. |
| MODE[2:0] | None | MODE[2:0]: None. |
| SO | O, internal weak pull-up | SSPI Mode: SO. |
| SI | I, internal weak pull-up | SSPI Mode: SI. |
| SSIO | I, internal weak pull-up | QSSPI Configuration Mode: Data input pin. |
| SSI1 | I, internal weak pull-up | QSSPI Configuration Mode: Data input pin. |
| SSI2 | I, MODE[1:0]: Internal weak pull-up, MODE[2:0]: None | QSSPI Configuration Mode: Data input pin. |
| SSI3 | I, internal weak pull-up | QSSPI Configuration Mode: Data input pin. |
| SSPI_CLK | I, internal weak pull-up | SSPI/QSSPI Configuration Mode: Clock input pin. |
| SSPI_CS_N | I, internal weak pull-up | SSPI Mode: Enable signal SSPI_CS_N, active low, internal weak pull-up. |
| SSPI_WPN | I, MODE[1:0]: Internal weak pull-up, MODE[2:0]: None | SSPI Mode: Enable signal SSPI_WPN, active low, internal weak pull-up. |
| CLKHOLD_N | I, internal weak pull-down | In SSPI Mode, active low. |
| CSI_B | I, internal weak pull-up | CPU Mode: Chip select signal active low. Master CPU Mode: Connects to external configuration controller's chip select signal, or can be directly grounded or connected via a 1KΩ resistor. Slave CPU Mode: External configuration controller controls the CSI_B signal to select the FPGA. Master and Slave modes are issued by the external controller; CSI_B signals in other modes are not related. Used in FPGA cascade configuration mode (Daisy Chain) to connect to the next device. |
| CSO_B | O, internal weak pull-up | SERIAL Mode: Output configuration data for the next device. Master SPI Mode: Output configuration data for the next device. CPU Mode: Output chip select signal for the next device. Configuration process weak pull-up selection signal pin. |
| PUDC_B | I, internal weak pull-down | FPGA powers up with internal weak pull-up resistors enabled in low-level configuration. PUDC_B low level: All GPIOs except PUDC_B have weak pull-up. PUDC_B high level: All GPIOs are high impedance. PUDC_B cannot be left floating during configuration. |
| RDWR_B | I, internal weak pull-down | CPU Mode: Data read/write control signal. When RDWR is high, FPGA outputs data; when low, the external controller writes data to FPGA. Master CPU Mode: Can connect to external controller's RDWR signal, or can be directly grounded or connected via a ≤1kΩ resistor to GND. Slave CPU Mode: External controller's RDWR signal. The lower 8 bits of CPU mode are affected by the RDWR status after FPGA wakeup; the lower 8 bits of CPU mode setting are not affected by RDWR. |
| GCLKC_[x]A / GCLKT_[x]A | I | GCLKT_[x]A: Default dedicated pin for GCLKC_[x], [x] is the clock sequence number. |
| GCLKC_[x]B / GCLKT_[x]B | I | GCLKT_[x]B: Configurable as a dedicated differential input pin for GCLKC_[x]. When A is not used as a dedicated GCLK pin, it can be configured to achieve GCLK pin functionality. [x] is the clock sequence number. |
| GCLKC_[x]A | I | GCLKC_[x]A: Default dedicated pin for GCLKT_[x], [x] is the clock sequence number. |
| GCLKC_[x]B | I | GCLKC_[x]B: Configurable as a dedicated differential input pin for GCLKT_[x]. When A is not used as a dedicated GCLK pin, it can be configured to achieve GCLK pin functionality. [x] is the clock sequence number. |
| DOUT | O | SERIAL Mode: Data output. |
| DIN | I, internal weak pull-up | SERIAL Mode: Data input. |
| TMS | I, internal weak pull-up | JTAG Mode: Serial input. |
| TCK | I, internal weak pull-up | JTAG Mode: Serial clock input. |
| TDO | O, internal weak pull-up | JTAG Mode: Serial data output. |
| TDI | I, internal weak pull-up | JTAG Mode: Serial data input. |
| RECONFIG_N | I, internal weak pull-up | Global reset GowinCONFIG logic signal, active low. |
| DONE[1] | O, internal weak pull-up | High level indicates successful programming configuration. Low level indicates programming configuration failure or incomplete programming. When DONE signal is low, the chip startup is delayed until the DONE signal is high. |
| READY[1] | I/O, internal weak pull-up | Low level indicates that the device cannot be programmed. High level indicates that the device can be programmed. |
| LPLL_C_FB/RPLL_C_FB/T PLL_C_FB/BPLL_C_FB | I/O, internal weak pull-up | Left/Right/Top/Bottom PLL feedback input pins, C (Comp). |
| LPLL_T_FB/RPLL_T_FB | I/O, internal weak pull-up | Left/Right/Top/Bottom PLL feedback input pins, T (True). |
| LPLL_C_IN/RPLL_C_IN | I/O, internal weak pull-up | Left/Right/Top/Bottom PLL clock input pins, C (Comp). |
| LPLL_T_IN/RPLL_T_IN/TP | I/O, internal weak pull-up | Left/Right/Top/Bottom PLL clock input pins, T (True). |
| LL_T_IN/BPLL_T_IN | I/O, internal weak pull-up | Left/Right/Top/Bottom PLL clock input pins, T (True). |
| MODE2 | I, internal weak pull-up | "GND", indicates the pin is internally grounded. |
| MODE1 | I, internal weak pull-up | "GND", indicates the pin is internally grounded. |
| MODE0 | I, internal weak pull-up | GowinCONFIG configuration mode selection signal port: If the pin is marked as "VCCIO", it indicates the pin has internal power; if marked as "GND", it indicates the pin is internally grounded. |
| DQ* | Default as DQ pins within the DQS* group; can be configured via software as DQS data pins within the DQS* group. | |
| DQS* | Default as DQS pins within the DQS* group; can be configured via software as DQ data pins within the DQS* group. | |
| DQ1/DQS_01 | I/O | Default as DQ data pins within the DQS1 group; can be configured via software as DQS pins within the DQS0 group, or as DQS pins within the DQS1 group. |
| DQ2/DQS_23 | I/O | Default as DQ data pins within the DQS2 group; can be configured via software as DQS pins within the DQS2 group, or as DQS pins within the DQS3 group. |
| DQ5/DQS_45 | I/O | Default as DQ data pins within the DQS5 group; can be configured via software as DQS pins within the DQS4 group, or as DQS pins within the DQS5 group. |
| DQ6/DQS_67 | I/O | Default as DQ data pins within the DQS6 group; can be configured via software as DQS pins within the DQS6 group, or as DQS pins within the DQS7 group. |
| DQ10/DQS_910 | I/O | Default as DQ data pins within the DQS10 group; can be configured via software as DQS pins within the DQS9 group, or as DQS pins within the DQS10 group. |
| VSS | NA | Ground pin. |
| VCC | NA | Core power supply pin. |
| VCCIO# | NA | I/O BANK power supply pin. |
| VCCX | NA | Auxiliary power supply pin. |
| VCCLDO [1] | NA | Power supply pin for the internal LDO module that provides voltage for SRAM. |
| VEFUSE [2] | NA | Power supply pin for eFuse write operation. |
| VDD12M | NA | MIPI module LP mode power supply pin. |
| VDDXM | NA | MIPI module auxiliary power supply pin. |
| VDDAM | NA | MIPI module analog circuit power supply pin. |
| VDDDM | NA | MIPI module digital circuit power supply pin. |
| VDDDP | NA | PSRAM power supply pin. |
| VDDQP | NA | Power supply pin for PSRAM data bus. |
| NC | NA | Reserved, not used. |
| ADCINCLK | ADC | ADC clock input pin. |
| ADCVN | DIO | SENSOR differential analog signal input pin. |
| ADCVP | DIO | SENSOR differential analog signal input pin. |
| M0_CKN | DIO | MIPI_DPHY clock channel differential input/output pin. |
| M0_CKP | DIO | MIPI_DPHY clock channel differential input/output pin. |
| M0_D0N | DIO | MIPI_DPHY data channel 0 differential input/output pin. |
| M0_D0P | DIO | MIPI_DPHY data channel 0 differential input/output pin. |
| M0_D1N | DIO | MIPI_DPHY data channel 1 differential input/output pin. |
| M0_D1P | DIO | MIPI_DPHY data channel 1 differential input/output pin. |
| M0_D2N | DIO | MIPI_DPHY data channel 2 differential input/output pin. |
| M0_D2P | DIO | MIPI_DPHY data channel 2 differential input/output pin. |
| M0_D3N | DIO | MIPI_DPHY data channel 3 differential input/output pin. |
| M0_D3P | DIO | MIPI_DPHY data channel 3 differential input/output pin. |
Power Specifications
This section details the power requirements for the GW5AR-25 FPGA.
| Name | Description | Minimum Value | Maximum Value |
|---|---|---|---|
| FPGA Logic | Core voltage, LV | 0.87V | 1.03V |
| Vcc | Core voltage, EV | 1.14V | 1.8V |
| VCCIO | I/O Bank power supply | 1.14V | 3.465V |
| VCCIO1 | I/O Bank1 power supply, connected to PSRAM interface, VCCIO1 provides PSRAM working voltage | 1.71V | 1.89V |
| Vccx | Auxiliary voltage | 2.375V | 3.465V |
| VCCLDO [1] | Power supply voltage for the internal LDO module that provides voltage for SRAM | 1.14V | 3.3V |
| VEFUSE [2] | Voltage required for eFuse write operation | 1.62V | 1.98V |
| VDDAM | MIPI module analog circuit power supply | 0.87V | 1V |
| VDDDM | MIPI module digital circuit power supply | 0.87V | 1V |
| VDDXM | MIPI module auxiliary analog power supply | 2.375V | 3.465V |
| VDD12M | MIPI module LP mode power supply | 1.14V | 1.32V |
| VDDP | PSRAM power supply | 1.71V | 1.89V |
| VDDQP | PSRAM data bus power supply | 1.71V | 1.89V |
Notes:
- [1] VCCLDO: Higher voltage leads to higher power consumption.
- [2] When the eFuse write operation is not required, this power supply can be connected to GND or left floating.
- If multiple power supplies are shorted on certain packages or PCBs, the intersection of the voltage ranges for all shorted power supplies must be considered, satisfying the requirements of multiple power supplies simultaneously.
Pin List UG256P
This section provides a detailed pin list for the UG256P package.
| Pin Name | Function | BANK | DQS | Configuration Function | Differential Pair | LVDS | UG256P |
|---|---|---|---|---|---|---|---|
| IOB10A/D03/SSPI_CS_N | I/O | 5 | none | D03/SSPI_CS_N | True of IOB10B | True | D3 |
| IOB10B/D04/SI/SSIO | I/O | 5 | none | D04/SI/SSIO | Comp_of_IOB10A | True | D2 |
| IOB12A/GCLKT_10B[1]/D07/SSPI_WPN/SSI2/LPLL1_T_IN1 | I/O | 5 | none | GCLKT_10B/D07/SSPI_WPN/SSI2/LPLL1_T_IN1 | True_of_IOB12B | True | E1 |
| IOB12B/GCLKC_10B[1]/RDWR_B/LPLL1_C_IN1 | I/O | 5 | none | GCLKC_10B/RDWR_B/LPLL1_C_IN1 | Comp_of_IOB12A | True | D1 |
| IOB14A/SSPI_CLK | I/O | 5 | none | SSPI_CLK | True_of_IOB14B | True | F2 |
| IOB14B/CLKHOLD_N/SSI3 | I/O | 5 | none | CLKHOLD_N/SSI3 | Comp_of_IOB14A | True | F1 |
| IOB16A | I/O | 5 | none | True of IOB16B | True | F5 | |
| IOB16B | I/O | 5 | none | Comp_of_IOB16A | True | E5 | |
| IOB18A | I/O | 5 | none | True of IOB18B | True | F4 | |
| IOB18B | I/O | 5 | none | Comp_of_IOB18A | True | F3 | |
| IOB1A/RECONFIG_N | I/O | 5 | none | RECONFIG_N | none | A2 | |
| IOB22A | I/O | 5 | none | True of IOB22B | True | G5 | |
| IOB22B | I/O | 5 | none | Comp_of_IOB22A | True | H5 | |
| IOB24A | I/O | 5 | none | True of IOB24B | True | G2 | |
| IOB24B | I/O | 5 | none | Comp_of_IOB24A | True | G1 | |
| IOB26A/GCLKT_9B[1] | I/O | 5 | none | GCLKT_9B | True_of_IOB26B | True | H2 |
| IOB26B/GCLKC_9B[1] | I/O | 5 | none | GCLKC_9B | Comp_of_IOB26A | True | H1 |
| IOB29A/GCLKT_11A[1] | I/O | 4 | none | GCLKT_11A | True_of_IOB29B | True | H4 |
| IOB29B/GCLKC_11A[1] | I/O | 4 | none | GCLKC_11A | Comp_of_IOB29A | True | H3 |
| IOB2A | I/O | 5 | none | True of IOB2B | True | F6 | |
| IOB2B | I/O | 5 | none | Comp_of_IOB2A | True | E6 | |
| IOB31A/GCLKT_10A[1]/D14/BPLL_T_FB0 | I/O | 4 | none | GCLKT_10A/D14/BPLL_T_FB0 | True_of_IOB31B | True | J2 |
| IOB31B/GCLKC_10A[1]/D15/BPLL_C_FB0 | I/O | 4 | none | GCLKC_10A/D15/BPLL_C_FB0 | Comp_of_IOB31A | True | J1 |
| IOB33A/GCLKT_9A[1]/D13/BPLL_T_IN1 | I/O | 4 | none | GCLKT_9A/D13/BPLL_T_IN1 | True_of_IOB33B | True | J4 |
| IOB33B/GCLKC_9A[1]/EMCCLK/BPLL_C_IN1 | I/O | 4 | none | GCLKC_9A/EMCCLK/BPLL_C_IN1 | Comp_of_IOB33A | True | J3 |
| IOB35A/GCLKT_8 | I/O | 4 | none | GCLKT_8 | True_of_IOB35B | True | K2 |
| IOB35B/GCLKC_8 | I/O | 4 | none | GCLKC_8 | Comp_of_IOB35A | True | K1 |
| IOB37A/READY | I/O | 4 | none | READY | True_of_IOB37B | True | L2 |
| IOB37B/MCS_N/CSO_B | I/O | 4 | none | MCS_N/CSO_B | Comp_of_IOB37A | True | L1 |
| IOB50A/D11 | I/O | 4 | none | D11 | True_of_IOB50B | True | M2 |
| IOB50B/D12 | I/O | 4 | none | D12 | Comp_of_IOB50A | True | M1 |
| IOB52A/MODE1 | I/O | 4 | none | MODE1 | True_of_IOB52B | True | N2 |
| IOB52B/D10 | I/O | 4 | none | D10 | Comp_of_IOB52A | True | N1 |
| IOB54A/GCLKT_11B[1]/D01/MI2/BPLL_T_FB1 | I/O | 4 | none | GCLKT_11B/D01/MI2/BPLL_T_FB1 | True_of_IOB54B | True | P2 |
| IOB54B/GCLKC_11B[1]/D02/MI3/BPLL_C_FB1 | I/O | 4 | none | GCLKC_11B/D02/MI3/BPLL_C_FB1 | Comp_of_IOB54A | True | P1 |
Bank Definitions
This section outlines the I/O banks and their associated reference voltages.
| Bank | Reference Voltage (VREF) | I/O Bank Description |
|---|---|---|
| IO Bank7 | Independent reference voltage (VREF). | |
| IO Bank0 | Independent reference voltage (VREF). | |
| IO Bank1 | Independent reference voltage (VREF). | |
| IO Bank6 | Independent reference voltage (VREF). | |
| MIPI | Independent reference voltage (VREF). | |
| JTAG | Independent reference voltage (VREF). | |
| I/O Bank2 | Independent reference voltage (VREF). | |
| Bank11 | Independent reference voltage (VREF). | |
| CFG | Independent reference voltage (VREF). | |
| I/O Bank5 | Independent reference voltage (VREF). | |
| I/O Bank4 | Independent reference voltage (VREF). | |
| I/O Bank3 | Independent reference voltage (VREF). |
Notes:
- [1] Each bank also provides an independent reference voltage (VREF).
- [2] Users can select the internal VREF source of the IOB (0.6V, 0.75V, 0.9V, 1.25V, 1.5V, and proportional voltages based on VCCIO (36%, 50%, 64%)).
- [3] Users can also select an external VREF input (using any I/O pin in the bank as an external VREF input).
