Intel® Agilex™ Hard Processor System Component Reference Manual

1. Introduction to the Intel® Agilex™ Hard Processor System Component

The hard processor system (HPS) component is a wrapper that interfaces logic in your design to the HPS hard logic, simulation models, bus functional models (BFMs), and software handoff files. It instantiates the HPS hard logic and enables soft components to interface with it, occupying a small footprint in the FPGA fabric for soft-to-hard logic connection.

Platform Designer can be used to ensure interoperability by adapting Avalon® Memory-Mapped (Avalon-MM) interfaces to AXI*, handling data width mismatches, and clock domain transfer crossings. This allows interfacing with Intel®, customer, or third-party FPGA core IP without creating integration logic.

For more information about the HPS system architecture and features, refer to the "Introduction to the Hard Processor" chapter in the Intel Agilex™ Hard Processor System Technical Reference Manual.

1.1. Cortex*-A53 MPCore* Processor

The HPS includes an Arm® Cortex*-A53 MPCore* Processor composed of four Armv8-A architecture central processing units (CPUs).

1.2. CoreSight* Debug Components

The Arm CoreSight* debug components include:

• Debug Access Port (DAP)
• System Trace Macrocell (STM)
• Embedded Trace FIFO (ETF)
• AMBA* Trace Bus Replicator
• Embedded Trace Router (ETR)
• Trace Port Interface Unit (TPIU)
• Embedded Cross Trigger (ECT)

1.3. Interconnect

The HPS system interconnect supports:

• Configurable Arm TrustZone*-compliant firewall and security support, allowing secure or non-secure access for each peripheral and individual transactions.
• A multi-tiered bus structure separating high bandwidth masters from lower bandwidth peripherals.
• Quality of service (QoS) with three programmable levels.
• On-chip debugging and tracing capabilities, based on Arteris* FlexNoC* network-on-chip (NoC) interconnect technology.

1.4. FPGA Bridges

FPGA bridges provide communication channels between the HPS and the FPGA fabric. Some interfaces include:

• FPGA-to-SoC bridge
• SoC-to-FPGA bridge
• Lightweight SoC-to-FPGA bridge

1.5. Memory Controllers

The HPS includes two memory controller peripherals:

• NAND Flash Controller
• SD/MMC Controller

1.6. Support Peripherals

The HPS includes the following support peripherals:

• Clock Manager
• Reset Manager
• System Manager
• Timer
• Watchdog Timer
• Direct Memory Access (DMA) Controller
• Error Checking and Correction Controller

1.6.1. Interface Peripherals

Interface peripherals include:

• Ethernet Media Access Controllers (EMAC)
• USB 2.0 On-The-Go (OTG) Controllers
• I2C Controllers
• UARTS
• SPI Master Controllers
• SPI Slave Controllers
• GPIO Interfaces

1.6.2. On-Chip Memories

On-Chip RAM is the only on-chip memory.

1.7. Introduction to the HPS Component Revision History

2. Configuring the Intel Agilex Hard Processor System Component

This chapter describes the parameters and interfaces available in the HPS component parameter editor within Platform Designer.

2.1. Parameterizing the HPS Component

To parameterize the HPS component:

1. Install the Intel Quartus® Prime Pro Edition design software with Intel Agilex device support. Instructions are available at: Intel Download Center.
2. Open the Intel Quartus Prime software.
3. Open Platform Designer by selecting Tools > Platform Designer.
4. Select an existing Intel Quartus Prime project and Platform Designer system, or create new files. Ensure the correct Intel Agilex device is selected in the Device Family and Device Part dropdowns.
5. In the IP Catalog tab, navigate to Library > Processors and Peripherals > Hard Processor Systems > Hard Processor System Intel Agilex FPGA IP.

2.2. FPGA Interfaces

The FPGA Interfaces tab allows configuration of primary interfaces between the FPGA and the HPS. Key groups include:

• General
• HPS FPGA AXI Bridges
• HPS Boot Source
• DMA Peripheral Request
• Interrupts

2.2.1. General Interfaces

2.2.1.1. Enable MPU Standby and Event Interfaces

Enabling MPU standby and event signals notifies the FPGA fabric when the MPU is in standby. Event signals wake up Cortex-A53 processors from a wait-for-event (WFE) state. This option enables the h2f_mpu_events conduit, comprising signals like:

• h2f_mpu_events: Input signal for FPGA to signal events to all processors, waking them from WFE state. Asserting this signal is equivalent to the Cortex-A53 SEV instruction. It requires a minimum of two MPU clock cycles to be asserted high for processor recognition.
• h2f_mpu_evento: Output signal from any MPU core to the FPGA fabric, asserted when an SEV instruction is executed. This is a multi-cycle pulse, requiring a rising edge detector in the FPGA logic.
• h2f_mpu_standbywfe[3:0]: Output per processor indicating WFE standby mode (high when in standby).
• h2f_mpu_standbywfi[3:0]: Output per processor indicating wait-for-interrupt (WFI) standby mode (high when in standby).

2.2.1.2. Enable General Purpose Signals

Enabling general purpose signals activates the h2f_gp conduit, a pair of 32-bit uni-directional interfaces between the HPS System Manager and the FPGA fabric. These signals are h2f_gp_in (input to HPS) and h2f_gp_out (output from HPS).

2.2.1.3. Enable Debug APB Interface

The debug Advanced Peripheral Bus (APB)* interface allows FPGA debug components to access HPS debug components. Enabling this option provides interfaces and signals such as:

2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events

This interface allows FPGA logic to insert messages into the trace stream. Enabling it activates the h2f_cs and f2h_stm_hw_events conduits.

2.2.1.5. Enable FPGA Cross Trigger Interface

The cross trigger interface (CTI) connects trigger sources and sinks in FPGA logic with the embedded cross trigger (ECT). Enabling this option activates the h2f_cti conduit, comprising signals like:

• h2f_cti_trig_in [7..0]
• h2f_cti_trig_out_ack [7..0]
• h2f_cti_trig_out [7..0]
• h2f_cti_trig_in_ack [7..0]

2.2.1.6. Enable DDR Arm Trace Bus (ATB)

Enabling the DDR Arm Trace Bus provides the ddr_atb_clock clock input and ddr_atb_reset reset input interfaces.

2.2.2. HPS-FPGA AXI Bridges

These bridges facilitate communication between the HPS and FPGA fabric using AXI protocols.

2.2.2.1. FPGA-to-HPS Slave Interface

This interface allows FPGA masters to issue transactions to the HPS. Configuration options include:

• Interface specification (AXI-4 or ACE-lite).
• Enable/Data Width (128-, 256-, or 512-bit).
• Interface address width (40 bits down to 20 bits), with the Address Span Extender component available for masters with smaller address widths.
• Interface destination (CCU, SDRAM Direct, or Inband).

When this bridge is enabled, f2h_axi_slave, f2h_axi_clock, and f2h_axi_reset are available. The hps_emif conduit is enabled when AXI or ACE-Lite bridge is selected.

2.2.2.2. HPS to FPGA AXI-4 Master Interface

This interface allows HPS masters to issue transactions to the FPGA fabric. Configuration includes:

• Enable/Data Width (32-, 64-, or 128-bit).
• Bridge address width (32 bits down to 20 bits).

This bridge accepts FPGA fabric clocks and performs clock domain crossing. Soft logic adapters can support other interface standards like Avalon-MM.

2.2.2.3. Lightweight HPS to FPGA Master Interface

This low-bandwidth control interface allows HPS masters to issue transactions to the FPGA fabric. It features a fixed 32-bit data width and configurable bridge address width (21 or 20 bits). Interfaces h2f_lw_axi_master, h2f_lw_axi_clock, and h2f_lw_axi_reset are available when enabled.

2.2.3. HPS Boot Source

The HPS SSBL Location dropdown selects the boot source for the HPS Second Stage Bootloader:

• Use the boot flash as used by the SDM
• Use HPS SD/MMC flash
• Use HPS NAND flash

Note: The HPS Boot Source tab is removed in Intel Quartus Prime Pro Edition version 19.3. Refer to the BuildingBootloader web page on RocketBoards for boot source information.

2.2.4. DMA Controller Interface

This interface allows soft IP in the FPGA to communicate with the HPS DMA controller. Up to eight interface channels can be configured. Each DMA peripheral request interface conduit (f2h_dma<n>) contains:

• f2h_dma<n>_req: Signal for burst transfer requests.
• f2h_dma<n>_single: Signal for single word transfer requests.
• f2h_dma<n>_ack: Signal indicating DMA acknowledgment.

Note: FPGA DMA interfaces 6 and 7 are multiplexed with the EMAC2 I2C DMA interface.

2.2.5. Interrupts

The Interrupts section is divided into FPGA-to-HPS and HPS-to-FPGA subsections.

2.2.5.1. FPGA-to-HPS

Enabling FPGA-to-HPS interrupts configures the HPS component to provide 64 general purpose interrupts to the MPU's generic interrupt controller (GIC). These are implemented via 32-bit interfaces:

• f2h_irq0: Interrupts 0 through 31.
• f2h_irq1: Interrupts 32 through 63.

These interrupts are asynchronous on the FPGA interface and synchronized internally to the MPU's peripheral clock.

2.2.5.2. HPS-to-FPGA

The following table lists available HPS-to-FPGA interrupt interfaces:

2.3. HPS Clocks and Resets

This section covers Input Clocks, Internal Clocks and Output Clocks, and Resets.

2.3.1. Input Clocks

The Input Clocks tab includes subsections for External Clock Source, FPGA-to-HPS Clocks Source, and Peripheral FPGA Clocks.

2.3.1.1. External Clock Source

The EOSC clock frequency field specifies the input clock frequency to the hps_osc_clk pin, which drives the main HPS PLL.

2.3.1.2. FPGA-to-HPS Clocks Source

Enabling the FPGA-to-HPS free clock option provides an alternative input (f2h_free_clk) to the main HPS PLL, driven from the FPGA fabric.

2.3.1.3. Peripheral FPGA Clocks

This subsection describes parameters for peripheral clock frequencies, such as EMAC, SD/MMC, and SPI.

2.3.2. Internal Clocks and Output Clocks

This subsection covers Main PLL Output Clocks, HPS to FPGA User Clocks, HPS Peripheral Clocks, Clock Sources, and PLL Report.

2.3.2.1. Main PLL Output Clocks – Desired Frequencies

This section controls the MPU clock frequency. The Default MPU clock frequency field shows the default maximum frequency based on the device speed grade. The Override default MPU clock frequency box allows manual entry of a slower frequency in the Custom MPU clock frequency field.

2.3.2.2. HPS to FPGA User Clocks

Enabling HPS-to-FPGA User0 or User1 clock options provides available HPS PLL outputs to the FPGA for custom logic. The clock frequency field shows the default maximum frequency, which can be manually overridden.

2.3.2.3. HPS Peripheral Clocks – Desired Frequencies

Clock frequencies provided here are reported in a Synopsys* Design Constraints File (.sdc). Changes can be made by altering the L3 source clock frequency or clock divider.

2.3.2.4. Clock Sources

Dropdowns in this section control multiplexers in the HPS clock manager to select PLL or clock sources. The FPGA to HPS Free clock is available if enabled in the Input Clocks tab.

2.3.2.5. PLL Report

This section provides calculated parameters for HPS PLLs and frequencies for main and peripheral clocks.

2.3.3. Resets

Options include:

• Enable HPS warm reset handshake signals: Enables additional reset handshake signals for soft logic to notify the HPS when a warm reset is safe. Exposes h2f_pending_rst_req_n and f2h_pending_rst_ack_n.
• Enable HPS-to-FPGA cold reset output: Exposes the h2f_coldreset reset output interface.
• Enable watchdog reset: Exposes the h2f_watchdog_rst reset output interface.
• How SDM handles HPS watchdog reset: Dropdown to direct the SDM to treat HPS watchdog reset assertions as Cold reset, Warm reset, or Trigger Remote Update.

2.4. HPS EMIF

The HPS supports one DDR4 interface. Note that EMIF conduit behavior differs between Quartus Prime Pro Edition versions 19.2 and 19.3 regarding enablement and SDRAM tab visibility.

2.5. I/O Delays

The I/O Delays tab allows adding optional delay chains to HPS dedicated I/O pins. Options include:

• Zero_chain_dly: Bypasses the delay chain.
• Chain_dly: Uses the minimum delay chain path.
• One_chain_dly to thirty_chain_dly: Uses between one and thirty delay chains.

2.6. Pin MUX and Peripherals

The Pin MUX and Peripherals tab includes sub-windows for Pin Mux GUI, Pin Mux Report, and EMAC ptp interface.

2.6.1. Pin Mux GUI

The Pin MUX GUI section has two tabs: Auto-Place IP and Advanced.

• Auto-Place IP: Lists HPS peripherals that can be enabled and routed to HPS I/Os or the FPGA. Peripherals like NAND Flash Controller, SD/MMC Controller, Ethernet Media Access Controller, USB 2.0 OTG Controller, I2C Controller, UART Controller, SPI Master, SPI Slave, CoreSight Debug and Trace, and GPIO can be enabled. Clicking Apply Selections performs automatic placement of enabled peripheral signals to HPS I/Os.
• Advanced: Contains sub-tabs for Advanced IP Placement and Advanced FPGA Placement.

2.6.1.1. Advanced IP Placement

Allows specific pin placement of each peripheral in the HPS dedicated I/O quadrant space. Changes take effect upon clicking Apply Selections.

2.6.1.2. Advanced FPGA Placement

Allows routing of specific peripherals to the FPGA if they were enabled and allocated in the Auto-Place IP tab. Options for bit-width specification are available for SD/MMC, NAND, and TRACE. Interface and PHY Options dropdowns are available for EMACs.

2.6.2. Pin Mux Report

Details the physical pins of the device mapping to each HPS I/O location.

2.6.3. EMAC ptp Interface

Enables the Precision Time Protocol (PTP) FPGA interface for each EMAC. When enabled, signals like emac<n>_ptp_pps_o, emac<n>_ptp_aux_tx_trig_i, emac<n>_ptp_tstmp_data, emac<n>_ptp_tstmp_en, and emac_ptp_ref_clock become available.

2.7. Generating and Compiling the HPS Component

The process is similar to other Platform Designer projects:

1. Generate the design with Platform Designer. This includes an .sdc file with clock timing constraints.
2. Add the generated <qsys_system_name>.qip file to the Intel Quartus Prime project. This file contains pin assignments.
3. Perform analysis and synthesis using Intel Quartus Prime.
4. Compile the design.
5. Optionally back-annotate SDRAM pin assignments to eliminate warnings in future compilations.

When using the FPGA-to-HPS slave interface in AXI-4 mode, selecting Load IP-XACT Register Details includes relevant CSR offset information.

2.8. Using the Address Span Extender Component

The FPGA-to-SoC bridge can expose entire address spaces (1GB and 4GB) to the FPGA fabric. The Address Span Extender component provides a memory-mapped window, allowing FPGA masters with smaller address spans to access the full address space. It can be used between a soft logic master and an FPGA-to-SoC bridge to reduce address bits required for accessing HPS interfaces.

The address span extender can also be used in the HPS-to-FPGA direction for slave interfaces in the FPGA, enabling paging or windowing of memory.

2.9. Configuring the HPS Component Revision History