ublox MAYA-W4 Series Host-Based Multiradio Modules
Specifications
- Product Name: MAYA-W4 series
- Features: Host-based multi-radio modules with Wi-Fi 6, Bluetooth Low Energy 5.4, and IEEE 802.15.4
- Model Variants: MAYA-W471, MAYA-W473, MAYA-W476, MAYA-W472,
- MAYA-W436, MAYA-W442, MAYA-W463, MAYA-W466, MAYA-W333
- Type Numbers: MAYA-W471-00B-00, MAYA-W473-00B-00,
- MAYA-W476-00B-00, MAYA-W472-00B-00, MAYA-W436-00B-00,
- MAYA-W442-00B-00, MAYA-W463-00B-00, MAYA-W466-00B-00,
- MAYA-W433-00B-00
System Description
Overview: The MAYA-W4 series is a host-based multiradio module that supports Wi-Fi 6, Bluetooth Low Energy 5.4, and IEEE 802.15.4 technologies.
Module Architecture: The module architecture includes components for seamless integration into various systems.
Module Integration
Supply Interface: Connect the module to a suitable power supply interface following the specified voltage requirements.
- 2.1.1 Digital I/O Interfaces Reference Voltage (VIO): Ensure the digital I/O interfaces reference voltage is within the specified range for proper functionality.
Antenna Diversity: Implement antenna diversity to enhance signal reception and transmission capabilities.
System Function Interfaces: Utilize the system function interfaces for seamless communication with external devices and systems.
FAQs
Q: What are the key features of the MAYA-W4 series?
A: The key features include support for Wi-Fi 6, Bluetooth Low Energy 5.4, and IEEE 802.15.4 technologies, making it versatile for various applications.
Q: How many model variants are available in the MAYA-W4 series?
A: There are nine model variants available in the MAYA-W4 series, each offering specific functionalities to cater to different requirements.
Abstract
Targeted towards hardware and software application engineers, this document describes how to integrate MAYA-W4 modules in application products and explains the hardware design-in, software, component handling, regulatory compliance, and testing of the modules. It also lists the external antennas approved for use with the module. Designed for a wide range of industrial applications, this range of ultra-compact, cost-efficient, host-based, multiradio modules includes product variants that are supplied with or without internal antenna. Integrated with a MAC/Baseband processor and RF front end components, MAYA-W4 modules connect to a host processor through various interfaces, including SDIO or USB for Wi-Fi, High-Speed UART or USB for Bluetooth, and SPI for 802.15.4.
Document status description
Draft Objective specification Advance information Early production information Production information
For functional testing. Revised and supplementary data will be published later. Target values. Revised and supplementary data will be published later. Data based on early testing. Revised and supplementary data will be published later. Data from product verification. Revised and supplementary data may be published later. Document contains the final product specification.
This document applies to the following products:
Product name MAYA-W471 MAYA-W473 MAYA-W476 MAYA-W472 MAYA-W436 MAYA-W442 MAYA-W463 MAYA-W466 MAYA-W333
Type number MAYA-W471-00B-00 MAYA-W473-00B-00 MAYA-W476-00B-00 MAYA-W472-00B-00 MAYA-W436-00B-00 MAYA-W442-00B-00 MAYA-W463-00B-00 MAYA-W466-00B-00 MAYA-W433-00B-00
For information about the related hardware, software, and status of listed product types, see also
the respective data sheets [1][2][3][4].
u-blox or third parties may hold intellectual property rights in the products, names, logos, and designs included in this document. Copying, reproduction, or modification of this document or any part thereof is only permitted with the express written permission of u-blox. Disclosure to third parties is permitted for clearly public documents only. The information contained herein is provided “as is” and u-blox assumes no liability for its use. No warranty, either express or implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent documents and statuses, visit www.u-blox.com.
System description
Overview
Comprising ultra-compact, multiradio modules with Wi-Fi 6, Bluetooth Low Energy 5.4, and IEEE 802.15.4 connectivity, the MAYA-W4 series supports IEEE 802.11a/b/g/n/ac/ax standards and delivers PHY data rates up to 115 Mbit/s with 1×1 dual band 2.4 / 5 GHz Wi-Fi with 20 MHz channel bandwidth. The modules can work as simple access points, stations, in P2P connections, or in a combination of these modes.
MAYA-W4 series supports Bluetooth Low Energy 5.4, including 2 Mbit/s high-speed data rate, long range, extended advertising, and isochronous channels for LE audio. MAYA-W4 series variants include an 802.15.4 radio supporting the Thread mesh network protocol for Matter applications running over Wi-Fi and Thread.
MAYA-W4 supports an optional LTE filter and is available with or without an antenna, including variants with U.FL connectors, antenna pins, or an on-board antenna. MAYA-W4 modules come with RF calibration and MAC addresses available in the integrated OTP memory.
The modules are developed for reliable, high-demanding, industrial devices and applications that demand high performance.
Radio type approvals for Europe (RED), Great Britain (UKCA), the United States (FCC), Canada (ISED) and Japan (Giteki) are planned, and other country certifications (China, Australia, South Korea, Taiwan, Brazil) can be provided on request.
Module architecture
MAYA-W4 includes the NXP IW610x System-On-Chip (SoC) with fully integrated power management circuitry that provides power to the internal voltage domains of the SoC, integrated MAC/baseband processor, transceivers for 2.4 GHz and 5 GHz Wi-Fi operation, Bluetooth Low Energy connectivity, and 802.15.4 Thread support.
MAYA-W4 also includes discrete RF components for configuring the antenna interface enabling the antenna path connections as shown in the block diagrams in [1].
For host CPU connectivity, MAYA-W4 supports a Secure Digital Input Output (SDIO) 3.0 interface for Wi-Fi and a Universal Asynchronous Receiver Transmitter (UART) interface for Bluetooth Low Energy. Wi-Fi and Bluetooth Low Energy communication are also supported through a USB 2.0 device interface. A Serial Peripheral Interface (SPI) is available for 802.15.4 Thread operation. The host interface configuration is selected through Configuration pins.
All module variants support:
· Integrated discrete filters in the 2.4 GHz band and 5 GHz band · Optional LTE filter for improved coexistence with LTE bands 7, 38, 40, 41 · External coexistence interfaces to enable coexistence with other co-located wireless devices
The MAYA-W4 series includes variants with single or dual-band Wi-Fi 6, Bluetooth Low Energy 5.4, and optional 802.15.4 radio. It also offers multiple antenna solutions:
· Single embedded antenna, antenna pin, or U.FL connector for shared 2.4 GHz Wi-Fi and Bluetooth Low Energy/802.15.4 operation
· Dual antenna pins or U.FL connectors for simultaneous Wi-Fi and Bluetooth Low Energy/ 802.15.4 operation
See the MAYA-W4 data sheet [1] for the available MAYA-W4 module variants.
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2 Module integration
MAYA-W4 shall be integrated into the application product together with a Host CPU system. Figure 1 shows a typical integration.
Figure 1. MAYA-W4 integration in host system
· The SDIO or USB provide the main interface for Wi-Fi data and downloading firmware. The UART or USB interface is used for Bluetooth data. SPI is used for 802.15.4.
· The preferred data and communication interface between Host CPU and MAYA-W4 is set according to the instructions for Configuration pins.
· Host interface signals for power down, reset, host and module wake-up are available to control MAYA-W4 from host CPU.
· The module is power supplied through the 3V3, 1V8, VIO, and VIO_SD domain pins. To match the host CPU pad voltage, VIO can be set to either 1.8 V or 3.3 V. VIO_SD can be set to 1.8 V or 3.3 V to match the SDIO interface voltage of the Host CPU.
· MAYA-W4 antenna configurations, including antenna pin(s), U.FL connector(s), or internal antenna, are described in [1].
· For correct operation, it is important to correctly configure MAYA-W4 with the settings and startup sequences described in the MAYA-W4 data sheet [1]. This configuration requires that PDn is asserted and that the timing of power sources is enabled. This configuration places requirements on enabling the timing of power sources and the assertion of PDn.
· The MAYA-W4 product summary [24] describes the features of the different MAYA-W4 versions. Use this document to identify the MAYA module that is best suited for your application product.
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Power supply interface
MAYA-W4 series power supply pins 3V3, 1V8, VIO, and VIO_SD pins must be sourced by a regulated DC power supply, such as an LDO or SMPS. The appropriate type for your design depends on the main power source of the application.
The DC power supply can be taken from any of the following sources:
· Switched Mode Power Supply (SMPS) · Low Drop Out (LDO) regulator
When choosing between an SMPS or LDO to supply the modules, it is advisable to consider the acceptable power and thermal dissipation of the application product. See also Module supply design.
The power supply design must strictly adhere to the defined power-up sequence. Ensuring compliance with the recommended power-up sequence is critical when implementing power management functions.
The current consumed through the supply pins on MAYA-W4 series modules can vary by several orders of magnitude depending on the operation mode and state. The current consumption can change from high consumption, experienced during Wi-Fi transmission at maximum RF power level in connected-mode, to low current consumption during the low power idle-mode when power saving is enabled. Regardless of the chosen DC power supply, it is crucial that it can satisfy the high peak current consumed by the module. When designing the supply circuitry for the module, a contingency of at least 20% over the stated peak current is recommended. See also Module supply design.
Domain
Allowable ripple (peak to peak) over DC supply
3V3 1V8 VIO_SD VIO
10-100 kHz 65 mVpk-pk 65 mV 65 mVpk-pk 65 mVpk-pk
100 kHz-1 MHz 25 mVpk-pk 25 mVpk-pk 25 mVpk-pk 25 mVpk-pk
Table 1: Summary of voltage supply requirements
>1 MHz 10 mVpk-pk 10 mVpk-pk 10 mVpk-pk 10 mVpk-pk
Current consumption, peak
400 mA 1000 mA 2 mA 2 mA
Figure 2: Proposed implementation of MAYA-W4 power supply circuitry
2.1.1 Digital I/O interfaces reference voltage (VIO)
The dedicated VIO pin enables integration of MAYA-W4 in either 1.8 V or 3.3 V applications without the need for level converters according to the voltage level selected. For information about the supply voltage requirements, see also the MAYA-W4 series data sheet [1].
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2.2 Antenna interfaces
Different antenna solutions can be used to integrate MAYA-W4 modules into application designs.
2.2.1 Antenna solutions
Figure 3 shows the available antenna options.
Figure 3: Antenna options
· External antenna: An external antenna of choice connected through a coaxial cable to a U.FL connector placed on the module or Reverse Polarity SMA connector placed on the application PCB and connected to the module antenna pin.
· Integrated antenna: A permanent antenna included in the PCB application design. Ideally an SMD antenna mounted on the application PCB, or a Flexible PCB antenna attached to the housing of the application product.
· Internal antenna: A Niche antenna, licensed from Abracon and integrated onto the module’s PCB, designed for a minimum BOM.
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2.2.2 RF pins and connectors
The MAYA-W4 series supports multiple single- and dual-antenna configurations:
· Internal PCB trace antenna or antenna pin configured externally by a 0 jumper · Two external antennas connected through antenna pins · Two external antennas connected through on-module U.FL connectors
To prevent mutual interference and improve coexistence performance with LTE bands, MAYA-W4 supports an optionally integrated, high-performance 2.4 GHz SAW LTE band pass filter.
Table 2 shows the available antenna interfaces on MAYA-W4 series modules.
Product variant MAYA-W4x0
MAYA-W4x1
MAYA-W4x3
Antenna interface J2 J1 RF_ANT0 RF_ANT1 RF_ANT1
MAYA-W4x6
RF_ANT1
ANT_FEED
Description2
U.FL connector for external 2.4/5 GHz Wi-Fi antenna
U.FL connector for external Bluetooth Low Energy/802.15.4 antenna
Antenna pin for external 2.4/5 GHz Wi-Fi antenna
Antenna pin for external Bluetooth Low Energy/802.15.4 antenna
Antenna pin for external 2.4/5 GHz Wi-Fi, Bluetooth Low Energy, and 802.15.4 antenna. Bluetooth Low Energy, 802.15.4, and 2.4 GHz Wi-Fi are time-shared.
Antenna pin for external 2.4/5 GHz Wi-Fi, Bluetooth Low Energy, and 802.15.4 antenna. Bluetooth Low Energy, 802.15.4, and 2.4 GHz Wi-Fi are time-shared.
External antenna feed pin from RF_ANT1 for Internal PCB trace antenna.
Table 2: MAYA-W4 antenna configurations
For proper implementation of antennas in the application product, follow the RF interface options.
See also the Antenna integration application note [18].
2.2.3 Approved antenna designs
MAYA-W4 modules come with a pre-certified antenna design that can save cost and time during the certification process. To leverage this benefit, customers are required to implement an antenna layout that is fully compliant with the u-blox reference design outlined in the MAYA-W4 antenna reference design application note [24]. Reference design source files are available on request3 from u-blox.
For Bluetooth and Wi-Fi operation, MAYA-W4 modules have been tested and approved for use with the antennas featured in the list of Approved antennas.
To implement a design compliant with the u-blox FCC certification Grant follow the instructions in
the MAYA-W4 antenna reference design application note [24].
2.2.4 Integrated antennas
MAYA-W4 module variants with RF pins allow an SMD antenna to be mounted on the application board, which can then be connected with a transmission line. The module variants suitable for use with an integrated antenna are described in Antenna solutions.
For proper implementation of the antennas in the application product, follow the RF interface options.
2 Support for 5 GHz Wi-Fi and 802.15.4 depends on the specific product variant. 3 Reference designs are only available after certification
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2.2.5 External antennas
External antennas can be used with MAYA-W4 module variants equipped with U.FL connectors. The antennas connect to the module through coaxial cables. The module variants suitable for use with an external antenna are described in Antenna solutions.
External antennas are particularly suited for application products housed in metal casings that demand that the antennas are placed externally.
For proper implementation of the antennas in the application product, follow the RF interface options.
To avoid invalidating the compliance and pre-certification of u-blox modules with the various
regulatory bodies, use only external antennas included the list of Approved antennas. u-blox modules may also be integrated with other antennas. In which case, OEM installers must certify their own designs with the respective regulatory agencies.
2.2.6 Internal antennas
MAYA-W4x6 modules include an internal Niche antenna that is printed on the PCB and connected to pin L9 (ANT_FEED). To use the internal antenna, pin L9 must be connected to the RF signal pin K9 (RF_ANT1). The antenna utilizes antenna technology from Abracon. The variants equipped with an internal antenna are described in Antenna solutions.
For proper antenna performance observe the following design considerations. When using these modules with an external antenna this shall be connected to pin K9.
· To enable good antenna radiation performance, it is important to place the module on the edge of the main PCB with the antenna facing outwards.
· A ground plane extending at least 10 mm on both sides of the module is recommended. · Include a non-disruptive GND plane underneath the module with a clearance, cut out, underneath
the antenna, as shown in Figure 4. · Observe the antenna clearance shall be implemented on all layers. · To avoid degradation of the antenna characteristics, do not place physically tall or large
components closer than 10 mm to the module antenna. · To avoid any adverse impact on antenna performance, include a 5 mm clearance between the
antenna and the casing. Polycarbonate (PC) and Acrylonitrile butadiene styrene (ABS) materials have less impact on antenna performance than other types of thermoplastic. · Include plenty of stitching vias from the module ground pins to the GND plane layer. Ensure that the impedance between the module pins and ground reference is minimal. · Consider the end products use case and assembly to make sure that the antenna is not obstructed by any external item.
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Figure 4 shows the PCB artwork on main PCB top layer for MAYA-W4x6 modules. It also shows the placement and GND clearance of the internal PCB trace antenna. The antenna clearance is only required for these module variants.
Figure 4: PCB artwork on main PCB top layer for MAYA-W466 and MAYA-W476
2.3 Antenna diversity
For module variants with antenna pins, you can implement Wi-Fi antenna diversity by adding an external antenna switch. The antenna diversity algorithm controls the switch using the RF control pin RF_CNTL3.
To configure antenna diversity:
· On MAYA-W4 modules with dual antenna pins, connect the external antenna diversity switch to the Wi-Fi RF_ANT0 pin.
· On MAYA-W4 modules with a single antenna pin, connect the external diversity antenna switch to the shared RF_ANT1 pin. For these modules, both Wi-Fi and Bluetooth are included in the diversity switching.
· Modules with an internal antenna can use it as a diversity antenna.
Antenna switching diversity is only supported in Wi-Fi station mode. The antenna diversity algorithm is triggered periodically by evaluating the link quality. If the link quality is unchanged the algorithm keeps the current antenna until the next evaluation. This mainly addresses multipath fading when the conditions change slowly and make fixed installations less critical for optimum placement.
For optimal efficiency, diversity antennas should be separated by at least ¼ wavelength, ideally ½ wavelength, to minimize mutual coupling and interference. To further reduce antenna correlation, implementing orthogonal polarization where antennas are oriented with perpendicular polarization axes is highly beneficial. This configuration improves signal independence, enhances performance in multipath environments, and maximizes diversity gains.
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MAYA-W4 series – System integration manual The Infineon BGS12WN6 is an example of a single-pin, external antenna switch with an operating frequency of up to 9 GHz. A typical circuit implementation for antenna diversity is shown in Figure 5. For RF diversity, connect the switch to the Wi-Fi antenna pin, RF_ANT0 or RF_ANT1.
Figure 5: RF diversity switch implementation.
For information on how to configure and enable/disable the software antenna diversity feature, see Configuring antenna diversity.
2.4 System function interfaces
2.4.1 Power-up sequence
PDn must be held low during start up and released when the power is stable, or later when the module is powered on. Other than this, there are no additional requirements for the power-up sequence. The external power rails can be applied in any order provided that PDn remains low. Figure 6 shows the power-up sequence for MAYA-W4, where all power rails can be independently applied before PDn is set high.
Figure 6: Power sequence of MAYA-W4 module
PDn is powered by the 3V3 voltage domain and is connected through a 51 k pull-up resistor to 3V3 inside the module.
Optionally, the PDn pin can be left unconnected so that it follows 3V3 through the pull-up resistor. In which case, the power down mode is not accessible and a further full-power cycle must be made to reset the module.
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2.4.2 Power-down / Reset
The module enters power-down mode when PDn is asserted (low) while all power supplies to the module are enabled. After PDn is deasserted (high), the module is reset and takes approximately 20 ms to get ready for SDIO enumeration.
MAYA-W4 series modules are reset to a default operating state by any of the following events:
· Power on: Module is powered on and internal voltages are good. · PDn assert: The device is reset when the PDn input pin is < 0.2 V (VIL) and transitions from low to
high. For correct reset, PDn must be asserted for a minimum of 1 µs.
A firmware download to the module is required after each reset. For information about
downloading the firmware, see also Software.
Optional independent software reset of the WLAN and Bluetooth subsystems is possible
through the IND_RST_WL and IND_RST_NB pins, respectively. The pins can be left open if they are not needed.
2.4.3 Power-off sequence
MAYA-W4 modules enter power-down mode when PDn is asserted. After assertion, the power on the 3V3, 1V8, VIO, and VIO_SD supplies can be removed. The module then enters power-off mode.
2.4.4 Wake-up signals
MAYA-W4 series modules provide wake-up input and output signals that handle the low-power modes for both Wi-Fi and Bluetooth. See also Power states.
The wake-up signals are used to exit MAYA-W4 or host CPU from sleep modes. These signals are optional. Wake-up signals are powered by the VIO voltage domain. WL_WAKE_IN and NB_WAKE_IN are optional, out-of-band, wake-up pins that are used to wake up the radios from sleep mode.
Table 3 describes the various wake-up, input and output signals.
Pin name WL_WAKE_OUT WL_WAKE_IN NB_WAKE_OUT NB_WAKE_IN SPI_INT SD_INT
I/O type O I O I O O
Description Wi-Fi radio wake-up output signal Wi-Fi radio wake-up input signal Bluetooth LE/802.15.4 radio wake-up output signal Bluetooth LE/802.15.4 radio wake-up input signal SPI interrupt output signal Optional SDIO interrupt output signal
Table 3: Wake-up signal definitions
GPIO pin muxing GPIO[4] GPIO[16] GPIO[5] GPIO[17] GPIO[1]
2.4.5 Configuration pins
MAYA-W4 series modules have configuration pins to set specific interface configuration following a reset. The function of these configuration pins changes immediately (~1 ms) to their initial function after reset, as shown in Table 4.
Configuration pins CON[2:0] are used to set the firmware boot options that subsequently select the interfaces for the Wi-Fi, Bluetooth, and 802.15.4 traffic. Strap CON[2:0] to GND through a 51 k pulldown resistor to set these configuration bits to “0”, as described in Table 4. No external circuitry is required to set CON[3:5] configuration bits to “1”.
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During boot-up, configuration pins CON[3,5] must be set according to the settings described in Table 4. No external circuitry is required to set the configuration, which means that these pins can be left unconnected (NC). If these pins are connected, make sure that signals CON[3,5] are not pulled low by any external circuitry during boot-up. After boot, CON[3,5] revert to their main function.
Configuration bits CON[3] CON[5]
Pin name SPI_INT/CON[3] RF_CNTL0
Pin number D2 H3
Configuration settings Reserved set to 1 Reserved set to 1
CON[2:0]
Firmware boot options CON[2:0]
Table 4: Configuration pins
CON[2]: G4 CON[1]: E3 CON[0]: D3
Strap value 011 (default) 101 Others
Wi-Fi SDIO USB Reserved
Bluetooth 802.15.4
UART
SPI
USB
SPI
Reserved Reserved
2.4.6 Power states
MAYA-W4 series modules have several operation states. The power states and general guidelines for Wi-Fi and Bluetooth operations are defined in Table 5.
General status Power down
Power state Power-off
Power-down
Normal operation Active Deep sleep
Description
3V3, 1V8, VIO, and VIO_SD supplies that are not present or are below the operating range. The module is switched off.
Asserting PDn while 3V3, 1V8, VIO, and VIO_SD supplies are present powers down the module. This represents the lowest leakage mode of operation with active voltage rails. Register and memory states are not maintained in power-down mode. The module is automatically reset after exiting power-down mode, which means that the firmware must be downloaded again. If firmware is not downloaded, the device must be kept in its power-down state to reduce the leakage.
Enables TX/RX data connection with the system running at the specified power consumption.
Low-power state used in the sleep state of many power-save modes. Memory is placed in low-power retention mode.
Table 5: Description of module power states
2.5 Host interfaces
MAYA-W4 series modules support SDIO 3.0, USB 2.0, high-speed UART, and SPI host interfaces. Commands and data for Wi-Fi traffic are transferred through the SDIO or USB interface. Bluetooth uses the high-speed UART or USB interface, and the SPI interface is used for the 802.15.4 radio. Interfaces are selected by setting the appropriate boot option. For information about the configuration options for the host interface, see also Configuration pins.
2.5.1 SDIO 3.0 interface
MAYA-W4 series modules include an industry-standard SDIO 3.0 device interface with a clock range of up to 208 MHz. The host controller uses the SDIO bus protocol to access the Wi-Fi function. The interface supports 4-bit SDIO transfer mode with data rates up to 104 MB/s in SDR104 mode. The modules also support the Default Speed (DS) and High-Speed (HS) modes.
The SDIO interface voltage is set by VIO_SD to either 1.8 V or 3.3 V.
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Table 6 summarizes the supported bus speed modes.
Bus speed mode SDR104 SDR50 DDR50 SDR25 SDR12 HS: High-Speed DS: Default Speed
Max. bus speed [MB/s] 104 50 50 25 12.5 25 12.5
Max. clock frequency [MHz] 208 100 50 50 25 50 25
VIO_SD / Signal voltage [V] 1.8 1.8 1.8 1.8 1.8 3.3 3.3
Table 6: SDIO bus speeds
MAYA includes internal 100 k (typical value) pull-up resistors on the SDIO signals. Nevertheless, it is advisable to connect pull-up resistors to these lines. See also Data communication interfaces. Small value in-series termination resistors might also be applied to mitigate signal integrity and EMI issues.
Table 7 describes the function of each of the SDIO signals.
Name
I/O
SD_CLK
I
SD_CMD
I/O
SD_DAT[3:0]
I/O
SD_INT
O
Description SDIO clock input SDIO command line SDIO data line bits [3:0] SDIO interrupt output (optional)
Remarks
External PU required External PU required Multiplexed with GPIO[1]
Table 7: SDIO signal definitions
SDIO interface pins are powered by the VIO_SD voltage domain.
2.5.2 USB 2.0 interface
MAYA-W4 includes a Hi-Speed USB 2.0 interface with a transfer rate of 480 Mb/s that can be used for Wi-Fi and Bluetooth Low Energy. The interface is implemented as a controlled impedance bus, utilizing a differential data pair (D+ and D-) to mitigate noise, reduce crosstalk, and maintain signal integrity. Figure 7 shows the key parameters for calculating track impedance, where:
· Width (W) shows the width of the copper layer on the top layer · Distance (S) shows the distance between the top copper layer and the two adjacent GND planes. · Dielectric substrate thickness (H) shows the distance between the GND reference on the bottom
plane and the copper layer on the top layer. · Thickness of the copper layer (T) can also be represented by “Base Copper Weight”, which is
commonly used as the parameter for PCB stack-up.
· Dielectric constant (r) defines the ratio between the electric permeability of the material against
the electric permeability of free space.
Figure 7: USB differential pair showing key parameters for controlled impedance
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To and avoid EMI issues and ensure the integrity of the bus signals, the USB data lines must follow the recommendations described in Table 8.
Signal group
Parameter
Min.
Typ.
Max.
Unit
USB differential data
Single Ended impedance, Differential impedance, Common mode impedance, Impedance control, , , Shunt capacitance to GND
45 90 30
0 – 10% 0
Bus skew length mismatch between differential
0
pair
Isolation to other signals
4 w
0 + 10% 5 155
pF mm
Table 8: USB bus requirements
USB data signals routed on the host board can influence RF performance. Shunt capacitors or an
ESD protection filter connected to GND may be needed to reduce in-band noise from USB harmonics.
If the USB data link is routed on a connector, consider ESD protection and use specifically designed TVS diodes and common-mode chokes to reduce electromagnetic interference (EMI), for the USB lines. To avoid signal degradation select common-mode chokes with suitable inductance and current rating.
Implement a load switch controlled by PDn on USB_AVDD33 to reduce leakage current during power down mode.
2.5.3 High-speed UART interface
MAYA-W4 series modules support a high-speed Universal Asynchronous Receiver/Transmitter (UART) interface with baud rates up to 3 Mbps. The default baud rate after reset is 115.2 Kbps. The UART interface operation includes: · Bluetooth firmware upload to the module · Bluetooth data (HCI transport) High-Speed UART signals are powered by the VIO voltage domain. Table 9 describes the function of each of the UART signals
Name UART_TX UART_RX UART_RTS UART_CTS
I/O Description
Name
O
UART serial output signal, connect to Host RX
GPIO[15]
I
UART serial input signal, connect to Host TX
GPIO[14]
O
UART request-to-send output signal (active low), connect to Host CTS GPIO[13]
I
UART clear-to-send input signal (active low), connect to Host RTS
GPIO[12]
Table 9: UART signal descriptions
5 Total mismatch includes skew introduced by cable and host side routing, keep it at minimum if USB bus is routed on a connector.
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2.5.4 SPI interface
MAYA-W4 variants with 802.15.4 radio support an SPI host interface with a maximum clock speed of 10 MHz. The pins are shared with the external PTA coexistence interface.
Table 10 describes the module pins on the SPI interface.
Pin name SPI_FRM SPI_CLK SPI_RX SPI_TX SPI_INT
I/O type I I I O O
Description SPI frame input signal (active low chip select) SPI clock input signal SPI receive input signal SPI transmit output signal SPI Interrupt output signal
Table 10: 802.15.4 SPI interface description
GPIO pin multiplexing GPIO[8] GPIO[9] GPIO[7] GPIO[6] –
2.6 External coexistence interface
For optimal performance when sharing the wireless medium, external coexistence interfaces enable signaling between the internal radios and external co-located wireless devices. External radios can be connected to the 5-wire packet traffic arbitration interface (PTA) or the 2-wire wireless coexistence interface 2 (WCI-2). The WCI-2 message, and the message type, comply with Bluetooth special interest group (SIG) core specification volume 7, part C.
Table 13 describes the function of each of the external coexistence signals.
Pin name
I/O type
Description
GPIO pin multiplexing
EXT_STATE
I
EXT_GNT
O
EXT_FREQ
I
EXT_PRI
I
EXT_REQ
I
WCI-2_SIN
I
WCI-2_SOUT O
External radio state input signal (optional) External radio traffic direction (Tx/Rx): · 1: Tx · 0: Rx
GPIO[22]
External radio grant output signal (mandatory)
GPIO[20]
External radio frequency input signal (optional) Frequency overlap between external radio and Wi-Fi: · 1: overlap · 0: non-overlap This signal is useful when the external radio is a frequency hopping device.
GPIO[18]
External radio input priority signal (optional)
GPIO[21]
Priority of the request from the external radio. Can support
1 bit priority (sample once) and 2-bit priority (sample
twice). Can also have Tx/Rx info following the priority info if
EXT_STATE is not used.
Request from the external radio (mandatory)
GPIO[19]
WCI-2 serial interface input
GPIO[22]
WCI-2 serial interface output
GPIO[18]
Table 11: External coexistence interface description
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2.7
2.7 General purpose I/O
MAYA-W4 provides several GPIO pins, which default to a high-impedance tristate on power-up and reset. Some GPIO pins are multi-functional and are configured according to their intended purpose after initialization and firmware download. For detailed pin assignment information, see also the MAYA-W4 series data sheet [1]. For information describing the function of available GPIO signals in each supported interface, see also UART, SPI, External coexistence interface and JTAG. All other GPIO signals are described in the Pin assignment section of the MAYA-W4 series data sheet [1].
2.8 Other remarks
2.8.1 Unused pins
MAYA-W4 series modules have unconnected (NC) pins that are reserved for future use. These pins can be left unconnected on the application board.
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3 Design-in
Follow the design guidelines in this chapter to optimize the integration of MAYA-W4 series modules in the final application board.
3.1 Overview
Although all application circuits must be properly designed, the following aspects of the application design require special attention:
· Module antenna integration: RF_ANT o Antennas and RF circuits affect RF performance and certification compliance. It is important to follow the design instructions given here to achieve the performance specified in the MAYA-W4 data sheet. To maintain compliance and subsequent certification of the application design, it is important to observe the applicable parts of antenna schematic and layout described in Antenna design.
· Module power supply: Power and GND o Power supply circuits might affect the products operating stability and RF performance. It is important to select a suitable device capable to source the adequate current. It is also important to implement adequate power and ground planes in PCB stack-up and to implement bypass capacitors for these supplies. See also Supply interfaces.
· High-speed interfaces, such as PCIe, SDIO, USB, high-speed UART, SPI, and PCM o High-speed interfaces are a potential source of noise that can affect the regulatory compliance of standards for radiated emissions. It is important to follow the schematic and layout design recommendations described in SDIO 3.0 interface and the General high-speed layout guidelines.
· System functions: Power Down, Reset, and Configuration o Careful utilization of these pins in the application design is necessary to ensure correct operation of the product. Specifically, check that the state and voltage level of these pins are correctly defined during module boot and operation. It is important to follow the pin design described in the General high-speed layout guidelines.
· Other pins: specific signals o Careful utilization of these pins is necessary to ensure that the module operates correctly. It is important to follow the schematic and design layout recommendations.
· NC pins must not be connected.
3.2 RF interface
MAYA-W4 modules provide several RF-interface options for connecting external antennas, as described in RF pins and connectors.
According to FCC regulations, the transmission line from the module antenna pin to the physical
antenna (or antenna connector on the host PCB) is considered part of the approved antenna design. Therefore, module integrators must use exactly the antenna reference design used in the module FCC type approval or certify their own design.
For instructions on how to design circuits that comply with these requirements, see also Antenna interfaces.
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3.2.1 Antenna design
To optimize the radiated performance of the final product, the selection and placement of both the module and antenna must be chosen with due regard to the mechanical structure and electrical design of the product. To avoid costly redesigns and their potential impact on the mechanical design, it is important to determine the positioning of these components early in the product design phase.
The compliance and subsequent certification of the RF design depends heavily on the radiating performance of the antennas. To ensure that the RF certification of MAYA-W4 modules is extended through to the application design, carefully follow these guidelines:
· External antennas, including, linear monopole classes: o Place the module and antenna in any convenient area on the board. External antennas do not impose any restriction on where the module is placed on the PCB. o Select antennas with an optimal radiating performance in the operating bands. The radiation performance depends mainly on the antennas. o Choose RF cables that offer minimum insertion loss. Unnecessary insertion loss is introduced by low quality or long cables. Large insertion losses reduce radiation performance. o Use a high-quality 50 coaxial connector for proper PCB-to-RF cable transition.
· Integrated antennas, such as patch-like antennas: o Internal integrated antennas impose some physical restrictions on the PCB design. The orientation of the ground plane relative to the antenna element must also be considered: – Integrated antennas excite RF currents on its counterpoise, typically the PCB ground plane of the device that becomes part of the antenna; its dimension defines the minimum frequency that can be radiated. Therefore, the ground plane can be reduced to a minimum size that should be similar to the quarter of the wavelength of the minimum frequency that has to be radiated,. – Find a numerical example to estimate the physical restrictions on a PCB, where: Frequency = 2.4 GHz Wavelength = 12.5 cm Quarter wavelength = 3.5 cm in free space or 1.5 cm on a FR4 substrate PCB.
· Choose antennas with optimal radiating performance in the operating bands. Radiation performance depends on the complete product and antenna system design, including the mechanical design and usage of the product. Table 12 summarizes the requirements for the antenna RF interface.
· Make the RF isolation between the system antennas as high as possible, and the correlation between the 3D radiation patterns of the two antennas as low as possible. In general, RF separation of at least a quarter wavelength between the two antennas is required to achieve a minimum isolation and low pattern correlation. If possible, increase the separation to maximize the performance and fulfill the requirements in Table 13.
Item Impedance Frequency range
Return loss
Requirements
Remarks
50 nominal characteristic impedance
The impedance of the antenna RF connection must match the 50 impedance of Antenna pins.
2400 2500 MHz 5150 5885 MHz
For 802.11b/g/n/ax and Bluetooth/802.15.4. For 802.11a/n/ac/ax.
S11 < -10 dB (VSWR < 2:1) recommended S11 < -6 dB (VSWR < 3:1) acceptable
Defined by the interrelated S11 (Input Reflection Coefficient) parameter and Voltage Standing Wave Ratio (VSWR), the Return loss describes how well the primary antenna RF connection matches the 50 characteristic impedance of the ANT pin.
To maximize the amount of the power transferred to the antenna, the impedance of the antenna termination must match (as much as possible) the 50 nominal impedance of the ANT pin over the entire operating frequency range .
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Item Efficiency
Maximum gain
Requirements > -1.5 dB ( > 70% ) recommended > -3.0 dB ( > 50% ) acceptable
TBD
Remarks
Radiation efficiency is the ratio of the radiated power to the power fed to the antenna input: the efficiency is a measure of how well an antenna receives or transmits.
Although higher gain antennas can be used, these must be evaluated and/or certified. To comply with the radiation exposure limits of regulatory agencies, the maximum antenna gain must not exceed the value specified in the list of Approved antennas. See also Regulatory compliance.
Table 12: Summary of antenna interface requirements
Table 13 specifies additional requirements for implementing a dual antenna design.
Item
Isolation (in-band)
Requirements S21 > 30 dB recommended
Isolation (out-of-band)
S21 > 35 dB recommended S21 > 30 dB acceptable
Envelope Correlation ECC < 0.1 recommended
Coefficient (ECC)
ECC < 0.5 acceptable
Remarks
The in-band isolation, defined by the S21 (Forward Transmission Coefficient) parameter measures the power transmission between two antennas. Lower isolation might be acceptable depending on usecase scenario and performance requirements.
Out-of-band isolation is evaluated in the band of the aggressor. This ensures that the transmitting signal from the other radio is sufficiently attenuated by the receiving antenna. It also avoids any saturation and intermodulation effect on the receiver port.
The ECC (Envelope Correlation Coefficient) parameter correlates the far field parameters between antennas in the same system. A low ECC parameter is fundamental in improving the performance of MIMO-based systems.
Table 13: Summary of Wi-Fi/Bluetooth coexistence requirements
When operating dual antennas in the same 2.4 GHz band, sufficient isolation is critical for
attaining an optimal throughput performance in Wi-Fi/Bluetooth/802.15.4 coexistence mode.
Select antennas that provide:
· Optimal return loss (or VSWR) over all the operating frequencies. · Optimal efficiency figure over all the operating frequencies. · An appropriate gain that does not exceed the regulatory limits specified in some regulatory
country authorities like the FCC in the United States.
3.2.1.1 Integrated antenna design
If integrated antennas are used, the transmission line is terminated by the antennas themselves or by the antenna together with the connected coaxial cable and U.FL plug.
Consider the following guidelines when designing the antenna:
· The antenna design process should commence at the same time as the mechanical design of the product. PCB mock-ups are useful in estimating overall efficiency and radiation path of the intended design during early development stages.
· Integrated antennas are not suitable for placement inside a metal casing or if plastics including metal flakes is used for the product housing.
· Use antennas designed by an antenna manufacturer that provide the best possible return loss (or VSWR).
· Provide a ground plane large enough according to the related integrated antenna requirements. The ground plane of the application PCB may be reduced to a minimum size that must be similar to one quarter of wavelength of the minimum frequency that has to be radiated. The overall antenna efficiency may benefit from larger ground planes.
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· Proper placement of the antenna and its surroundings is also critical for antenna performance. Avoid placing the antenna close to conductive or RF-absorbing parts, such as metal objects or ferrite sheets, as these may absorb part of the radiated power, shift the resonant antenna frequency of the antenna, or otherwise affect the antenna radiation pattern.
· Ensure that installation and deployment of the antenna system, including PCB layout and matching circuitry, is done correctly. In this regard, it is recommended that you strictly follow the specific guidelines provided by the antenna manufacturer.
· Antennas may require tuning/matching to reach the target performance. It is recommended to plan measurement and validation activities with the antenna manufacturer before releasing the end-product to manufacturing.
· The receiver section may be affected by noise sources like hi-speed digital busses. Avoid placing the antenna close to busses as DDR. Otherwise, consider taking specific countermeasures, like metal shields or ferrite sheets, to reduce the interference.
· Be aware of interaction between co-located RF systems, like nearby LTE bands and other possible radio systems. Transmitted power may interact or disturb the performance of MAYA-W4 modules where specific LTE filter is not present.
3.2.1.2 RF transmission line design
RF transmission lines, such as those that connect from RF_ANT pins to their related antenna connectors or antenna, must be designed with a characteristic impedance of 50 .
Figure 8 shows the design options for implementing a transmission line, namely: · Microstrip track separated with dielectric material and coupled to a single ground plane. · Coplanar microstrip track separated with dielectric material and coupled to both the ground
plane and side conductor. This is the most common transmission line implementation. · Stripline track separated by dielectric material and sandwiched between two parallel ground
planes.
The parameters shown in the cross-sectional area of each trace design include:
· Width (W) shows the width of the copper layer on the top layer · Distance (S) shows the distance between the top copper layer and the two adjacent GND planes. · Dielectric substrate thickness (H) shows the distance between the GND reference on the bottom
plane and the copper layer on the top layer. · Thickness of the copper layer (T) can also be represented by “Base Copper Weight”, which is
commonly used as the parameter for PCB stack-up.
· Dielectric constant (r) defines the ratio between the electric permeability of the material against
the electric permeability of free space.
The width of a 50 microstrip depends on mainly “r” and “H”, which must be calculated for each
PCB layer stack-up.
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Figure 8: Transmission line trace design
Follow these recommendations to design a 50 transmission line correctly:
· Designers must provide enough clearance from surrounding traces and ground in the same layer. In general, the trace to ground clearance should be at least twice that of the trace width. The transmission line should also be “guarded” by the ground plane area on each side.
· In the first iteration, calculate the characteristic impedance using tools provided by the layout software. Ask the PCB manufacturer to provide the final values usually calculated using dedicated software and production stack-ups. It is sometimes possible to request an impedance test coupon on side of the panel to measure the real impedance of the traces.
· Although FR-4 dielectric material can result in high losses at high frequencies, it can still be an appropriate choice for RF designs. In which case, aim to: o Minimize RF trace lengths to reduce dielectric losses. o If traces longer than few centimeters are needed, use a coaxial connector and cable to reduce losses. o For good impedance control over the PCB manufacturing process, design the stack-up with wide 50 traces with width of at least 200 µm. o Contact the PCB manufacturer for specific tolerance of controlled impedance traces. As FR-4 material exhibits poor thickness stability it gives less control of impedance over the trace width.
· For PCBs with components larger than 0402 and dielectric thickness below 200 µm, add a keep-out, that is, some clearance (void area) on the ground reference layer below any pin on the RF transmission lines. This helps to reduce the parasitic capacitance to ground.
· Route RF lines in 45 ° angle and avoid acute angles. The transmission lines width and spacing to GND must be uniform and routed as smoothly as possible.
· Add GND stitching vias around transmission lines. · Provide a sufficient number of vias on the adjacent metal layer. Include a solid metal connection
between the adjacent metal layer on the PCB stack-up to the main ground layer. · To avoid crosstalk between RF traces and Hi-impedance or analog signals, route RF transmission
lines as far from noise sources (like switching supplies and digital lines) and any other sensitive circuit. · Avoid stubs on the transmission lines. Any component on the transmission line should be placed with the connected pin located over the trace. Also avoid any unnecessary components on RF traces.
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MAYA-W4 series – System integration manual Figure 9 shows a coplanar trace design example connecting the module RF pin to an edge mounted SMA connector. From top to bottom right: top layer, layer 2, and layer 3.
Figure 9: RF trace, coplanar microstrip, and ground design example
Figure 10 shows typical artwork implementing a coplanar microstrip on three adjacent layers. The trace includes from the module pad to the SMA connector (module-side): · Coplanar microstrip, section (1) · Impedance matching PI network, (SMA-side) · Coplanar microstrip, section (2), and · Edge mounted SMA RF connector
Figure 10: Layout example showing implementation
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The ground clearance on layer 2 allows for a wider microstrip, which is less lossy than a narrow one. The ground clearance is especially critical in the 5 GHz band. A wider trace also has less impedance variation over PCB production batches due to the absolute tolerances in the PCB etching process. Figure 11 shows the layout of pads for a U.FL connector. Pay special attention to the GND clearance under the signal pad, which must be implemented to minimize capacitive load.
Figure 11: U.FL connector layout showing top layer (left) and inner layer 1 (right)
3.3 Supply interfaces
Power supply design significantly impacts RF performance and stability. To ensure optimal operation, select suitable power sources and appropriately rated bypass capacitors. Carefully route power supply nets or planes and incorporate robust power and ground planes in the PCB stack-up.
Pay close attention to the schematic, PCB layout, and the module supply design guidelines here.
3.3.1 Module supply design
Although the GND pins are internally connected in the module, it is advisable to connect all available ground pins on the application board to solid ground with a good (low impedance) connection to host PCB ground. This minimizes power loss, improves RF performance, and allows for more efficient thermal performance.
Low impedance connection of the module supply pins, supplied by a DC supply source, is required for accurate RF performance.
Consider the following guidelines when developing the schematic:
· All power supply pins must be connected to an appropriate DC source. · Any series component with an Equivalent Series Resistance (ESR) greater than a few m should
be avoided. The only exception to this general rule is the use of ferrite beads for DC filtering. To avoid possible instability in the DC supply, only use ferrite beads if needed. · For high-frequency filtering, additional bypass capacitors in the range of 100 nF to 1 µF are required on all supply pins. Offering low ESR/ESL resistance, a class II ceramic capacitor with an X7R or X5R dielectric is well suited for this purpose. Bypass capacitors of a smaller size can be chosen to minimize ESL (Equivalent Series Inductance) in the manufacturing process. The capacitor should be placed as close as possible to the module supply pin.
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· To help filter current spikes from the RF section and avoid ground bounce, a minimum bulk
capacitance of 10 µF should be applied to the 1V8 and 3V3 rails (optionally on VIO_SD and VIO) and placed close to the module supply pins. Offering low ESR/ESL resistance, a class II ceramic capacitor with an X7R or X5R dielectric is well suited for this purpose. Special care should be taken in the selection of X5R/X7R dielectrics due to capacitance derating versus DC bias voltage.
3.3.1.1 Guidelines for supply circuit design using an SMPS
A Switched Mode Power Supply (SMPS) is generally recommended for converting the main supply to the module supply when the voltage difference is relatively high. In these circumstances, an SMPS dissipates less power and heat than an LDO. By contrast, an LDO is generally simpler to use and does not generate the amount of noise an SMPS might.
To comply with the module voltage supply requirements described in Table 1, the characteristics of the SMPS should meet the following prerequisites:
· Power capability: The regulator, together with any additional filter in front of the module, must be capable of providing a voltage within the specified operating range. It must also be capable of delivering the specified peak current.
· Low output ripple: The peak-to-peak ripple voltage of the switching regulator must not exceed the specified limits. This requirement is appliable to both the voltage ripple generated by the SMPS at operating frequency and the high-frequency noise generated by power switching.
· PWM/PFM mode operation: It is advisable to select regulators that support a fixed Pulse Width Modulation (PWM) mode. Pulse Frequency Modulation (PFM) mode typically exhibits higher ripple and can affect RF performance. If power consumption is not a primary concern, PFM/PWM mode transitions should be avoided in favor of fixed PWM operation to reduce the peak-to-peak noise on the voltage rails. In mixed PWM/PFM mode, switching regulators can be used provided that the PFM/PWM modes and transition between modes complies with the requirements.
3.3.1.2 Guidelines for supply circuit design using an LDO linear regulator
The use of a linear regulator is appropriate when the difference between the available supply rail and the module supply is relatively low. Linear regulators can also be considered for powering 1.8 V domains particularly those having low current requirements and those cascaded from an SMPSgenerated low voltage rail.
To comply with the module voltage requirements summarized in Table 1, the characteristics of the Low Drop-Out (LDO) linear regulator used to power the voltage rails must meet the following prerequisites:
· Power capabilities: The LDO linear regulator must be able to provide a voltage within the specified operating range. It must also be capable of withstanding and delivering the maximum specified peak current while in “connected mode”.
· Power dissipation: The power handling capability of the LDO linear regulator must be checked to limit its junction temperature to the maximum rated operating range. The worst-case junction temperature can be estimated as shown below: , = ( – ) + Where: is the junction-to-ambient thermal resistance of the LDO package6, is the current consumption of the given voltage rail in continuous TX/RX mode and is the maximum operating temperature of the end product inside the housing.
6 The thermal dissipation capability reported in datasheets is usually tested on a reference board with adequate copper area (see also JESD51 [17]). Junction temperature on a typical PCB can be higher than the estimated value due to the limited space to dissipate the heat. Thermal reliefs on pads also affect the capability of a device to dissipate heat.
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3.4 Data communication interfaces
3.4.1 SDIO 3.0 interface
The SDIO 3.0 bus in MAYA-W4 series modules support a clock frequency up to 208 MHz, which means that special care must be taken to guarantee signal integrity and minimize electromagnetic interference (EMI) issues. The signals should be routed with a single-ended impedance of 50 . It is advisable to route all signals on the bus so that they are of the same length and the appropriate grounding in the surrounding layers. The total bus length should be kept to a minimum. To minimize crosstalk with other parts of the circuit, the layout of the SDIO bus should be designed with adequate isolation between its signals and surrounding busses/traces.
Implement an undisrupted return-current path in close vicinity to the signal traces. Figure 12 shows an optional application schematic for the SDIO bus in MAYA-W4, while Table 14 summarizes the electrical requirements of the bus. Even though MAYA-W4 includes on chip Pull-up resistors it is advisable to add external ones for optimum pull-up to match routing and host CPU impedance.
Figure 12: SDIO application schematic
A small value capacitor in the range of a few pF to GND could be considered for SDIO_CLK as
an EMI debug option and signal termination. This capacitor should be placed as close as possible to the MAYA-W4 clock input pin and can be assembled only for EMI purpose. The capacitor value adds to total line capacitance and must not exceed total allowed capacitance to avoid violating clock rise and fall timing specifications.
Signal group CLK, CMD, DAT[0:3] CLK, CMD, DAT[0:3] DAT[0:3] CMD CLK, CMD, DAT[0:3] CLK, CMD, DAT[0:3] CMD, DAT[0:3] CLK CMD, DAT[0:3]
Parameter Single ended impedance, 0 Impedance control Pull-Up range, Rdat Pull-Up range, Rcmd Series termination (Host side), Rterm7 Bus length8 Bus skew length mismatch to CLK Center to center CLK to other SDIO signals9 Center to center between signals11
Table 14: SDIO bus requirements
Min.
0 – 10% 10 10 0
Typ. 50
0 47 10 0
-3 4*W 3*W
Max.
0 + 10% 100 50
100 +3
Unit k k mm mm
7 Series termination values larger than typical recommended only for addressing EMI issues 8 Routing should minimize the total bus length. 9 To accommodate BGA escape, center-to-center spacing requirements can be ignored for up to 10 mm of routed length.
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3.4.2 High-speed UART interface
The high-speed UART interface for the MAYA-W4 complies with the Bluetooth HCI UART Transport layer. The module uses the settings shown in Table 15.
UART Settings Baud rate default after reset Baud rate default after firmware load Data bits Parity bit Stop bit Flow Control
115200 baud 115200 baud 8 No parity 1 stop bit RTS/CTS
Table 15: HCI UART transport layer settings
RTS/CTS flow control is used to prevent temporary UART buffer overrun. · If RTS is 0 (output, active low), the module is ready to receive, and the host is allowed to send. · If CTS is 0 (input, active low), the host is ready to receive, and the module is allowed to send.
The use of hardware flow control with RTS/CTS is mandatory.
Baud rate 1200 2400 4800 9600 19200
38400 57600 76800 115200 230400
460800 500000 921600 1000000 1382400
1500000 1843200 2000000 2100000 2764800
3000000
Table 16: Possible baud rates for the UART interface
After a hardware reset, the UART interface is configured for 115200 baud. See Bluetooth driver bringup for information on how to change the baud rate.
3.5 General high-speed layout guidelines
These guidelines describe the best practices for the layout of all high-speed busses on MAYA-W4. Designers should prioritize the layout of higher speed busses. Low frequency signals, other than those with high-impedance traces, are generally not critical to the layout.
Low frequency signals with high-impedance traces (such as signals driven by weak pull resistors)
can be affected by crosstalk. For these high impedance traces, a supplementary isolation of 4*W (four times the line width) from other busses is recommended.
3.5.1 General considerations for schematic design and PCB floor planning
· Verify which signal bus requires termination and add appropriate series resistor terminations to the schematics.
· Carefully consider the placement of the module with respect to the antenna position and host processor. Minimize RF trace length first and then the SDIO bus length.
· SDIO bus routing must aim to keep layer-to-layer transition to a minimum. · Verify the allowable stack-ups, and the controlled impedance dimensioning for antenna traces and
busses, with the PCB manufacturer. · Verify that the power supply design and power sequence are compliant with the MAYA-W4
specifications described in System function interfaces.
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3.5.2 Component placement
· Accessory parts like bypass capacitors must be placed as close as possible to the module to improve filtering capability. Prioritize placing the smallest capacitors close to module pins.
· Do not place components close to the antenna area. Follow the recommendations of the antenna manufacturer to determine distance of the antenna in relation to other parts of the system. Designers should also maximize the distance of the antenna to High-frequency busses, like DDRs and related components. Alternatively, consider an optional metal shield to reduce interferences that might otherwise be picked up by the antenna and subsequently reduce module sensitivity.
3.5.3 Layout and manufacturing
· Avoid stubs on high-speed signals. Test points or component pads should be placed over the PCB trace.
· Verify the recommended maximum signal skew for differential pairs and length matching of buses.
· Minimize the routing length; longer traces degrade signal performance. Ensure that the maximum allowable length for high-speed busses is not exceeded.
· Ensure to track any impedance matched traces. Consult early with the PCB manufacturer for proper stack-up definition.
· RF, analog, and digital sections should have dedicated and clearly separated areas on the board. · No digital routing is allowed in the GND reference plane area of RF traces (ANT pins and Antenna). · Designers are strongly recommended to avoid digital routing beneath all layers of RF traces. · Ground cuts or separation are not allowed below the module. · As a priority, minimize the length of the RF traces. Then, minimize bus length to reduce potential
EMI issues related to the radiation of digital busses. · Couple all traces (Including low speed or DC traces) with a reference plane (GND or power). · Hi-speed busses are not allowed to change reference plane. If a change to the reference plane is
unavoidable, some capacitors and an adequate number of vias, connecting the reference planes, must be added in the area of transition to provide a low impedance return path through the various reference planes. · Trace routing should maintain a distance that is greater than 3*W from the edge of the ground plane routing. · Power planes should maintain a safe distance from the edge of the PCB. The distance must be sufficient to route a ground ring around the PCB, and the ground ring must then be stitched to other layers through vias. · Route the power supply in low impedance power planes. If you choose to route the power supply with traces, do not route loop structures.
The heat dissipation during continuous transmission at maximum power can significantly raise
the temperature of application baseboards under MAYA-W4 series modules. Avoid placing temperature sensitive devices close to the module and provide these devices with sufficient grounding to transfer generated heat to the PCB.
3.6 Module footprint and paste mask
Figure 13 shows the pin layout of MAYA-W4 series modules. The proposed land pattern layout complements the pin layout of the module. Both Solder Mask Defined (SMD) and Non-Solder Mask Defined (NSMD) pins can be used with adherence to the following considerations:
· All pins should be Non-Solder Mask Defined (NSMD) · To help with the dissipation of the heat generated by the module, GND pads must have good
thermal bonding to PCB ground planes.
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The suggested stencil layout for MAYA-W4 modules should follow the copper pad layout, also shown in Figure 13.
Figure 13: Recommended footprint for MAYA-W4, bottom view
The “RF KEEP_OUT AREA” is only applicable on MAYA-W4x6 variants when using the internal PCB antenna. The “RF KEEP_OUT AREA” can be omitted for the other module variants.
3.7 Thermal guidelines
MAYA-W4 series modules are designed to operate from -40 °C to +85 °C at an ambient temperature inside the enclosure box. The board generates heat during high loads that must be dissipated to sustain the lifetime of the components.
Improving thermal dissipation in the module decreases its internal temperature and consequently increases the long-term reliability of device applications operating at high ambient temperatures. The module generates large amounts of thermal power during high loads that must be dissipated.
For best performance, application PCB layouts should adhere to the following guidelines:
· Vias specification for ground filling: 300/600, with no thermal reliefs allowed on vias. · Ground via densities under the module: 50 /2; thermal vias can be placed in gaps between
the thermal pads of the module. · Minimum layer count and copper thickness: 4 , 35 . · Minimum board size: 5570 . · To optimize the heat flow from the module, power planes and signal traces should not cross the
layers beneath the module.
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These recommendations facilitate a design that is capable of achieving a thermal characterization parameter of = °/ for MAYA-W460, MAYA-W461, and MAYA-W471 and = °/ for MAYA-W466 and MAYA-476 where, refers to the junction between the module and the bottom side of the main PCB characterization parameter.
Use the following hardware techniques to further improve thermal dissipation in the module and optimize its performance in customer applications:
· Maximize the return loss of the antenna to reduce reflected RF power to the module. · Improve the efficiency of any component that generates heat, including power supplies and
processor, by dissipating it evenly throughout the application device. · Provide sufficient ventilation in the mechanical enclosure of the application. · For continuous operation at high temperatures, particularly in high-power density applications or
smaller PCB sizes, include a heat sink on the bottom side of the main PCB. The heat sink is best connected using electrically insulated / high thermal conductivity adhesive10.
3.8 ESD guidelines
In compliance with the following European regulations, designers must implement proper protection measures against ESD events on any pin exposed to end users:
· ESD testing standard CENELEC EN 61000-4-2 [11] · Radio equipment standard ETSI EN 301 489-1 [12]
The minimum requirements as per these European regulations are summarized in Table 17.
Application
All exposed surfaces of the radio equipment and any ancillary equipment in the end product.
Category Contact discharge Air discharge
Immunity level 4 kV 8 kV
Table 17: Minimum ESD immunity requirements based on EN 61000-4-2
Compliance with the protection levels specified in EN 61000-4-2 [11] are fulfilled by including proper ESD protection in parallel to any susceptible trace that is close to areas accessible to end users.
Special care should be taken with the RF_ANT pins that, if exposed, might be needed to be
protected with an ESD absorber with adequate parasitic capacitance. For 5 GHz operation, a
protection with maximum internal capacitance of 0.1 pF is advised.
3.9 Design-in checklists
3.9.1 Schematic checklist
Check that the module pins have been properly numbered and designated in the schematic
(including thermal pins). See Pin definition in the MAYA-W4 data sheet [1].
Power supply design complies with the voltage supply requirements in Table 1 and the power
supply requirements described in the module data sheet [1].
The Power-up sequence has been properly implemented. Adequate bypassing has been included in front of each power pin as described in Component
placement.
Each signal group is consistent with its own power rail supply or proper signal translation has been
provided. See Pin definition in the MAYA-W4 data sheet [1].
Configuration pins are properly set at bootstrap. See Configuration pins.
10 Typically not required.
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SDIO bus includes series resistors and pull-ups, if needed. See also Figure 12 and SDIO 3.0
interface.
Unused pins are properly terminated. See Unused pins. A pi-filter is provided in front of each antenna for final matching. High-speed UART interface. Additional RF co-location filters have been considered in the design. See block diagrams in the
MAYA-W4 data sheet [1].
3.9.2 Layout checklist
PCB stack-up and controlled impedance traces follow the recommendations given by the PCB
manufacturer. See RF transmission line design.
All pins are properly connected, and the footprint follows u-blox pin design recommendations. See
Module footprint and paste mask.
Proper clearance has been provided between the RF and digital sections of the design. See Layout
and manufacturing.
Proper isolation has been provided between antennas (RF co-location, diversity, or multi-antenna
design). See Layout and manufacturing.
Bypass capacitors have been placed close to the module. See Component placement. Low impedance power path has been provided to the module. See Component placement. Controlled impedance traces have been properly implemented in the layout (both RF and digital)
and the recommendations provided by the PCB manufacturer have been followed. See RF transmission line design and Component placement.
50 RF traces and connectors follow the rules described in Antenna design. RF keep-out area has been implemented for MAYA-W4x6 variants using the internal antenna. Antenna integration has been reviewed by the antenna manufacturer. Proper grounding has been provided to the module for the low impedance return path and heat
sink. See Layout and manufacturing.
Reference plane skipping has been minimized for high frequency busses. See Layout and
manufacturing.
All traces and planes are routed inside the area defined by the main ground plane. See Layout and
manufacturing
u-blox has reviewed and approved the PCB12.
12 This is applicable only for end-products based on u-blox reference designs.
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4 Module migration
Application products may be designed so that they can migrate from one module generation to another typically to reduce unutilized functionality, lower production costs or integrate a later module design to include additional functionality that is unavailable in an existing design.
All modules in the MAYA family share the same physical size (mechanical dimensions) and the same land pattern, which allows them to be used interchangeably in your application design. However, slight deviations in pin assignments, such as which pins serve specific functions, or the exact layout of the land pattern can occur between the various module generations.
To design your product application for migration to either a later or an earlier module generation: · Create a draft design integrating the target module – that is, the main module you plan to include
in your product. · To get an overview of the pinout commonalities and deviations between the different module
generations, compare the pin assignment tables of the modules and the schematic drawings of your application design carefully. · Mitigate all identified differences using the information in this chapter.
4.1 Generic considerations
Several aspects of migrating to previous and later module generation apply universally to all u-blox modules:
· Host interfaces are implemented consistently supported in all module generations and are always assigned to the same pins. Modules that support additional functions might include dedicated non-generic interfaces.
· Configuration pins used for selecting interfaces are always assigned to the same pins, but the number of configuration pins might differ between the different module generations. Implement PD resistor placeholders to include the full set of configuration pins. Make sure that the additional “inactive” configuration pins are in correct state during power-up. This is particularly important to if the additional configuration pins are connected and used by other circuitry.
· Control signals are generally identical for modules with chips from the same supplier. Use 0 series resistors to connect or disconnect the signals to use or not to use according to your choice.
· Power supplies are commonly assigned to the same pins for all modules generations. Use standard series voltage regulators to conveniently change the voltage and current capabilities – if needed. Power switches can be used if the supply voltages are already available. Key considerations include: o Implement voltage supplies sources, LDO’s or SMPS’s, by using standard series voltage regulators, which enable the use of drop-in compatible versions to achieve the desired voltage level for the specific used module. o Current budget. Ensure the current budget of the application hardware is designed to support all module variants, including the one with the highest current consumption. o Power On and off sequence. Use Host CPU GPIOs to enable voltage regulators or load switches in the appropriate order during the start-up sequence of the target module generation. Alternatively use hardware-sequenced implementations.
· RF interface connections are commonly assigned to the same pins. · Unused pins: All pins have internal keeper resistors. Leave unused pins open.
Software differs between each module generation and is not within the scope of this chapter.
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4.2 MAYA-W4 migration
Several aspects of migration to a later module generation are unique to the MAYA family.
4.2.1 Data interfaces
MAYA-W4 includes interfaces for Wi-Fi, Bluetooth, and 802.15.4 data communication. Implement these according to the instructions in this document. The interface selection is activated during startup according to the logic state of the configuration pins.
· SDIO interface for Wi-Fi positioned on generic MAYA pins. The SDIO interface includes an optional interrupt output signal that may be used for data transfer requests in your design.
· UART interface for Bluetooth is implemented on generic MAYA pins. · SPI interface for 802.15.4 Wi-Fi. This is not a standard interface for the MAYA family. Use 0
resistors to connect or disconnect this interface or optionally set the connected HOST CPU’s pins to high impedance. The SPI interface includes an interrupt output signal that may also be utilized in the design. · USB interface for Wi-Fi and Bluetooth. This is not generic interface for the MAYA family. The default USB implementation includes series resistors on DM and DP, which can be used to connect or disconnect the USB from the MAYA module. Vbus is used for USB supply and for indicating USB connection on the customer application, and is connected to a generic pin used for the 3V3 supply voltage in other MAYA modules. Include 0 resistors to connect this pin to either Vbus or 3V3 supply. Use 0 resistors to connect Vbus to the USB indicator pin.
4.2.2 Configuration pins
MAYA-W4 includes three configuration pins (CON[2:0]) for interface selection and two additional pins (CON[3] and CON[5]) for other configurations. It is important that all of these pins are in the correct state during start-up. The CON[3] and CON[5] pins can be left unconnected (NC), but if they are connected, make sure that they are not pulled low by any external circuitry during boot-up.
· Dedicated configuration pins CON[2:0] allocated on generic pins. · Additional configuration pins CON[3] and CON[5]. These pins can be optionally used for other
purposes but must be set to the correct state during boot-up, as described in the MAYA-W4 data sheet [1].
Configuration pins can deviate between MAYA family modules. Study the data sheet
[1][2][3][4] and system integration manual [5][6][7][8] for the targeted modules. In preparation for future migration, implement the full set of configuration pins by adding “placeholders” for pull-down resistors.
4.2.3 Wake-up and Reset interface
MAYA-W4 includes the generic set of NXP control signals.
· Power Down signal, PDn, with a pull-up resistor included in the module. PDn is allocated to a standard pin for MAYA family modules with NXP chipset.
· Individual reset signals: one for Wi-Fi and another for IEEE 802.15.4 (Zigbee) and Bluetooth narrowband channels. Connect these to Host CPU via 0 resistors to implement these functions required for your chosen module generation.
· Wake up signals for Module to Host CPU and Host CPU to Module. Optionally connect these through 0 resistors.
Reset and Wake-up signals might differ between modules. Study the data sheet and the
system integration manual for the target module generation to decide which signals to implement. Handle deviations with either series 0 resistors or set the Host CPU pin to high impedance.
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4.2.4 Power-up
The Power-up sequences generally differ for each module generation.. In all MAYA module generations, the power down signals (PDn or WL_EN/BT_EN) must be set low during the power up before external supplies are applied.
In MAYA-W4, PDn must be held low during start up and released when the power is stable, or later when the module is powered on. Other than this, there are no additional requirements for the powerup sequence. The external power rails can be applied in any order provided that PDn remains low.
For correct implementation, study the data sheet and the system integration manual
[5][6][7][8] for the target module generation.
4.2.5 Power supply
The power supply pins are in the same position across all MCU generations. Implement the specified supply voltages to support the required current consumption.
For MAYA-W4 Vbus is allocated to one of the 3V3 pins. Connect Vbus to MAYA-W4 pins
through a 0 resistor. For other MAYA generations that use this pin as power supply, connect Vbus to a 3V3 voltage node by a 0 resistor.
4.2.6 RF
The RF signals are implemented on generic pins, which are positioned consistently across all module generations. These signals all have 50 characteristic impedance. Ensure that the antenna Pi network is consistent across all module generations. Otherwise, impedance matching may need to be adjusted to account for slight variations between module variants.
The RF standard and frequency band used for each RF pin might differ. For correct
implementation, study the data sheet and the system integration manual [5][6][7][8] for the target module generation.
4.2.6.1 Internal antenna
Place modules with internal antennas on the application PCB in accordance with the information described within the respective System integration manual [5][6][7][8].
· Niche antennas must be placed on the edge of the application PCB with the antenna facing outwards.
· Any copper, traces, or GND planes, must be cleared on all layers beneath the module’s antenna area.
4.2.6.2 External antenna
Connect external antennas with 50 microstrips and 50 RF connectors. If needed, tune the antenna matching PI network components to achieve full antenna performance.
If migrating to a module operating in an extended frequency band, make sure that the selected antenna covers the required frequency bands.
4.3 Mechanical design
All module generations are mechanically compatible and share the same land pattern design with some exceptions that are described in the Mechanical specification of the data sheet [1][2][3][4].
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4.4 Production and handling
The soldering process and profile are the same for all module generations. When preparing for reflow soldering, note that the number of reflow cycles can be dissimilar between each module generation and each module variant.
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5 Software
The chapter describes the available software options for MAYA-W4 series modules, which are based on the NXP IW610 chipset family. The drivers and firmware required to operate MAYA-W4 series modules are developed by NXP and are pre-integrated into the Linux/Android BSP for NXP i.MX processors [19] and the MCUXpresso SDK for NXP MCU devices [20].
Documentation for the NXP software releases includes release notes and a list of supported software features. The drivers are provided free of charge as open-source code under NXP licensing terms.
As open-source code, the drivers can be integrated or ported to other non-NXP based host
platforms.
5.1 Available software packages
Open-source and MCUXpresso SDK driver support for IW610 is still pending. Contact your local
support team for the latest MAYA-W4 software deliverables.
5.1.1 Open-source Linux/Android drivers
The Wi-Fi driver and firmware for MAYA-W4 series modules are integrated into the Linux BSP for NXP i.MX processors. Yocto recipes for the driver and firmware, that can be used to develop custom Linuxbased systems, are part of the NXP i.MX Linux BSP.
The latest version of the driver source code and Wi-Fi/Bluetooth firmware are available from the following open-source repositories:
· Wi-Fi driver: · Firmware:
https://github.com/nxp-imx/mwifiex https://github.com/nxp-imx/imx-firmware/
Use the repository branches matching the latest Linux BSP release version. At the time of this
document publication, this is release lf-6.6.36_2.1.0.
Check for the latest BSP release and available incremental patch releases on the NXP i.MX
Linux page [19].
Yocto recipes for the driver and firmware (nxp-wlan-sdk, kernel-module-nxp-wlan, firmware-nxpwifi) are included in the NXP meta-imx and meta-freescale layers.
Bluetooth uses the hci_uart or btnxpuart driver from the Linux kernel and BlueZ host stack. The OpenThread stack (provided by Google Nest Team) and Matter (Project CHIP) are used for 802.15.4 based applications. NXP provides an OpenThread binary that can be run as a Thread application, or it can be built from source code.
5.1.2 MCUXpresso SDK
The MCUXpresso SDK [20] is a comprehensive software enablement package for MCU devices from NXP. It includes production-grade software with optionally integrated real-time operation systems (RTOS), integrated enabling software technologies (stacks and middleware), reference software, and more. The SDK includes the Wi-Fi, Bluetooth and 802.15.4 drivers and firmware for supported NXP MCUs integrated into MAYA-W4 series modules. MCUXpresso Wi-Fi, Bluetooth and 802.15.4 support for the NXP IW610 chipset in MAYA-W4 is currently available for the FreeRTOSTM real-time operation system.
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5.2 u-blox software deliverables
u-blox also supply the following additional software deliverables for MAYA-W4 series modules: · A Yocto/OpenEmbedded meta layer, which includes recipes for related development tools. For
more information about the Yocto layer, see also Yocto meta layer.
For the latest MAYA-W4 series software deliverables, contact your local support team.
5.2.1 Yocto meta layer
Yocto is an open-source project aimed at helping the development of custom Linux-based systems for embedded products. It provides a complete development environment with tools, documentation, and metadata like recipes, classes, and configuration. Yocto is based on the OpenEmbedded build system.
A Yocto/OpenEmbedded meta layer “meta-ublox-modules” is provided by u-blox for all host-based modules. This layer is used in Yocto projects to build the image for most host platforms that run Linux kernels. It contains the recipes used to build the Linux drivers, support tools, and any configuration files that are needed to operate the modules.
Item Build recipe Patches Calibration files Output power configuration Modprobe rules Manufacturing package recipes
Description
Includes all the instructions to extract, compile, and install the drivers, firmware and tools in the root file system of the host system image.
Used to fix bugs in u-blox-distributed drivers seen either locally or reported by the vendor.
Calibration files, provided by u-blox, used while loading the driver. These files store the tuning parameters needed for RF parts in the module, like the crystal.
RF power specific files for the different bands, rates and countries are stored in the configuration files provided by u-blox.
Configuration files for the modprobe utility used to store the driver load parameters.
Includes different recipes for building the manufacturing tools. These recipes are used in production and RF-related tests.
Table 18: Yocto layer content
Calibration files are needed for the modules during the prototype stage of development. After
prototyping, all required calibrations are programmed into the OTP on the module.
Further information about the Yocto layer and how to integrate it into the development
environment is provided in the README files of the meta layer.
5.3 Software architecture
From a software perspective, host-based MAYA-W4 series modules contain only on-board OTP memory with calibration parameters and MAC addresses. Consequently, the modules require a hostside driver and device firmware to run. At startup and at every reset or power cycle, the host driver needs to download the firmware binary file to the module. The firmware binary file is typically a “combo” firmware, which comprises the Wi-Fi, Bluetooth, and 802.15.4 firmware images. This file is downloaded to the module by the Wi-Fi driver through the Wi-Fi host interface.
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Figure 14 shows the different software components and upper layers required for the operation of MAYA-W4 series modules in a Linux OS.
Figure 14: Basic Wi-Fi, Bluetooth, and 802.15.4 software architecture
The Wi-Fi driver (mxm_mwifiex) is a unified driver for all supported NXP Wi-Fi chipsets, which allows simple migration and forward compatibility with future devices. Driver sources can be used or ported for other non-NXP host platforms. The Wi-Fi host driver interfaces the lower-layer bus drivers with the upper-layer protocol stacks of the operating system. It uses the TCP/IP stack from the Linux kernel for data transmission, and the cfg80211 subsystem in the kernel is used for configuration and control.
Bluetooth uses the Linux BlueZ host stack through the HCI UART interface of the module, but other third-party stacks can also be supported. The hci_uart or btnxpuart driver from the Linux kernel is used for the serial UART interface of the module.
Thread is an IPv6-based networking protocol designed for low-power Internet of Things devices in an IEEE802.15.4 wireless mesh network. OpenThread [25], released by Google, is an open-source implementation of Thread. The 802.15.4 subsystem of MAYA-W4 works as controller in OpenThread Radio Co-Processor (RCP) design. The OpenThread core runs on the host processor and communicates with the controller via OpenThread Daemon (Ot-daemon) through SPI interface over the Spinel protocol. Clients can connect to the UNIX socket of the Ot-daemon and communicate using OpenThread CLI as a protocol. A Thread Border Router (see OpenThread Border Router [26]) connects a Thread network to other IP-based networks, such as Wi-Fi or Ethernet.
5.4 Bringing-up the Linux drivers
When initializing, configuring, and activating Wi-Fi, Bluetooth, and 802.15.4 radios for the first time, the “bring-up” process involves loading the necessary drivers, configuring settings, and ensuring that the hardware components are functioning correctly. Use the procedures described in this section to get the wireless radios up and running for the first time under Linux.
The bring-up process is described for the SDIO-UART-SPI host interface combination based
on a pre-production software release.
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5.4.1 Wi-Fi driver
To bring up the Wi-Fi driver:
1. Prior to loading the driver, check the kernel log to make sure that the MAYA-W4 series module is reported on the SDIO bus of the host system, as shown in the following example:
mmc1: new ultra high speed SDR104 SDIO card at address 0001 2. Use the following command to load the Wi-Fi driver and firmware:
root@imx8mqevk:~# modprobe moal mod_para=nxp/wifi_mod_para.conf
The Wi-Fi driver parameters are configured in the /lib/firmware/nxp/wifi_mod_para.conf file in a chipset-specific block for MAYA-W4:
SDIW610 = { cfg80211_wext=0xf max_vir_bss=1 cal_data_cfg=none ps_mode=1 auto_ds=1 host_mlme=1 fw_name=nxp/sduartspi_iw610.bin.se
}
In this configuration, the Wi-Fi driver downloads combo-firmware for Wi-Fi, Bluetooth, and 802.15.4 to the module. Other firmware options are shown in Table 19.
Firmware image
sduartspi_iw610.bin.se
sduart_iw610.bin.se sd_iw610.bin.se uartspi_iw610.bin.se uart_iw610_bt.bin.se usbusbspi_iw610.bin.se usb_iw610.bin.se
Description Combo-firmware for Wi-Fi (SDIO), Bluetooth (UART), and 802.15.4 (SPI) Combo-firmware for Wi-Fi (SDIO) and Bluetooth (UART) Wi-Fi only firmware for parallel download (SDIO) Bluetooth (UART) and 802.15.4 (SPI) firmware for parallel download Bluetooth only firmware for parallel download (UART) Combo-firmware for Wi-Fi (USB), Bluetooth (USB), and 802.15.4 (SPI) Wi-Fi only firmware for parallel download (USB)
Table 19: Firmware images
3. Use the following command to search and display the Wi-Fi driver and firmware versions:
root@imx8mqevk:~# cat /proc/mwlan/adapter0/mlan0/info | grep version driver_version = SDIW610—18.99.5.p36-MM6X18514-(FP99) firmware_major_version=18.99.5
4. Use command iw dev to display and verify the available Wi-Fi interfaces, as shown in the following code example:
root@imx8mqevk:~# iw dev phy#0
Interface wfd0 addr ba:f4:4f:a5:6d:a1 type managed
Interface uap0 addr ba:f4:4f:a5:6e:a1 type AP
Interface mlan0 addr b8:f4:4f:a5:6d:a1 type managed
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Table 20 describes the functions of the Wi-Fi interfaces.
Interface mlan0 uap0 wfd0
Function Network interface for station mode functionality. Typically used with wpa_supplicant. Network interface for access-point functionality. Typically used with hostapd. Network interface for P2P functionality. Can operate in both group owner (GO) and group client (GC) modes.
Table 20: Wi-Fi network interfaces
5.4.2 Bluetooth interface
You bring up the Bluetooth interface using the NXP Bluetooth UART driver (btnxpuart) or the standard Linux HCI UART driver (hci_uart).
5.4.2.1 Using the NXP Bluetooth UART driver
The btnxpuart driver is available in the i.MX Linux BSP L6.1.22 and later. It supports a power-save feature that automatically puts the chip into a sleep state when idle.
To use the NXP Bluetooth UART driver, add a bluetooth sub node with a device compatibility string to the attached UART node in the device-tree file:
&uart1 { bluetooth { compatibility = “nxp,88w8987-bt”; fw-init-baudrate = <115200>; };
};
The Wi-Fi driver must be loaded first, with either Wi-Fi standalone or combo firmware, before loading the NXP Bluetooth UART driver. The btnxpuart driver takes care of downloading the Bluetooth standalone firmware if required.
To load the NXP Bluetooth UART driver, enter the following command:
root@imx8mqevk:~# modprobe btnxpuart
The btnxpuart driver automatically changes the UART baud rate to 3 Mbaud after the firmware
is downloaded.
5.4.2.2 Using the Linux HCI UART driver
To bring up the Bluetooth interface using the Linux HCI UART driver:
1. Download the firmware as combo-firmware by loading the Wi-Fi driver first, or as Bluetooth standalone firmware through the UART interface using a firmware loader tool.
2. Load the Linux HCI UART driver and attach the serial device for the HCI UART interface to the Linux BlueZ stack (using /dev/ttyUSB0 as example):
root@imx8mqevk:~# modprobe hci_uart root@imx8mqevk:~# hciattach /dev/ttyUSB0 any 115200 flow root@imx8mqevk:~# hciconfig hci0 up
3. Using the hciconfig command from BlueZ, verify that the Bluetooth HCI interface is up:
hci0: Type: Primary Bus: UART BD Address: B8:F4:4F:A5:6D:A0 ACL MTU: 1021:7 SCO MTU: 120:6 UP RUNNING RX bytes:1498 acl:0 sco:0 events:90 errors:0 TX bytes:1270 acl:0 sco:0 commands:90 errors:0
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4. The host application can change the UART baud rate with a vendor specific HCI command (OCF 0x0009). The command complete event is transmitted to the host at the old baud rate. After this, the host can switch to the new baud rate and then wait for 5 ms or more before sending the next command. HCI command syntax using hcitool:
hcitool i hci0 cmd 0x3f 0x0009 <4-byte little-endian value for baud rate>
For example, enter the following commands to change the baud rate to 3 Mbaud:
root@imx8mqevk:~# hcitool -i hci0 cmd 0x3f 0x0009 0xc0 0xc6 0x2d 0x00 root@imx8mqevk:~# killall hciattach root@imx8mqevk:~# hciattach /dev/ttyUSB0 any 3000000 flow root@imx8mqevk:~# hciconfig hci0 up
5.4.3 Creating a Thread network using the 802.15.4 radio
SPI communication protocol is used to interface between the host and the MAYA-W4 module. NXP provides pre-compiled OpenThread tools and SPI driver utility to establish the communication between i.MX 8M Mini and the MAYA-W4 module.
To create a Thread network with MAYA-W4 on the NXP i.MX 8M Mini platform using the open-source OpenThread stack [25]:
1. Copy the pre-compiled OpenThread tools to the host platform and check they have executable permission. Pre-compiled OpenThread tools include ot-ctl, ot-daemon, and spi-hdlc-adapter.
2. The NXP software package includes an SPI device tree file for the i.MX 8M Mini platform. Copy the SPI device tree file to the host platform and reboot the system.
root@imx8mmevk:~# cp <latest-IW610x-sw-package/OT-Tools-LNX-X_X_X-IMX8>/imx8mm-evkxxx.dtb /run/media/mmcblk2p1/imx8mm-evk.dtb
root@imx8mmevk:~# reboot
3. Download the firmware to the MAYA-W4 module. The combo firmware downloaded through the Wi-Fi driver includes the 802.15.4 radio firmware.
root@imx8mmevk:~# modprobe moal mod_para=nxp/wifi_mod_para.conf
4. Start OpenThread ot-daemon in the background.
root@imx8mmevk:~# ot-daemon “spinel+spi:///dev/spidev1.0?gpio-intdevice=/dev/gpiochip5&gpio-int-line=12&gpio-reset-device=/dev/gpiochip5&gpio-resetline=14&spi-mode=0&spi-speed=1000000&spi-reset-delay=500” &
The SPI command parameters are described in Table 21.
Parameter spinel+spi:// gpio-int-device gpio-int-line gpio-reset-device gpio-reset-line spi-mode spi-speed spi-reset-delay
Description Path to the SPI interface Path to the Linux sysfs-exported GPIO device with the SPI interrupt signal (SPI_INT) The offset index of the SPI interrupt signal (SPI_INT) in the GPIO device Path to the Linux sysfs-exported GPIO device with the 802.15.4 reset signal (IND_RST_NB) The offset index of the 802.15.4 reset signal (IND_RST_NB) in the GPIO device SPI mode to use (0-3) SPI speed in Hertz (max. 10 MHz) The delay after “RESET” assertion, in milliseconds
Table 21: SPI command parameters
5. Create a Thread network on MAYA-W4 and check the device state is set to “leader”, as described in Starting a Thread network and verifying the device state.
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Create a Thread network on the remote device and check the device state is set to “child”, as described in Starting a Thread network and verifying the device state. Note that the initial remote device state is set to leader until its status is accepted by the parent device, MAYA-W4.
root@imx8mmevk:~# ot-ctl state Child Done
6. Verify the assigned mesh-local addresses on MAYA-W4 (device A) and remote device B:
root@imx8mmevk:~# ot-ctl ipaddr fdc0:de7a:b5c0:0:0:ff:fe00:0c01 fdc0:de7a:b5c0:0:66bf:99b9:24c0:d55f fe80:0:0:0:18e5:29b3:a638:943b Done
# Routing Locator (RLOC) # Mesh-Local EID (ML-EID) # Link-Local Address (LLA)
7. Ping the child device using the mesh-local address:
root@imx8mmevk:~# ot-ctl ping fdc0:de7a:b5c0:0:66bf:99b9:24c0:d55f 16 bytes from fdc0:de7a:b5c0:0:66bf:99b9:24c0:d55f icmp_seq=1 hlim=64 time=17ms
8. To run a throughput test using iperf3 and mesh-local addresses. o Start iperf3 server on device A:
root@imx8mmevk:~# iperf -s -u -i 1 -w 400k -p 5005 -V -B <mesh-local-addr-A> o Start iperf3 client on device B:
root@imx8mmevk:~# iperf -c <mesh-local-addr-A> -B <mesh-local-addr-B> -u -b 250k -l 500 -V -i 1 -t 20 -p 5005
For more information about the OpenThread application features, see the OpenThread web page [25]. For more information about the OpenThread setup with MAYA-W4, contact your local support team.
5.4.3.1 Creating a Thread network
The OpenThread Command Line Interface (CLI) exposes configuration and management APIs. It allows users to issue commands and interact with OpenThread devices.
1. Stop any existing Thread network and apply a factory reset on 802.15.4 radio:
root@imx8mmevk:~# ot-ctl thread stop Done root@imx8mmevk:~# ot-ctl ifconfig down Done root@imx8mmevk:~# ot-ctl factoryreset Done 2. Initialize a new operational dataset (leader only):
root@imx8mmevk:~# ot-ctl dataset init new Done 3. Set the channel of operation:
root@imx8mmevk:~# ot-ctl channel 26 Done
4. Set the networkkey for the network: root@imx8mmevk:~# ot-ctl networkkey 00112233445566778899aabbccddeeff Done
5. Commit the active dataset:
root@imx8mmevk:~# ot-ctl commit active Done
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5.4.3.2 Starting a Thread network and verifying the device state
To start the Thread network and verify the state of the device: 1. Bring up the network interface:
root@imx8mmevk:/usr/sbin# ot-ctl ifconfig up Done 2. Start the Thread network: root@imx8mmevk:/usr/sbin# ot-ctl thread start Done 3. Check the current state of the device: root@imx8mmevk:/usr/sbin# ot-ctl thread state leader Done
5.5 Configuring antenna diversity
You enable/disable and configure the software antenna diversity feature from the command line interface (CLI) through the configuration file /proc/mwlan/adapter0/config. Check the antenna configuration status Read the antcfg parameter in the configuration file to retrieve information about the current antenna diversity configuration: cat /proc/mwlan/adapter0/config | grep antcfg The current antcfg setting defines the status. For example, the following response is returned if antenna diversity software is enabled: antcfg=0xffff 6000 1 The following response is returned if the configuration is set to one antenna: antcfg=0x1 Enable TX/RX software antenna diversity To enable TX/RX software antenna diversity with the default evaluation time interval, enter: echo “antcfg=0xffff” > /proc/mwlan/adapter0/config The evaluation time interval can be optionally configured. The default time interval is 6 s (0x1770 ms). To enable TX/RX software antenna diversity and set the evaluation time interval to 6 seconds, enter: echo “antcfg=0xffff 0x1770” > /proc/mwlan/adapter0/config
TX/RX software antenna diversity is only supported in Wi-Fi STA mode.
Disable TX/RX software antenna diversity To disable TX/RX software antenna diversity and set the antenna configuration to antenna 1, enter: echo “antcfg=1” > /proc/mwlan/adapter0/config
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5.6 Usage examples
The Wi-Fi and Bluetooth features and configurations for NXP-based wireless modules on i.MX Linux host platforms are described in the NXP User Manual UM11490 [21]. The document covers the initialization and configuration of the Wi-Fi and Bluetooth interfaces. It is applicable for MAYA-W4 series on i.MX 8 family NXP host processors and other NXP-based wireless modules.
The Wi-Fi features demonstrated in the NXP User Manual [21] are configured with the open source wpa_supplicant/hostapd and Linux utilities. The features include scanning for nearby access points, connecting to an access point, configuring the device as an access point, Wi-Fi security, Wi-Fi Direct, and throughput testing using the iperf utility.
The Bluetooth features utilize the Linux BlueZ host stack and comprise:
· Scan · Pair, · Bluetooth or Bluetooth Low Energy (LE) device connection · A2DP profile, hands-free profile · Bluetooth LE device GATT server operation
Guidelines for enabling driver debug logging are also provided.
For instructions describing the use of radio test mode on Linux hosts for regulatory compliance testing, see the NXP RF test mode application note [29].
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6 Handling and soldering
MAYA-W4 series modules are Electrostatic Sensitive Devices that demand the observance of
special handling precautions against static damage. Failure to observe these precautions can result in severe damage to the product.
6.1 ESD handling precautions
As the risk of electrostatic discharge in the RF transceivers and patch antennas of the module is of particular concern, standard ESD safety practices are prerequisite. See also Figure 15.
Consider also:
· When connecting test equipment or any other electronics to the module (as a standalone or PCBmounted device), the first point of contact must always be to local GND.
· Before mounting a patch antenna, connect the device to ground. · When handling the RF pin, do not touch any charged capacitors. Be especially careful when
handling materials like patch antennas (~10 pF), coaxial cables (~50-80 pF/m), soldering irons, or any other materials that can develop charges. · To prevent electrostatic discharge through the RF input, do not touch any exposed antenna area. If there is any risk of the exposed antenna being touched in an unprotected ESD work area, be sure to implement proper ESD protection measures in the design. · When soldering RF connectors and patch antennas to the RF pin on the receiver, be sure to use an ESD-safe soldering iron (tip).
Figure 15: Standard workstation setup for safe handling of ESD-sensitive devices
6.2 Packaging, shipping, storage, and moisture preconditioning
For information pertaining to reels, tapes, or trays, moisture sensitivity levels (MSL), storage, shipment, and drying preconditioning, see the MAYA-W4 series data sheet [1] and the Product packaging guide [9].
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6.3 Reflow soldering process
MAYA-W4 modules are surface mounted devices supplied on a multi-layer FR4-type PCB with goldplated connection pads. The modules are produced in a lead-free process using lead-free soldering paste. The thickness of solder resist between the host PCB top side and the bottom side of the MAYA-W4 module must be considered for the soldering process.
MAYA-W4 modules are compatible with industrial reflow profile for RoHS solders, and “no-clean” soldering paste is strongly recommended.
The reflow profile used is dependent on the thermal mass of the entire populated PCB, the heat transfer efficiency of the oven, and the type of solder paste that is used. The optimal soldering profile must be trimmed for the specific process and PCB layout.
A vacuum reflow process is not recommended to use for MAYA-W4 modules.
The target values shown in Table 22 and Figure 16 are given as general guidelines for a Pb-free
process only. For further information, see also the JEDEC J-STD-020E [14] standard.
Process parameter Pre-heat
Peak
Cooling General
Ramp up rate to TSMIN TSMIN TSMAX tS (from 25°C) tS (Pre-heat) TL tL (time above TL) TP tP (time above TP -5°C) Ramp-down from TL (max) Tto peak Allowed reflow soldering cycles
Unit K/s °C °C s s °C s °C s K/s s –
Target 3 150 200 150 110 217 90 245-250 30 6 300 See the MAYA-W4 series data sheet [1]
Table 22: Recommended reflow profile
Figure 16: Reflow profile
The lower value of TP and slower ramp down rate is preferred.
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6.3.1 Cleaning
Cleaning the modules is not recommended. Residues underneath the modules cannot be easily removed with a washing process.
· Cleaning with water will lead to capillary effects where water is absorbed in the gap between the baseboard and the module. The combination of residues of soldering flux and encapsulated water leads to short circuits or resistor-like interconnections between neighboring pins. Water will also damage the sticker and the inkjet printed text.
· Cleaning with alcohol or other organic solvents can result in soldering flux residues flooding into areas that are not accessible for post-wash inspections. The solvent will also damage the label and the ink-jet printed text.
· Ultrasonic cleaning will permanently damage the module and the crystal oscillators in particular. For best results use a “no clean” soldering paste and circumvent the need for a cleaning stage after the soldering process.
6.3.2 Other notes
· Boards with combined through-hole technology (THT) components and surface-mount technology (SMT) devices may require wave soldering to solder the THT components. Only a single wave-soldering process is allowed for boards populated with the modules. Miniature Wave Selective Solder processes are preferred over traditional wave soldering processes.
· Hand-soldering is not recommended. · Rework is not recommended. · Conformal coating can affect the performance of the module, which means that it is important to
prevent the liquid from flowing into the module. The RF shields do not provide protection for the module from coating liquids with low viscosity; therefore, care is required while applying the coating. Conformal coating of the module will void the warranty. · Grounding metal covers: Attempts to improve grounding by soldering ground cables, wick, or other forms of metal strips directly onto the EMI covers is done so at the customer’s own risk and will void the module warranty. The numerous ground pins on the module are adequate to provide optimal immunity to interferences. · The modules contain components which are sensitive to Ultrasonic Waves. Use of any Ultrasonic Processes (cleaning, welding, etc.) may damage the module. The use of ultrasonic processes together with the module will void the warranty.
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7 Regulatory compliance
All approvals are currently pending
7.1 General requirements
MAYA-W4 series modules are designed to comply with the regulatory demands of Federal Communications Commission (FCC), Innovation, Science and Economic Development Canada (ISED)14 and the CE mark. This chapter contains instructions on the process needed for an integrator when including the MAYA-W4 module into an end-product.
· Any deviation from the process described can cause the MAYA-W4 series module not to comply with the regulatory authorizations of the module and thus void the user’s authority to operate the equipment.
· Any changes to hardware, hosts, or co-location configuration might require new radiated emission and SAR evaluation and/or testing.
· The regulatory compliance of MAYA-W4 does not exempt the end-product from being evaluated against applicable regulatory demands; for example, FCC Part 15B criteria for unintentional radiators [16].
· The end-product manufacturer must follow all the engineering and operating guidelines, as specified by the grantee (u-blox).
· MAYA-W4 is for OEM integrators only. · Only authorized antenna(s) may be used. For the list of authorized antennas, see Approved
antennas In the end-product, the MAYA-W4 module must be installed in such a way that only authorized antennas can be used. · The end-product must use the specified antenna trace reference design, as described in the MAYA-W4 antenna reference design application note [24]. · Any notification to the end user about how to install or remove the integrated radio module is NOT allowed.
If these conditions can’t be met or any of the operating instructions are violated, the u-blox
regulatory authorization will be considered invalid. Under these circumstances, the integrator is responsible to re-evaluate the end-product including the MAYA-W4 series module and obtain their own regulatory authorization, or u-blox may be able to support updates of the u-blox regulatory authorization. See also Antenna requirements.
7.1 European Union regulatory compliance
MAYA-W4 series modules comply with the essential requirements and other relevant provisions of Radio Equipment Directive (RED) 2014/53/EU.
For information about the regulatory compliance of MAYA-W4 series modules against requirements and provisions in the European Union, see the MAYA-W4 Declaration of Conformity [28].
7.1.1 CE End-product regulatory compliance
7.1.1.1 Safety standard
In order to fulfill the safety standard EN 60950-1 [15], the MAYA-W4 module must be supplied with a Class-2 Limited Power Source.
14 Formerly known as IC (Industry Canada).
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7.1.2 CE Equipment classes
In accordance with Article 1 of Commission Decision 2000/299/EC15, MAYA-W4 is defined as either Class-1 or Class-2 radio equipment, the end-product integrating MAYA-W4 inherits the equipment class of the module.
For guidance on end product marking in according with RED, see http://ec.europa.eu/ Operation in the band 5150 – 5350 MHz is only for indoor use to reduce the potential for
harmful interference.
The EIRP of the MAYA-W4 module must not exceed the limits of the regulatory domain that the
module operates in. Depending on the host platform implementation and antenna gain, integrators have to limit the maximum output power of the module through the host software. For information about the corresponding maximum transmit power levels of Approved antennas.
7.2 Great Britain regulatory compliance
For information about the regulatory compliance of MAYA-W4 series modules against requirements and provisions in Great Britain, see also the MAYA-W4 UKCA Declaration of Conformity [27].
7.2.1 UK Conformity Assessed (UKCA)
The United Kingdom is made up of the Great Britain (including England, Scotland, and Wales) and
the Northern Ireland. Northern Ireland continues to accept the CE marking. The following notice is applicable to Great Britain only.
MAYA-W4 series modules have been evaluated against the essential requirements of the Radio Equipment Regulations 2017 (SI 2017 No. 1206, as amended by SI 2019 No. 696).
For guidance on end product marking in accordance with UKCA, see https://www.gov.uk/guidance/using-the-ukca-marking.
7.3 United states/Canada End-product regulatory compliance
u-blox represents that the modular transmitter fulfills the FCC/ISED regulations when operating in authorized modes on any host product given that the integrator follows the instructions as described in this document. Accordingly, the host product manufacturer acknowledges that all host products referring to the FCC ID or ISED certification number of the modular transmitter and placed on the market by the host product manufacturer need to fulfil all of the requirements mentioned below. Noncompliance with these requirements may result in revocation of the FCC approval and removal of the host products from the market. These requirements correspond to questions featured in the FCC guidance for software security requirements for U-NII devices, FCC OET KDB 594280 D02 [23].
The modular transmitter approval of MAYA-W4, or any other radio module, does not exempt the
end product from being evaluated against applicable regulatory demands.
The evaluation of the end product shall be performed with the MAYA-W4 module installed and operating in a way that reflects the intended end product use case. The upper frequency measurement range of the end product evaluation is the 10th harmonic of 5.8 GHz as described in KDB 996369 D04.
15 2000/299/EC: Commission Decision of 6 April 2000 establishing the initial classification of radio equipment and telecommunications terminal equipment and associated identifiers.
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The following requirements apply to all products that integrate a radio module:
· Subpart B UNINTENTIONAL RADIATORS To verify that the composite device of host and module comply with the requirements of FCC part 15B, the integrator shall perform sufficient measurements using ANSI 63.4-2014.
· Subpart C INTENTIONAL RADIATORS It is required that the inte
Documents / Resources
 |
ublox MAYA-W4 Series Host Based Multiradio Modules [pdf] Instruction Manual MAYA-W471-00B-00, MAYA-W473-00B-00, MAYA-W476-00B-00, MAYA-W472-00B-00, MAYA-W436-00B-00, MAYA-W442-00B-00, MAYA-W463-00B-00, MAYA-W466-00B-00, MAYA-W433-00B-00, MAYA-W4 Series Host Based Multiradio Modules, MAYA-W4 Series, Host Based Multiradio Modules, Based Multiradio Modules, Multiradio Modules, Modules |