25G àjọlò Intel® FPGA IP Awọn akọsilẹ Tu
Itọsọna olumulo
Awọn akọsilẹ itusilẹ 25G Ethernet Intel FPGA IP (Awọn ẹrọ Intel Agilex)
Awọn ẹya Intel® FPGA IP ibaamu awọn ẹya sọfitiwia Intel Quartus® Prime Design Suite titi di v19.1. Bibẹrẹ ni Intel Quartus Prime Design Suite sọfitiwia ẹya 19.2, Intel FPGA IP ni ero ti ikede tuntun kan.
Nọmba Intel FPGA IP ẹya (XYZ) le yipada pẹlu ẹya sọfitiwia Intel Quartus Prime kọọkan. Iyipada ninu:
- X tọkasi atunyẹwo pataki ti IP. Ti o ba ṣe imudojuiwọn sọfitiwia Intel Quartus Prime, o gbọdọ tun IP ṣe.
- Y tọkasi IP pẹlu awọn ẹya tuntun. Tun IP rẹ ṣe lati ni awọn ẹya tuntun wọnyi.
- Z tọkasi IP pẹlu awọn ayipada kekere. Tun IP rẹ ṣe lati fi awọn ayipada wọnyi kun.
1.1. 25G àjọlò Intel FPGA IP v1.0.0
Table 1. v1.0.0 2022.09.26
| Intel Quartus NOMBA Version | Apejuwe | Ipa |
| 22.3 | Atilẹyin ti a ṣafikun fun ẹbi ohun elo Intel Agilex™ F-tile. • Iwọn iyara 25G nikan ni atilẹyin. • Ilana Aago konge 1588 ko ni atilẹyin. |
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Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn ami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
ISO
9001:2015
Iforukọsilẹ
Awọn akọsilẹ itusilẹ 25G Ethernet Intel FPGA IP (Awọn ẹrọ Intel Stratix 10)
Ti akọsilẹ itusilẹ ko ba wa fun ẹya IP kan pato, IP ko ni awọn ayipada ninu ẹya yẹn. Fun alaye lori awọn idasilẹ IP imudojuiwọn to v18.1, tọka si Intel Quartus Prime Design Suite Awọn akọsilẹ Tu silẹ.
Awọn ẹya Intel FPGA IP ibaamu awọn ẹya sọfitiwia Intel Quartus Prime Design Suite titi di v19.1. Bibẹrẹ ni Intel Quartus Prime Design Suite software version 19.2, Intel
FPGA IP ni ero ti ikede tuntun kan.
Nọmba Intel FPGA IP ẹya (XYZ) le yipada pẹlu ẹya sọfitiwia Intel Quartus Prime kọọkan. Iyipada ninu:
- X tọkasi atunyẹwo pataki ti IP. Ti o ba ṣe imudojuiwọn sọfitiwia Intel Quartus Prime, o gbọdọ tun IP ṣe.
- Y tọkasi IP pẹlu awọn ẹya tuntun. Tun IP rẹ ṣe lati ni awọn ẹya tuntun wọnyi.
- Z tọkasi IP pẹlu awọn ayipada kekere. Tun IP rẹ ṣe lati fi awọn ayipada wọnyi kun.
Alaye ti o jọmọ
- Intel Quartus Prime Design Suite Update Tu Awọn akọsilẹ
- 25G àjọlò Intel Stratix®10 FPGA IP Itọsọna olumulo Archives
- 25G àjọlò Intel Stratix® 10 FPGA IP Design Eksample User Itọsọna Archives
- Errata fun 25G Ethernet Intel FPGA IP ni Ipilẹ Imọ
2.1. 25G àjọlò Intel FPGA IP v19.4.1
Table 2. v19.4.1 2020.12.14
| Intel Quartus NOMBA Version | Apejuwe | Ipa |
| 20.4 | Imudojuiwọn gigun lori awọn fireemu VLAN: Ni awọn ẹya ti tẹlẹ ti 25G Ethernet Intel FPGA IP, aṣiṣe fireemu ti o tobi ju ni a sọ nigbati awọn ipo atẹle ba pade: 1. VLAN a. Wiwa VLAN ti ṣiṣẹ. b. IP naa n gbe/gba awọn fireemu pẹlu ipari ti o jẹ iwọn ipari TX/RX ti o pọju pẹlu 1 si 4 octets. 2. SVLAN a. Wiwa SVLAN ti ṣiṣẹ. b. IP naa n gbe/gba awọn fireemu pẹlu ipari ti o jẹ iwọn ipari TX/RX ti o pọju pẹlu 1 si 8 octets. • Ninu ẹya yii, IP ti ni imudojuiwọn lati ṣe atunṣe ihuwasi yii. |
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| Ṣe imudojuiwọn Avalon® ni wiwo ti a ṣe aworan iranti ni wiwo si wiwo ipo_* lati ṣe idiwọ akoko akoko iranti Avalon lakoko kika si awọn adirẹsi ti ko si: Ni awọn ẹya ti tẹlẹ ti 25G Ethernet Intel FPGA IP, Avalon iranti-mapped ni wiwo ka si awọn adirẹsi ti ko si tẹlẹ lori ni wiwo status_* yoo sọ ipo_waitrequest titi ti Avalon memorimapped oluwa beere awọn akoko jade. Ọrọ naa ti ni atunṣe ni bayi lati ma ṣe idaduro ibeere idaduro nigbati adirẹsi ti ko si tẹlẹ ti wọle. |
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| Awọn iyatọ ti o ṣiṣẹ RS-FEC ṣe atilẹyin igbejade 100% bayi. | - |
2.2. 25G àjọlò Intel FPGA IP v19.4.0
Table 3. v19.4.0 2019.12.16
| Intel Quartus NOMBA Version | Apejuwe | Ipa |
| 19.4 | Iyipada ihuwasi rx_am_lock: Ni awọn ẹya ti tẹlẹ ti 25G Ethernet Intel FPGA IP, ifihan agbara rx_am_lock huwa kanna bii rx_block_lock ni gbogbo awọn iyatọ. Ninu ẹya yii, fun awọn iyatọ IP ti RSFEC ti mu ṣiṣẹ, rx_am_lock n sọ ni bayi nigbati titiipa titete ba waye. Fun awọn iyatọ ti kii ṣe RSFEC ṣiṣẹ, rx_am_lock tun ṣe ihuwasi kanna bii rx_block_lock. |
Ifihan wiwo wiwo, rx_am_lock, huwa yatọ si awọn ẹya ti tẹlẹ fun awọn iyatọ RSFEC-ṣiṣẹ. |
| Ti ṣe imudojuiwọn Ibẹrẹ RX MAC ti Packet: Ni awọn ẹya ti tẹlẹ, RX MAC n ṣayẹwo fun ohun kikọ START lati pinnu ibẹrẹ ti apo. • Ninu ẹya yii, RX MAC n ṣayẹwo bayi fun awọn apo-iwe ti nwọle fun Ibẹrẹ Delimiter Frame (SFD), ni afikun si kikọ START nipasẹ aiyipada. • Ti o ba ti mu ipo-iṣaaju-iṣaaju ṣiṣẹ, MAC ṣayẹwo nikan fun ohun kikọ START lati gba laaye fun iṣaju aṣa. |
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| Ṣafikun iforukọsilẹ tuntun lati jẹ ki iṣayẹwo iṣaaju ṣiṣẹ: • Ninu awọn iforukọsilẹ RX MAC, iforukọsilẹ ni aiṣedeede 0x50A [4] ni a le kọ si 1 lati jẹki iṣayẹwo iṣaaju. Iforukọsilẹ yii jẹ “maṣe bikita” nigbati iṣaju iṣaju ti ṣiṣẹ. |
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2.3. 25G àjọlò Intel FPGA IP v19.3.0
Table 4. v19.3.0 2019.09.30
| Intel Quartus NOMBA Version | Apejuwe | Ipa |
| 19.3 | Fun iyatọ MAC + PCS + PMA, orukọ module wrapper transceiver ti wa ni ipilẹṣẹ ni agbara. Eyi ṣe idiwọ ikọlu module ti aifẹ ti ọpọlọpọ awọn iṣẹlẹ ti IP ba nlo ni eto kan. | - |
2.4. 25G àjọlò Intel FPGA IP v19.2.0
Table 5. v19.2.0 2019.07.01
| Intel Quartus NOMBA Version | Apejuwe | Ipa |
| 19.2 | Apẹrẹ Exampfun 25G Ethernet Intel FPGA IP: • Ti ṣe imudojuiwọn aṣayan ohun elo idagbasoke ibi-afẹde fun Intel Stratix® 10 awọn ẹrọ lati Intel Stratix 10 L-Tile GX Transceiver Signal Integrity Development Kit si Intel Stratix 10 10 GX Integrity Signal L-Tile (Igbejade) Idagbasoke Apo. |
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2.5. 25G àjọlò Intel FPGA IP v19.1
Table 6. v19.1 Kẹrin 2019
| Apejuwe | Ipa |
| Ṣafikun ẹya tuntun kan—Ipo adaṣe fun Iṣatunṣe RX PMA: Fi paramita tuntun kun-Ṣiṣe adaṣe adaṣe adaṣe fun ipo RX PMA CTLE/DFE. |
Awọn ayipada wọnyi jẹ iyan. Ti o ko ba ṣe igbesoke ipilẹ IP rẹ, ko ni ẹya tuntun yii. |
| Fun lorukọmii paramita Mu Altera Debug Master Endpoint (ADME) ṣiṣẹ lati Mu Abinibi PHY Debug Master Endpoint (NPDME) ṣiṣẹ gẹgẹbi fun isọdọtun Intel ninu sọfitiwia Intel Quartus Prime Pro Edition. Sọfitiwia Ipele Ipele Intel Quartus Prime tun nlo Mu Altera Debug Master Endpoint ṣiṣẹ (ADME). | - |
2.6. 25G àjọlò Intel FPGA IP v18.1
Table 7. Version 18.1 Kẹsán 2018
| Apejuwe | Ipa |
| Ṣafikun ẹya tuntun kan—PMA Ayanfẹ: Fikun paramita tuntun kan—Awọn iyatọ koko. |
Awọn ayipada wọnyi jẹ iyan. Ti o ko ba ṣe igbesoke ipilẹ IP rẹ, ko ni awọn ẹya tuntun wọnyi. |
| Fi ami ifihan titun kun fun 1588 Precision Time Protocol Interface—latency_sclk. | |
| Apẹrẹ Exampfun 25G Ethernet Intel FPGA IP: Ti lorukọmii aṣayan kit idagbasoke ibi-afẹde fun awọn ẹrọ Intel Stratix 10 lati Stratix 10 GX FPGA Apo Idagbasoke si Stratix 10 L-Tile GX Apo Idagbasoke Iṣeduro Iṣeduro Iṣipopada. |
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Alaye ti o jọmọ
- 25G àjọlò Intel Stratix 10 FPGA IP Itọsọna olumulo
- 25G àjọlò Intel Stratix 10 FPGA IP Design Eksample User Itọsọna
- Errata fun 25G Ethernet IP mojuto ni Ipilẹ Imọ
2.7. 25G àjọlò Intel FPGA IP v18.0
Table 8. Ẹya 18.0 May 2018
| Apejuwe | Ipa |
| Itusilẹ akọkọ fun awọn ẹrọ Intel Stratix 10. | - |
2.8. 25G àjọlò Intel Stratix 10 FPGA IP Itọsọna olumulo Archives
Awọn ẹya IP jẹ kanna bi awọn ẹya sọfitiwia Intel Quartus Prime Design Suite to v19.1. Lati Intel Quartus Prime Design Suite sọfitiwia ẹya 19.2 tabi nigbamii, awọn ohun kohun IP ni ero ikede IP tuntun kan.
Ti ẹya IP mojuto ko ba ṣe akojọ, itọsọna olumulo fun ẹya IP mojuto ti tẹlẹ kan.
| Intel Quartus NOMBA Version | IP Core Version | Itọsọna olumulo |
| 20.3 | 19.4.0 | 25G àjọlò Intel Stratix 10 FPGA IP Itọsọna olumulo |
| 20.1 | 19.4.0 | 25G àjọlò Intel Stratix 10 FPGA IP Itọsọna olumulo |
| 19.4 | 19.4.0 | 25G àjọlò Intel Stratix 10 FPGA IP Itọsọna olumulo |
| 19.3 | 19.3.0 | 25G àjọlò Intel Stratix 10 FPGA IP Itọsọna olumulo |
| 19.2 | 19.2.0 | 25G àjọlò Intel Stratix 10 FPGA IP Itọsọna olumulo |
| 19.1 | 19.1 | 25G àjọlò Intel Stratix 10 FPGA IP Itọsọna olumulo |
| 18.1 | 18.1 | 25G àjọlò Intel Stratix 10 FPGA IP Itọsọna olumulo |
| 18.0 | 18.0 | 25G àjọlò Intel Stratix 10 FPGA IP Itọsọna olumulo |
2.9. 25G àjọlò Intel Stratix 10 FPGA IP Design Eksample User Itọsọna Archives
Awọn ẹya IP jẹ kanna bi awọn ẹya sọfitiwia Intel Quartus Prime Design Suite to v19.1. Lati Intel Quartus Prime Design Suite sọfitiwia ẹya 19.2 tabi nigbamii, awọn ohun kohun IP ni ero ikede IP tuntun kan.
Ti ẹya IP mojuto ko ba ṣe akojọ, itọsọna olumulo fun ẹya IP mojuto ti tẹlẹ kan.
| Intel Quartus NOMBA Version | IP Core Version | Itọsọna olumulo |
| 19.1 | 19.1 | 25G àjọlò Intel Stratix 10 FPGA IP Design Eksample User Itọsọna |
| 18.1 | 18.1 | 25G àjọlò Intel Stratix 10 FPGA IP Design Eksample User Itọsọna |
| 18.0 | 18.0 | 25G àjọlò Intel Stratix 10 FPGA IP Design Eksample User Itọsọna |
Awọn akọsilẹ itusilẹ 25G Ethernet Intel FPGA IP (Awọn ẹrọ Intel Arria 10)
Ti akọsilẹ itusilẹ ko ba wa fun ẹya IP kan pato, IP ko ni awọn ayipada ninu ẹya yẹn. Fun alaye lori awọn idasilẹ IP imudojuiwọn to v18.1, tọka si Intel Quartus Prime Design Suite Awọn akọsilẹ Tu silẹ.
Awọn ẹya Intel FPGA IP ibaamu awọn ẹya sọfitiwia Intel Quartus Prime Design Suite titi di v19.1. Bibẹrẹ ni Intel Quartus Prime Design Suite sọfitiwia ẹya 19.2, Intel FPGA IP ni ero ti ikede tuntun kan.
Nọmba Intel FPGA IP ẹya (XYZ) le yipada pẹlu ẹya sọfitiwia Intel Quartus Prime kọọkan. Iyipada ninu:
- X tọkasi atunyẹwo pataki ti IP. Ti o ba ṣe imudojuiwọn sọfitiwia Intel Quartus Prime, o gbọdọ tun IP ṣe.
- Y tọkasi IP pẹlu awọn ẹya tuntun. Tun IP rẹ ṣe lati ni awọn ẹya tuntun wọnyi.
- Z tọkasi IP pẹlu awọn ayipada kekere. Tun IP rẹ ṣe lati fi awọn ayipada wọnyi kun.
Alaye ti o jọmọ
- Intel Quartus Prime Design Suite Update Tu Awọn akọsilẹ
- 25G àjọlò Intel Arria® 10 FPGA IP Itọsọna olumulo
- 25G àjọlò Intel Arria® 10 FPGA IP Design Eksample User Itọsọna
- Errata fun 25G Ethernet Intel FPGA IP ni Ipilẹ Imọ
3.1. 25G àjọlò Intel FPGA IP v19.4.1
Table 9. v19.4.1 2020.12.14
| Intel Quartus Ẹya akọkọ | Apejuwe | Ipa |
| 20.4 | Imudojuiwọn gigun lori awọn fireemu VLAN: Ni awọn ẹya ti tẹlẹ ti 25G Ethernet Intel FPGA IP, aṣiṣe fireemu ti o tobi ju ni a sọ nigbati awọn ipo atẹle ba pade: 1. VLAN a. Wiwa VLAN ti ṣiṣẹ. b. IP naa n gbe/gba awọn fireemu pẹlu ipari ti o jẹ iwọn ipari TX/RX ti o pọju pẹlu 1 si 4 octets. 2. SVLAN a. Wiwa SVLAN ti ṣiṣẹ. b. IP naa n gbe/gba awọn fireemu pẹlu ipari ti o jẹ iwọn ipari TX/RX ti o pọju pẹlu 1 si 8 octets. • Ninu ẹya yii, IP ti ni imudojuiwọn lati ṣe atunṣe ihuwasi yii. |
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| Ṣe imudojuiwọn iraye si wiwo ti a ṣe aworan iranti Avalon si wiwo ipo_* lati ṣe idiwọ akoko akoko iranti Avalon lakoko kika si awọn adirẹsi ti ko si: • IP ti ni imudojuiwọn lati mu ibeere idaduro duro nigbati adirẹsi ti ko si tẹlẹ ti wọle si ipo_* ni wiwo. |
3.2. 25G àjọlò Intel FPGA IP v19.4.0
Table 10. v19.4.0 2019.12.16
| Intel Quartus NOMBA Version | Apejuwe | Ipa |
| 19.4 | Iyipada ihuwasi rx_am_lock: Ni awọn ẹya ti tẹlẹ ti 25G Ethernet Intel FPGA IP, ifihan agbara rx_am_lock huwa kanna bii rx_block_lock ni gbogbo awọn iyatọ. Ninu ẹya yii, fun awọn iyatọ IP ti RSFEC ti mu ṣiṣẹ, rx_am_lock n sọ ni bayi nigbati titiipa titete ba waye. Fun awọn iyatọ ti kii ṣe RSFEC ṣiṣẹ, rx_am_lock tun ṣe ihuwasi kanna bii rx_block_lock. |
Ifihan wiwo wiwo, rx_am_lock, huwa yatọ si awọn ẹya ti tẹlẹ fun awọn iyatọ RSFEC-ṣiṣẹ. |
| Ti ṣe imudojuiwọn Ibẹrẹ RX MAC ti Packet: Ni awọn ẹya ti tẹlẹ, RX MAC n ṣayẹwo fun ohun kikọ START lati pinnu ibẹrẹ ti apo. • Ninu ẹya yii, RX MAC n ṣayẹwo bayi fun awọn apo-iwe ti nwọle fun Ibẹrẹ Delimiter Frame (SFD), ni afikun si kikọ START nipasẹ aiyipada. • Ti o ba ti mu ipo-iṣaaju-iṣaaju ṣiṣẹ, MAC ṣayẹwo nikan fun ohun kikọ START lati gba laaye fun iṣaju aṣa. |
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| Ṣafikun iforukọsilẹ tuntun lati jẹ ki iṣayẹwo iṣaaju ṣiṣẹ: • Ninu awọn iforukọsilẹ RX MAC, iforukọsilẹ ni aiṣedeede 0x50A [4] ni a le kọ si 1 lati jẹki iṣayẹwo iṣaaju. Iforukọsilẹ yii jẹ “maṣe bikita” nigbati iṣaju iṣaju ti ṣiṣẹ. |
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3.3. 25G àjọlò Intel FPGA IP v19.1
Table 11. v19.1 Kẹrin 2019
| Apejuwe | Ipa |
| Fun lorukọmii paramita Mu Altera Debug Master Endpoint (ADME) ṣiṣẹ lati Mu Abinibi PHY Debug Master Endpoint (NPDME) ṣiṣẹ gẹgẹbi fun isọdọtun Intel ninu sọfitiwia Intel Quartus Prime Pro Edition. Sọfitiwia Ipele Ipele Intel Quartus Prime tun nlo Mu Altera Debug Master Endpoint ṣiṣẹ (ADME). | - |
3.4. 25G àjọlò IP mojuto v17.0
Table 12. Ẹya 17.0 May 2017
| Apejuwe | Ipa |
| Awọn ẹya ojiji ti a ṣafikun fun awọn iforukọsilẹ awọn iṣiro kika. • Ninu awọn iforukọsilẹ awọn iṣiro TX, rọpo iforukọsilẹ CLEAR_TX_STATS ni aiṣedeede 0x845 pẹlu iforukọsilẹ CNTR_TX_CONFIG tuntun. Iforukọsilẹ tuntun ṣe afikun ibeere ojiji kan ati aṣiṣe-aṣiṣe-iṣiro diẹ si bit ti o ko gbogbo awọn iforukọsilẹ awọn iṣiro TX kuro. Ṣafikun iforukọsilẹ CNTR_RX_STATUS tuntun ni aiṣedeede 0x846, eyiti o pẹlu diẹ ninu aṣiṣe-aṣiṣe ati ipo diẹ fun ibeere ojiji. Ninu awọn iforukọsilẹ awọn iṣiro RX, rọpo iforukọsilẹ CLEAR_RX_STATS ni aiṣedeede 0x945 pẹlu iforukọsilẹ CNTR_RX_CONFIG tuntun. Iforukọsilẹ tuntun ṣe afikun ibeere ojiji kan ati aṣiṣe-aṣiṣe-aṣiṣe ko o bit si bit. ti o ko gbogbo TX statistiki forukọsilẹ. Ṣafikun iforukọsilẹ CNTR_TX_STATUS tuntun ni aiṣedeede 0x946, eyiti o pẹlu Aṣiṣe-aṣiṣe-bit ati ipo ipo kan fun ibeere ojiji. |
Ẹya tuntun naa ṣe atilẹyin igbẹkẹle ilọsiwaju ninu awọn kika kika awọn iṣiro. Lati ka iṣiro iṣiro kan, kọkọ ṣeto iwọn ibeere ojiji fun ṣeto awọn iforukọsilẹ (RX tabi TX), ati lẹhinna ka lati aworan iforukọsilẹ. Awọn iye kika da duro jijẹ lakoko ti ẹya ojiji wa ni ipa, ṣugbọn awọn iṣiro abẹlẹ tẹsiwaju lati pọsi. Lẹhin ti o tun ibere naa tunto, awọn iṣiro tun bẹrẹ awọn iye akojo wọn. Ni afikun, awọn aaye iforukọsilẹ tuntun pẹlu ipo aiṣedeede ati awọn ipin mimọ. |
| Ayipada RS-FEC tito ami isamisi lati ni ibamu pẹlu Abala 108 ti o ti pari ni bayi ti IEEE 802.3by sipesifikesonu. Ni iṣaaju ẹya RS-FEC ṣe ibamu pẹlu Eto Iṣeto Iṣọkan 25G/50G, ṣaaju IEEE ipari sipesifikesonu. |
RX RS-FEC n ṣe awari ati tiipa si mejeeji ti atijọ ati awọn ami isọdi tuntun, ṣugbọn TX RS-FEC n ṣe agbekalẹ kika ami isọdọtun IEEE tuntun nikan. |
Alaye ti o jọmọ
- 25G àjọlò IP mojuto User Itọsọna
- Errata fun 25G Ethernet IP mojuto ni Ipilẹ Imọ
3.5. 25G àjọlò IP mojuto v16.1
Table 13. Version 16.1 October 2016
| Apejuwe | Ipa |
| Itusilẹ akọkọ ni ile-ikawe IP Intel FPGA. | - |
Alaye ti o jọmọ
- 25G àjọlò IP mojuto User Itọsọna
- Errata fun 25G Ethernet IP mojuto ni Ipilẹ Imọ
3.6. 25G àjọlò Intel Arria® 10 FPGA IP Itọsọna olumulo Archive
Awọn ẹya IP jẹ kanna bi awọn ẹya sọfitiwia Intel Quartus Prime Design Suite to v19.1. Lati Intel Quartus Prime Design Suite sọfitiwia ẹya 19.2 tabi nigbamii, awọn ohun kohun IP ni ero ikede IP tuntun kan.
Ti ẹya IP mojuto ko ba ṣe akojọ, itọsọna olumulo fun ẹya IP mojuto ti tẹlẹ kan.
| Intel Quartus NOMBA Version | Ẹya IP | Itọsọna olumulo |
| 20.3 | 19.4.0 | 25G àjọlò Intel Arria® 10 FPGA IP Itọsọna olumulo |
| 19.4 | 19.4.0 | 25G àjọlò Intel Arria 10 FPGA IP Itọsọna olumulo |
| 17.0 | 17.0 | 25G àjọlò Intel Arria 10 FPGA IP Itọsọna olumulo |
3.7. 25G àjọlò Intel Arria 10 FPGA IP Design Eksample User Archives Itọsọna
Awọn ẹya IP jẹ kanna bi awọn ẹya sọfitiwia Intel Quartus Prime Design Suite to v19.1. Lati Intel Quartus Prime Design Suite sọfitiwia ẹya 19.2 tabi nigbamii, awọn ohun kohun IP ni ero ikede IP tuntun kan.
Ti ẹya IP mojuto ko ba ṣe akojọ, itọsọna olumulo fun ẹya IP mojuto ti tẹlẹ kan.
| Intel Quartus NOMBA Version | IP Core Version | Itọsọna olumulo |
| 16.1 | 16.1 | 25G àjọlò Design Example User Itọsọna |
25G àjọlò Intel® FPGA IP Awọn akọsilẹ Tu
Idajọ Ayelujara
Fi esi ranṣẹ
ID: 683067
Ẹya: 2022.09.26
Awọn iwe aṣẹ / Awọn orisun
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intel 25G àjọlò Intel FPGA IP [pdf] Itọsọna olumulo 25G Ethernet Intel FPGA IP, Ethernet Intel FPGA IP, Intel FPGA IP, FPGA IP, IP |