Topway Display LMT035DNJFWD-1 LCD Module User Manual

The LMT035DNJFWD-1 is an LCD module that provides high-quality display technology with a screen size of 3.5 inches (diagonal). The module has a color depth of up to 262K colors and a resolution of 320×240 pixels. The active area of the module is 70.08mm x 52.56mm, and the dot pitch is 0.219mm x 0.219mm. The display mode is transmissive, and the pixel configuration is RGB vertical stripe.
The viewing direction is 6 o’clock, and the polarizer surface treatment is anti-glare. The backlight type used in this module is a white LED backlight. The outline dimension of the module is 76.9mm x 63.9mm x 3.2mm (max).

Product Usage Instructions

To use the LMT035DNJFWD-1 LCD module, please follow these instructions:

Basic Specifications

Scree n Size(Diagonal) : 3.5”
Color Depth: 65K/262K Color

Number of dots : 320(RGB)x480
Active Area : 48.96×73.44mm

Dot Pitch : 0.153×0.153mm
Display Technology : a-Si TFT active matrix

Display Mode : Transmissive With Normally white
Pixel Configuration : RGB Vertical Stripe

Viewing Direction : 12H (*1) (gray scale inverse) 6H (*2)
Polarizer Surface Treatment: HC

Backlight Type: LEDs
Outline Dimension : 55.26x 84.69 x 2.2 mm (exclude FPC , see dwg for details)

Operating Temperature : – 20 ~ +70°C (No Condensation)
Storage Temperature : – 30 ~ +80°C (No Condensation)

Note:

For saturated color display content (eg. pure-red, pure-green, pure-blue or pure-colors-combinations).

For “color scales” display content.
Color tone may slightly change by temperature and driving condition.

Block Diagram

Terminal Functions

Pin No.	PIN Name	I/O	Descriptions
1	VSS	Power	Negative power supply,0V
2,3	IOVDD	Power	IO Positive Power
4,5	VDD	Power	Positive power supply
6	IM0	Input	MPU system interface mode select
7	IM1	Input	MPU system interface mode select
8	IM2	Input	MPU system interface mode select
9	RESX	Input	Reset signal RESX = L, Initialization is executed RESX = H, Normal running.
10	VSYNC	Input	Vertical sync. signal in RGB mode If no used, please connect this pin to VSS
11	HSYNC	Input	Horizontal sync, signal in RGB mode If no used, please connect this pin to VSS
12	PCLK	Input	Pixel clock signal in RGB mode If no used, please connect this pin to VSS
13	DE	Output	Data enable signal in RGB mode If no used, please fix this pin at VSS level
14	DB17/R5,Msb	I/O	Data Bus
15	DB16/R4	I/O
:	:	:
18	DB13/R1	I/O
19	DB12/R0,Lsb	I/O
20	DB11/G5,Msb	I/O
21	DB10/G4	I/O
:	:	:
24	DB7/G1	I/O
25	DB6/G0,Lsb	I/O
26	DB5/B5,Msb	I/O
27	DB4/B4	I/O
:	:	:
30	DB1/B1	I/O
31	DB0/B0,Lsb	I/O
32	VSS	Power	Negative power supply,0V
33	DOUT	Output	Serial data output pin If no used, leave this pin open
34	SDA	I/O	serial data input /output bi-direction pin
35	RDX	Input	serve as a read signal
36	WRX_SCL	Input	(WR) Write data enable pin in DBI Type B (SCL) Write data enable pin in DBI Type C If no used, please connect this pin to IOVDD
37	DCX	Input	Data/Command Selection pin Low: Command High: Parameter
38	CSX	Input	Chip select signal If no used, please connect this pin to IOVDD
39	NC(XR)	–
40	NC(YD)		No connect
41	NC(XL)		No connect
42	NC(YU)
43	LEDA	Power	LED ANODE
44~49	LEDK	Power	LEDK CATHODE
50	VSS	Power	Negative power supply,0V

Absolute Maximum Ratings

Items	Symbol	Min.	Max.	Unit	Condition
Power Voltage	VDD	-0.3	+3.6	V	VSS = 0V
Input Voltage	VIN	-0.3	+3.6	V	VSS = 0V
Operating Temperature	TOP	-20	+70	°C	No Condensation
Storage Temperature	TST	-30	+80	°C	No Condensation

Cautions:
Any Stresses exceeding the Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

Electrical Characteristics

DC Characteristics

Items	Symbo l	MIN.	TYP.	MAX.	Unit	Condition / Application Pin
Operating Voltage	VDD	2.65	3.0	3.6	V	VDD,IOVDD
Input High Voltage	VIH	0.7xVDD	–	VDD	V	IM0~IM2,RESX,VSYNC,HSY NC,PCLK,DB17/R5,Msb, DB16/R4~DB13/R1 ,DB12/R0,Lsb,DB11/G5,Msb, DB10/G4~DB7/G1 ,DB6/G0,Lsb,DB5/B5,Msb, DB4/B4~DB1/B1,DB0/B0,Lsb, SDA,RDX,WRX_SCL,DCX, CSX,
Input Low Voltage	VIL	-0.3	–	0.3xVDD	V
Output Low Voltage	VOL	0	–	0.99	V	DB17/R5,Msb, DB16/R4~DB13/R1 ,DB12/R0,Lsb,DB11/G5,Msb, DB10/G4~DB7/G1 ,DB6/G0,Lsb,DB5/B5,Msb, DB4/B4~DB1/B1,DB0/B0,Lsb, DE,SDA,DOUT
Operating Current	IDD	–	8	–	mA	VDD (*1)

Note: *1. VDD=3.0V

LED Backlight Circuit Characteristics

Items	Symbol	MIN.	TYP.	MAX.	Unit	Remark
Forward Voltage	Vf	–	3.2	–	V	For each LED
Forward Current	If	–	20	–	mA	For each LED
LED lifetime	–	–	30000	–	Hours

Note1:LED CIRCUIT DIAGRAM
Note 2:LED: VF =3.2V, IF =20mA(TYP)
Note 3:IF is defined for one LED.
Optical performance should be evaluated at Ta=25℃ only.
If LED is driven by high current, high ambient temperature & humidity condition.
The life time of LED will be reduced. Operating life means brightness goes down to 50% initial brightness.
Typical operating life time is estimated data.
Note 4:Under LCM operating, the stable forward current should be inputted. And forward voltage is for reference only.

AC Characteristics

DBI Type B

DBI Type B Timing Characteristic

DBI Type B Data Bus
8-bit Data Bus for 16-bit/pixel (RGB 5-6-5 Bits Input), 65K-color
8-bit Data Bus for 18-bit/pixel (RGB 6-6-6Bits Input), 262 K-color

9-bit Data Bus for 18-bit/pixel (RGB 6-6-6Bits Input), 262 K-color
16-bit Data Bus for 16-bit/pixel (RGB 5-6-5 Bits Input), 65K-color
16-bit Data Bus for 18-bit/pixel (RGB 6-6-6Bits Input), 262 K-color
18-bit Data Bus for 18-bit/pixel (RGB 6-6-6Bits Input), 262 K-color

3-Line SPI Interface Timing Characteristic

4-Line SPI Interface Timing Characteristic

Note:Ta=-30 to 70℃，IOVDD，VDD=2.5V to 3.3V，VSS=0V，T=10+/-0.5ns. Please refer to IC: ILI9488 data sheet for more details.

DPI Interface

DPI Interface Characteristic
DPI Interface pixel format

The Pixel clock (DCLK) runs all the time without stop. It is used to enter VS, HS, DE and D[17: 0] states when there is a rising edge of the DCLK. The DCLK cannot be used as the internal clock for other functions of the display module.
Vertical synchronization (VS) is used to indicate when a new frame of the display is received. This is low enable and its state is read to the display module by a rising edge of the DCLK signal.
Horizontal synchronization (HS) IS used to indicate when a new line of the frame is received. This is low enable and its state is read to the display module by a rising edge of the DCLK signal.
Data Enable (DE) is used to indicate when the RGB information that should be transferred in the display is received. This is a high enable, and its state is read to the display module by a rising edge of the DCLK signal. D[17:0] is used to indicate what is the information of the image that is transferred on the display (when DE = 0 (low) and there is a rising edge of DCLK). D[17:0] can be 0(low) or 1(high). These lines are read by a rising edge of the DCLK signal. In RGB interface modes, the input display data is written to GRAM first then outputs the corresponding source voltage according to the gray data from GRAM.
Note：Please refer to IC: ILI9488 data sheet for more details.
DPI(RGB) Interface timing

Power ON/OFF Sequence

Notes:

There are not any abnormal visual effects when one power mode changes to another power mode.
There is not any limitation, which is not specified by users, when one power mode changes to another power mode.

IOVDD and VDD can be applied or powered down in any order. During the Power Off sequence ,if the LCD is in the Sleep In mode, VDD and IOVDD must be powered down with a minimum of 120 msec.If the LCD is in the Sleep In mode, VDD and IOVDD can be powered down with a minimum of 0msec after the /RST has been released. /CS can be applied at any time or can be permanently grounded. /RST has priority over /CS.
Notes:

There will be no damage to the ILI9488 if the power sequences are not met.
There will be no abnormal visible effects on the display panel during the Power On/Off Sequence.
There will be no abnormal visible effects on the display between the end of the Power On Sequence and before receiving the Sleep Out command, and also between receiving the Sleep In command and the Power Off Sequence.
If the /RST line is not steadily held by the host during the Power On Sequence as defined in Sections 11.1 and 11.2 ( ILI9488 datasheet ), then it will be necessary to apply the Hardware /RST after the completion of the Host Power On Sequence to ensure correct operations. Otherwise, all the functions are not guaranteed.
When the power is turned on, the climb period timing (Trise) must be greater than 10us.
Keep data pins D[17:0] at low level, or IOVDD comes later

Reset timing

Item	Symbol	MIN.	TYP.	MAX.	Unit
Reset LOW pulse width	tRW	1.0	–	–	us
Reset time	TRT	–	–	120	ms

Note：Please refer to IC: ILI9488 data sheet for more details.

Optical Characteristics

Note 1: Detinition ot optical measurement system.
The optical characteristics should be measured in dark room. After 5 Minutes operation, the optical properties are measured at the center point of the LCD screen. All input terminals LCD panel must be ground when measuring the center area of the panel.
Note 2: Definition of viewing angle range and measurement system.
viewing angle is measured at the center point of the LCD by CONOSCOPE(ergo-80).
Note 3: Definition of contrast ratio
“White state”: The state is that the LCD should drive by white.
“Black state”: The state is that the LCD should drive by black.
white: To be determined black: To be determined.
Note 4: Definition of Response time
The response time is defined as the LCD optical switching time interval between “White” state and “Black” state. Rise time (ToN) is the time between photo detector output intensity changed from 90% to 10%. And fall time (Torr) is the time between photo detector output intensity changed from 10% to 90%
Note 5: Definition of color chromaticity (CIE1931)
Color coordinates measured at center point of LCD.
Note 6: Definition of Luminance Uniformity
Active area is divided into 9 measuring areas (Refer Fig. 2). Every measuring point is placed at the center of each measuring area.
Lmax: The measured Maximum luminance of all measurement position.
Lmin: The measured Minimum luminance of all measurement position.
Note 7: Definition of Luminance:
Measure the luminance of white state at center point.

Inspection Condition

Unless otherwise stated，all the inspections are carryout under the following condition

No.	Items	Conditions
1	Lighting	Illumination: Appearance 300-700Lux
2	Inspection Distance	30-40cm form the test sample，within normal viewing angle
3	Temperature	Room Temperature (25 ºC), no condensation
4	Viewing Angle	U/D: 45º/45º, L/R: 45º/45º
5	Inspection Time	15 seconds
6	Defect Allowance	Under 5.0” (include 5.0”): 3 5.0” to 7.0”: 4 Above 7.0”: 6

Display Pattern

No.	Items /Contents	Type			Standard	Judgment
No.	Items /Contents	CR	MA	MI	Standard	Judgment
1	No Display/Unstable Display		√		—	Not Allowed
2	Line defect		√		—	Not Allowed
3	Display abnormally		√		—	Not Allowed
4	Function Defective		√		—	Not Allowed
5	Glass Crack		√		—	Not Allowed
6	Spot Defect Including: Black spot, White spot， Foreign particle, Polarizer dirt, Cell particle			√	Under 5.0” (include 5.0”) 5
					(a+b)/2≤0.15	Allowed
					0.15<(a+b)/2≤0.25	3 max.
					(a+b)/2＞0.25	Not Allowed
					Above 5.0” 5
					(a+b)/2≤0.25	Allowed
					0.25<(a+b)/2≤0.5	3 max.
					(a+b)/2＞0.5	Not Allowed

7	Line Defect Including: Black line, White line, Scratch		√	Under 5.0” (include 5.0”)
				a≤0.03	Allowed
				0.03<a≤0.05 and b≤5.0	2 max.
				a＞0.05 or b＞5.0	Not Allowed
				Above 5.0”
				a≤0.03	Allowed
				0.03<a≤0.05 and b≤5.0	4 max.
				a＞0.05 or b＞5.0	Not Allowed
8	Polarizer Dent/Bubble		√	Under 5.0” (include 5.0”)
				(a+b)/2≤0.25	Allowed
				0.25< (a+b)/2≤0.5	3 max.
				(a+b)/2＞0.5	Not Allowed
				Above 5.0” 5
				(a+b)/2≤0.25	Allowed
				0.25< (a+b)/2≤0.5	3 max.
				(a+b)/2＞0.5	Not Allowed
9	Bright dot defect		√	Under 5.0” (include 5.0”)	0 max.
				5.0” to 7.0”	2 max.
				Above 7.0”	3 max.
				3 consecutive dots	Not Allowed
10	Dark dot defect		√	Under 5.0” (include 5.0”)	2 max.
				5.0” to 7.0”	4 max.
				Above 7.0”	5 max.
				3 consecutive dots	Not Allowed
11	Bright dot defect + Dark dot defect		√	Under 5.0” (include 5.0”)	2 max.
				5.0” to 7.0”	4 max.
				Above 7.0”	5 max.
12	FPC or FFC broken FPC/FFC	√		—	Not Allowed
13	PCBA defect PCBA	√		Refer to IPC-A-610 IPC-A-610	—

Quality Level and Sampling

Items	Standard
Sampling Standard	MIL-STD-105E
Sampling Level	Ⅱ
AQL level	MA: AQL=0.65 MI: AQL=1.0

Handling Precaution

Never attempt to disassemble or rework LCD module

Never let LCD module contact with liquids
LCD module can be easily damaged by electrostatic charge.
Please maintain an optimum anti-static working environment.
LCD panel is made with glass.
Any mechanical shock (eg. Vibration, distortion, extrusion, impact，drop) will damage the LCD module

Avoid showing a display pattern on screen for a long time (continuous ON segment)
The color and evenness of the display may slightly vary with the temperature
Signal and Power supply excess the operation range may damage the LCD module

Avoid touching the LCD surface to prevent any scratch on its surface

Packing Drawing

Per Carton