intel UG-01155 IOPLL FPGA IP Core User Guide
The UG-01155 IOPLL FPGA IP Core User Guide provides detailed instructions on how to configure and use the Intel® FPGA IP Core for Arria® 10 and Cyclone® 10 GX devices. With support for six different clock feedback modes and up to nine clock output signals, this IP core is a versatile tool for FPGA designers. This updated guide for Intel Quartus Prime Design Suite 18.1 also covers PLL dynamic phase shift and adjacent PLL input for PLL cascading mode.