SONY CXQ70116 16 Bit Microprocessor User Guide

The CXQ70116 is a CMOS 16-bit microprocessor with internal and
external 16-bit architecture. It has a powerful instruction set
that includes bit processing, packed BCD operations, and high-speed
multiplication/division operations.

Features

Minimum instruction execution time: 250 ns (at 8 MHz)
2 Mbytes/s data transfer rate (at 8 MHz)

2 clock cycles in any addressing mode

Pin Configuration (Top View)

[Include pin configuration diagram here]

Block Diagram

[Include block diagram here]

Pin Identification

[Include pin identification table here]

Pin Functions

[Include pin functions details here]

FAQ

1. How to connect IC pin?

The IC pin should be connected to ground according to the
manual.

2. What is the clock speed supported by the
microprocessor?

The microprocessor supports a clock speed of up to 8 MHz.

3. Can the CXQ70116 emulate an 8080 processor?

Yes, the CXQ70116 can emulate the functions of an 8080
processor.

“`

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SONY 16-Bit Microprocessor

CXQ70116

Description
The CX070116 is a CMOS 16-bit microprocessor with internal 16-bit architecture and a 16-bit external data bus. The CX070116 instruction set is a superset

Pin Configuration (Top View)

{Small-scale} { Large-scale }

Mode

of the 8086/8088; however, mnemonics and execution

times are different. The CX070116 additionally has a

A014

AD13

powerful instruction set including bit processing,

A012

packed BCD operations, and high-speed multiplication/

AD11

division operations. The CX070116 can also emulate

AD10

the functions of an 8080 and comes with a standby

A09

ADe

mode that significantly reduces power consumption.

AD1

It is software-compatible with the CX070108

A De

microprocessor.

AD,

·oo ADn
A,tlPSo A11/PS1
A1a!PS2 A1t!PS3 UBE S/LG
iiD
HLORQ HLOAK
WR

(AQ/AKoJ
1R01AK,1
(BUSLDCKJ

Features

AD3 AD2

Minimum instruction execution time:

AD1

250 ns (at 8 MHz)

A Do

· Maximum addressable memory: 1 Mbytes

NMI

INT

· Abundant memory addressing modes

CLK

· 14 X 16-bit register set

GND

· 101 instructions

IO/M BUFRtw BUFEN ASTB
INTAK POLL READY RESET

(BS2( (BS1J (BSoJ !OSoJ [OS1)

· Instruction set is a superset of 8086/B088

instruction set

· Bit, byte, word, and block operations

· Bit field operation instructions

· Packed BCD operation instructions

· Multiplication/division instructions execution time:

2.4 µs to 7.1 µs (at 8 MHz)

· High-speed block transfer instructions:

2 Mbytes/s (at 8 MHz)

· High-speed calculation of effective addresses:

2 clock cycles in any addressing mode

· Maskable (INT) and nonmaskable (NMI) interrupt

inputs

· IEEE-796 bus compatible interface

· 8080 emulation functions

· CMOS technology

· Low power consumption

· Standby function

· Single power supply

· 5-MHz or B-MHz clock

· 40-pin Plastic/Ceramic DIP (600 mil)

· NEC µPD70116 (V30) compatible

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CX070116
Block Diagram
a,
LC PC AW
aw cw ow
IX IY BP SP

SONY@

Bus Butter

T-State Control

Status Control

Ull!
BUFEN[BSo], BUFFi/W [8$1] flliM{BSaJ ASTB [OSgJ, INTAK (OS1] iiO, iili {iJlJSl:llCKJ
S/LG READY RESET POLL

Bus Hold Control
lnterrupl Control
~ ~
Effective Address Generator

HLDRO !RO!iKoJ HLDAK [RQ/W,]

~NMI
INT
CLK

Bus Control
Unit [BCU] Execution Unit [EXU]

Microinstruction Storage

Microinstruction

Sub Data Bus (16]

PSW

Main Data Bus [16]

Mlcrosequence Control
lnslruction Decoder

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CX070116

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Pin Identification

No.

Symbol

Direction

Function

IC*

Internally connected

2-16

AD14-ADo

In/Out

Address/ data bus

NMI

Nonmaskable interrupt input

INT

Maskable interrupt input

CLK

Clock input

GND

Ground

RESET

Reset input

READY

Ready input

POLL

Poll input

INTAK (QS1)

Out

Interrupt acknowledge output (queue status bit 1 output)

ASTB (QSo)

Out

Address strobe output (queue status bit 0 output)

BUFEN (BSo)

Out

Buffer enable output (bus status bit 0 output)

BUFR/W (BS1)

Out

Buffer read/write output (bus status bit 1 output)

10/M (BS2)

Out

Access is 1/0 or memory (bus status bit 2 output)

WR (BUSLOCK)

Out

Write strobe output (bus lock output)

HLDAK (RQ/AK1)

Out (In/Out)

Hold acknowledge output, (bus hold request input/ acknowledge output 1)

HLDRQ (RQ/AKo)

Hold request input (bus hold request input/acknowledge

(In/Out)

output 0)

Out

Read strobe output

S/LG

Sma II-scale/large-scale system input

UBE

Out

Upper byte enable

35-38 Ais/PS3-A16/PSo

Out

Address bus, high bits or processor status output

AD15

In/Out

Address/data bus, bit 15

Voo

Power supply

Notes: *IC should be connected to ground. Where pins have different functions in small- and large-scale systems, the large-scale system pin symbol and function are in parentheses. Unused input pins should be tied to ground or Voo to minimize power dissipation and prevent the flow of potentially harmful currents.

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CX070116

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Pin Functions
Some pins of the CXQ70116 have different functions according to whether the microprocessor is used in a small- or large-scale system. Other pins function the same way in either type of system.
AD1s – ADo [Address/Data Bus] For small- and large-scale systems. AD1s – ADo are the time-multiplexed address and data bus. They are active high. This bus contains the
lower 16 bits of the 20-bit address during T1 of the bus cycle. It is used as a 16-bit data bus during T2, T3, and T4 of the bus cycle.
The address/data bus is a three-state bus and can be high or low during standby mode. The bus will float to the high impedance during hold and interrupt acknowledge.
NMI [Nonmaskable Interrupt] For small· and large-scale systems. This pin is used to input nonmaskable interrupt requests. NMI cannot be masked by software. This input
is positive edge-triggered and can be sensed during any clock cycle. Actual interrupt processing begins, however, after completion of the instruction in progress.
The contents of interrupt vector 2 determine the starting address for the interrupt-servicing routine. Note that a hold request will be accepted even during NMI acknowledge.
This interrupt will cause the CXQ70116 to exit the standby mode.
INT [Maskable Interrupt] For small· and large-scale systems. This pin is a level-triggered interrupt request that can be masked by software. INT is active high and is sensed during the last clock of the instruction. The interrupt will be accepted if
the system is in interrupt enable state (if the interrupt enable flag IE is set). The CPU outputs the INTAK signal to inform external devices that the interrupt request has been granted.
If NMI and INT interrupts occur at the same time, NMI has higher priority than INT and INT cannot be accepted. A hold request will be accepted during INT acknowledge.
This interrupt causes the CXQ70116 to exit the standby mode.
CLK [Clock] For small- and large-scale systems. This pin is used for external clock input.
RESET [Reset] For small- and large-scale systems. This pin is used for the CPU reset signal. It is active high. Input of this signal has priority over all other
operations. After the reset signal input returns low, the CPU begins execution of the program starting at address FFFFOH.
In addition to causing normal CPU start, RESET input will cause the CXQ70116 to exit the standby mode.
READY [Ready] For small- and large-scale systems. When the memory or 1/0 device being accessed cannot complete data read or write within the CPU basic
access time, it can generate a CPU wait state (Tw) by setting this signal to inactive (low) and requesting a read/write cycle delay.
If the READY signal is active (high) during either T3 or Tw state, the CPU will not generate a wait state.

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CX070116

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POLL [Poll] For small- and large-scale systems. The CPU checks this input upon execution of the POLL instruction. If the input is low, then execution
continues. If the input is high, the CPU will check the POLL input every five clock cycles until the input becomes low again.
The POLL and READY functions are used to synchronize CPU program execution with the operation of external devices.

RD [Read Strobe] For small- and large-scale systems. The CPU outputs this strobe signal during data read from an 1/0 device or memory. The 16/M signal is
used to select between 1/0 and memory. RD will be high during standby mode. It is three-state and floats to the high impedance during hold acknowledge.

S/LG [Small/Large]

For small- and large-scale systems.

This signal determines the operation mode of the CPU. This signal is fixed either high or low. When this

signal is high, the CPU will operate in small-scale system mode, and when low, in the large-scale system

mode. A small-scale system will have at most one bus master such as a DMA controller device on the bus. A

large-scale system can have more than one bus master accessing the bus as well as the CPU.

Pins 24 to 31 function differently depending on the operating mode of the CPU. Separate nomenclatttre is

adopted for these signals in the two operational modes. Function

Pin No.

S/LG-high

S/LG-low

INTAK

OS1

ASTB

OSo

BU FEN

BSo

BUFR/W

BS1

10/M

BS2

BUSLOCK

HLDAK

RO/AK1

HLDRQ

RO/AKo

INTAK [Interrupt Acknowledge] For small-scale systems. The CPU generates the INTAK signal low when it accepts an INT signal. The interrupting device synchronizes with this signal and outputs the interrupt vector to the CPU via the
data bus (AD1 – ADo). INTAK will be high during standby mode.
ASTB [Address Strobe] For small-scale systems. The CPU outputs this strobe signal to latch address information at an external latch. ASTB will be low
during standby mode.

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CX070116

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BUFEN [Buffer Enable] For small-scale systems. It is used as the output enable signal for an external bidirectional buffer. The CPU generates this signal
during data transfer operations with external memory or 1/0 devices or during input of an interrupt vector. BU FEN will be high during standby mode. It is three-state and floats to the high impedance during hold
acknowledge.
BUFR/W [Buffer Read/Write] For small-scale systems. The output of this signal determines the direction of data transfer with an external bidirectional buffer. A
high output causes transmission from the CPU to the external device; a low signal causes data transfer from the external device to the CPU.
BUFR/W will be either high or low during standby mode. It is three-state and floats to the high impedance during hold acknowledge.
iO/M [10/Memory] For small-scale systems. The CPU generates this signal to specify either 1/0 access or memory access. A low-level output
specifies 1/0 and a high-level specifies memory.
iO/M will be either high or low during standby mode. It is three-state and floats to the high impedance during hold acknowledge.
WR [Write Strobe] For small-scale systems.
The CPU generates this strobe signal during data write to an 1/0 device or memory. Selection of either 1/0 or memory is performed by the 10/M signal.
WR will be high during standby mode. It is three-state and floats to the high impedance during hold acknowledge.
HLDAK [Hold Acknowledge] For small-scale systems. The HLDAK signal is used to indicate that the CPU accepts the hold request signal (HLDRQ). When this
signal is high, the address bus, address/data bus, and the control lines become high impedance.
HLDRQ [Hold Request] For small-scale systems. This input signal is used by external devices to request the CPU to release the address bus, address/data
bus, and the control bus.
UBE [Upper Byte Enable] For small- and large-scale systems. UBE indicates the use of the upper eight bits (AD1s – ADs) of the address/data bus during a bus cycle.
This signal is active low during T1 for read, write, and interrupt acknowledge cycles when AD1s – ADs are to be used. Bus cycles in which UBE is active are shown in the following table.

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CXQ70116

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Type of Bus Operation Word at even address
Word at odd address
Byte at even address Byte at odd address Notes: *First bus cycle
**Second bus cycle

-UBE
0 0 1 1 0

A Do 0 1 *
o··
0 1

Number of Bus Cycle 1 2
1 1

UBE is low continuously during the interrupt acknowledge state. It will be high during standby mode. It is three-state and floats to the high impedance during hold acknowledge.

A19/PS3 – A16/PSo [Address Bus/Processor Status]

For small- and large-scale systems.

These pins are time-multiplexed to operate as an address bus and as processor status signals.

When used as the address bus, these pins are the high 4 bits of the 20-bit memory address. During 1/0

access, a11 4 bits output data 0.

The processor status signals are provided for both memory and 1/0 use. PSJ is always 0 in the native

mode and 1 in 8080 emulation mode. The interrupt enable flag (IE) is output on pin PS2. Pins PS1 and PSo indicate which memory segment is being accessed.

A11/PS1

A16/PSo

Segment

Data segment 1

Stack segment

Program segment

Data segment 0

A19/PS3 – A16/PSo will be either high or low during standby mode. They are three-state and float to the high impedance during hold acknowledge.

QS1, QSo [Queue Status] For large-scale systems. The CPU uses these signals to allow external devices, such as the floating-point arithmetic processor
chip, to monitor the status of the internal CPU instruction queue.

QS1

QSo

Instruction Queue Status

NOP (queue does not change)

First byte of instruction

Flush queue

Subsequent bytes of instruction

The instruction queue status indicated by these signals is the status when the execution unit (EXU) accesses the instruction queue. The data output from these pins is therefoe valid only for one clock cycle immediately following queue access. These status signals are provided so that the floating-point processor chip can monitor the CPU’s program execution status and synchronize its operation with the CPU when control is passed to it by the FPO (Floating Point Operation) instructions.
QS1, QSo will be low during standby mode.

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CX070116

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BS2 – BSo [Bus Status] For large-scale systems. The CPU uses these status signals to allow an external bus controller to monitor what the current bus
cycle is. The external bus controller decodes these signals and generates the control signals required to perform
access of the memory or 1/0 device.

BS2

BS1

BSo

Bus Cycle

Interrupt acknowledge

1/0 read

1/0 write

Halt

Program fetch

Memory read

Memory write

Passive state

BS2 – BSo will be high during standby mode. They are three-state and float to the high impedance during hold acknowledge.

BUSLOCK [Bus Lock] For large-scale systems. The CPU uses this signal to secure the bus while executing the instrucion immediately following the
BUSLOCK prefix instruction. It is a status signal to the other bus masters in a multiprocessor system inhibiting them from using the system bus during this time.
The output of this signal is three-state and becomes high impedance during hold acknowledge. BUSLOCK is high during standby mode except if the HALT instruction has a BUSLOCK prefix.

RO/AK1, RO/AKo [Hold Request/Acknowledge] For large-scale systems. These pins function as bus hold request inputs (RO) and as bus hold acknowledge outputs (AK). RO/AKo
has a higher priority than RO/AK1. These pins have three-state outputs with on-chip pull-up resistors which keep the pin at high level when
the output is high impedance.
Voo [Power Supply] For small- and large-scale systems.
This pin is used for the +sv power supply.

GND [Ground] For small- and large-scale systems. This pin is used for ground.

IC [Internally Connected] This pin is used for tests performed at the factory by SONY. The CXQ70116 is used with this pin at ground potential.

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CX070116

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Absolute Maximum Ratings

Parameter
Power supply voltage Input voltage CLK input voltage Output voltage Power dissipation Operating temperature Storage temperature

Symbol
Voo V1 VK Vo PoMAX Topr Tstg

(Ta=+25°C)

Rating Value
-0.5 to +7.0 -0.5 to Voo +o.3 -0.5 to Voo +1.0 -0.5 to Voo +0.3
+o.5 -40 to +85 -65 to +150

Unit
v v v v
w
oc oc

Comment: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational sections of this specification. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC Characteristics

CXQ70116-5, Ta=-40°C to +85°C, Voo=+5V±10%

Parameter

Symbol

CX070116-8, Ta=-10°C to +70°C, Voo=+5V±5%

Min.

Limits Typ.

Max.

Unit

Test Conditions

Input voltage high

VIH

2.2

v Voo+0.3

Input voltage low

VIL

-0.5

0.8

CLK input voltage high

VKH

3.9

v Voo+1.0

CLK input voltage low

VKL

-0.5

0.6

Output voltage high

VOH 0.7XVoo

loH=-400 µA

Output voltage low

VOL

0.4

loL=2.5 mA

Input leakage current high

ILIH

µA

V1=Voo

Input leakage current low

ILIL

-10

µA

V1=0V

Output leakage current high

ILOH

µA

Vo=Voo

Output leakage current low

ILOL

-10

µA

Vo=OV

Supply current

70116-5

5 MHz loo

70116-8 45

8 MHz

mA Normal operation

mA Standby mode

mA Normal Operation

mA Standby mode

Capacitance
Parameter Input capacitance 1/0 capacitance

Symbol
C1 C10

Limits

Min.

Max.

15 15

Unit
pF pF

(Ta=+25°C, Voo=OV)
Test Conditions
fc=1 MHz Unmeasured pins returned to OV

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CX070116

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AC Characteristics

CX070116-5, Ta=-40°C to +85°C, Voo=+5V±10% CX070116-8, Ta=-10°C to +70°C, Voo=+5V±5%

Parameter

CXQ70116-5 Symbol
Min. Max.

CXQ70116-8 Min. Max.

Small/Large Scale

Clock cycle

tCYK

200

500

125

500

Clock pulse width high

tKKH

Clock pulse width low

tKKL

Clock rise time
r—
Clock fall time

tKR

tKF

READY inactive setup to CLK !

tSRYLK

-8

READY inactive hold after CLK t tHKRYH

READY active setup to CLK t

tSRYHK tKKL-8

tKKL-8

READY active hold after CLK t

tHKRYL

Data setup time to CLK !

tSDK

Data hold time after CLK !

tHKD

NMI. INT, POLL setup time to CLK t tSIK

RESET setup time to CLK t

tSRST

RESET hold time to CLK t

tHRST

Input rise time (except CLK)

tlR

Input fall time (except CLK)

tlF

Output rise time

tOR

Output fall time

tOF

Small Scale

Address delay time from CLK

tDKA

Address hold time from CLK

tHKA

PS delay time from CLK !

tDKP

PS float delay time from CLK t

tFKP

Address setup time to ASTB !

tSAST tKKL-60

tKKL-30

Address float delay time from CLK ! tFKA

tHKA

ASTB t delay time from CLK !

tDKSTH

ASTB ! delay time from CLK t

tDKSTL

ASTB width high

tSTST tKKL-20

tKKL-10

Address hold time from ASTB !

tHSTA tKKH-10

tKKL-10

Unit

Test Conditions

ns ns VKH=3.0V ns VKL=1.5V ns 1.5V to 3.0V ns 3.0V to 1.5V ns ns ns ns ns ns ns ns ns ns 0.8V to 2.2V ns 2.2V to 0.8V ns 0.8V to 2.2V ns 2.2V to 0.8V
ns ns ns ns ns
CL=100 pF ns ns ns ns ns

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CX070116

Parameter

CXQ70116·5 Symbol
Min. Max.

CXQ70116-8 Min. Max.

Unit

Test Conditions

Control delay time from CLK

tDKCT

110

Address float to RD )

tAFRL

RD ) delay time from CLK )
RD t delay time from CLK )

lDKRL tDKRH

165

150

Address delay time from RD l –·
RD width low

lDRHA tCYk-45 IRA 2tcvK-75

tCYk-40 2tcvK-50

ns ns CL=100 pF

Data output delay time from CLK ) tDKD

Data float delay time from CLK ) tFKD

WR width low

tww 2tcvK-60

2tcvK-40

–

HLDRO setup time to CLK l

tSHQK

HLDAK delay time from CLK )

lDKHA

160

100 ns

Large Scale

Address delay time from CLK

!OKA

Address hold time from CLK

tHKA

PS delay time from CLK )

IDKP

PS float delay time from CLK t

IFKP

Address float delay time from CLK ) tFKA

tHKA

Address delay time from RD l

tDRHA tcvK-45

tcvK-40

ASTB l delay time from BS )

!OBST

BS ) delay time from CLK l

lDKBL

110

BS l delay time from CLK )

tDKBH

130

RD ) delay time from address float tDAFRL

CL=100 pF

RD ) delay time from CLK l
R- D l delay time from CLK l

tDKRL tDKRH

165

150

RD width low

!RR 2tcvK-75

2tcvK-50

Data output delay time from CLK ) IDKD

Data float delay time from CLK ) !FKD

AK delay time from CLK )
RO setup time to CLK t RO hold time after CLK t

tDKAK

tSRQK

lHKRO

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CXQ70116

Timing Waveforms

AC Test Input Waveform [Except CLK]

2.2V

2.4V~

0.4V~

o.av

AC Output Test Points

-~r~

o.av

Wait [Ready] Timing

CLK

Clock Timing
CLK

SONY@

BUSLOCK Output Timing

POLL. NM I, INT input Timing
CLK~
PO([~
NMl,IT~

RESET Timing

Vee _ J
CLK RESET

L4 CLK CYCLES

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CX070116

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Read Timing [Small Scale]

CLK

A1/PS3 A,,IPS0 .j_J,’1<-;lf~

T4 ,_

Write Timing [Small Scale]

CLK

A1.,’PS3 A11/PS0

__..,,._.,_……,,’——…;._…jL_.j(,_

ASTB BUFFi.1W

Read Timing [Large Scale]

CLK

ASTB (71088
Output)

BUFR W

iOM -_V/…___ _ _ _ _ _V I _-_ –

Write Timing [Large Scale]

CLK

A1,JPS3 A 1_tP$0
USE

A0 15 -A00

ASTB (71088
Output)

8$2 – 850

Bus Status

as,-as0

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CX070116

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Interrupt Acknowledge Timing

BUFFi’W IOM
Hold Request/Acknowledge Timing [Small Scale] 1 or2 CLK HLDRQ HLDAK
Bus Request/Acknowledge Timing [Large Scale]

~1m·_”P’-.:

1._~1-m·”P’I

70116

Coprocessor

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CX070116

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Program Counter [PC] The program counter is a 16-bit binary counter that contains the segment offset address of the next
instruction which the EXU is to execute. The PC increments each time the microprogram fetches an instruction from the instruction queue. A new
location value is loaded into the PC each time a branch, call, return, or break instruction is executed. At this time, the contents of the PC are the same as the Prefetch Pointer (PFP).

Prefetch Pointer [PFP] The prefetch pointer ( PFP) is a 16-bit binary counter which contains a segment offset which is used to
calculate a program memory address that the bus control unit ( BCU) uses to prefetch the next word for the instruction queue. The contents of PFP are an offset from the PS (Program Segment) register.
The PFP is incremented each time the BCU prefetches an instruction from the program memory. A new location will be loaded into the PFP whenever a branch, call, return, or break instrucion is executed. At that time the contents of the PFP will be the same as those of the PC (Program Counter).

Segment Registers [PS, SS, DSo, and DS1]

The memory addresses accessed by the CXQ70116 are divided into 64K-byte logical segments. The

starting (base) address of each segment is specified by a segment register, and the offset from this starting

address is specified by the contents of another register or by the effective address. These are the four types of segment registers used.

Segment Register

Default Offset

PS (Program Segment) !——–
SS (Stack Segment)

PFP SP, effective address

DSo (Data Segment 0)

IX, effective address

DS1 (Data Segment ‘I)

General-Purpose Registers [AW, BW, CW, and OW] There are four 16-bit general-purpose registers. Each one can be used as one 16-bit register or as two
8-bit registers by dividing them into their high and low bytes (AH, AL BH, BL CH, CL, DH, DL). Each register is also used as a default register for processing specific instructions. The default
assignments are: AW: Word multiplication/division, word 1/0, BCD rotation, data conversion, translation AL: Byte multiplication/division, byte 1/0, BCD rotation, data conversion, translation AH: Byte multiplication/division BW: Translation CW: Loop control branch, repeat prefix CL: Shift instructions, rotation instructions, BCD operations OW: Word multiplication/division, indirect addressing 1/0

Pointers [SP, BP] and Index Registers [IX, IY] These registers serve as base pointers or index registers when accessing the memory using based addressing, indexed addressing, or based indexed addressing.
These registers can also be used for data transfer and arithmetic and logical operations in the same manner as the general-purpose registers. They cannot be used as 8-bit registers.
Also, each of these registers acts as a default register for specific operations. The default assignments are: SP: Stack operations IX: Block transfer (source), BCD string operations IY: Block transfer (destination), BCD string operations

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CX070116

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Program Status Word [PSW]

The program status word consists of the following six status and four control flags.

Status Flags

Control Flags

· V (Overflow)

· MD (Mode)

· S (Sign)

· DIR (Direction)

· Z (Zero)

· IE (Interrupt Enable)

· AC (Auxiliary Carry)

· BRK (Break)

· P (Parity)

· CY (Carry)

When the PSW is pushed on the stack, the word images of the various flags are as shown here.

PSW

15 14 13 12 11 10 9 8 7 6 5 4 3 2

v D

Bs z0 A0 p

I ER

The status flags are set and reset depending upon the result of each type of instruction executed. Instructions are provided to set, reset and complement the CY flag directly. Other instructins set and reset the control flags and control the operation of the CPU.

High-Speed Execution of Instructions
This section highlights the major architectural features that enhance the performance of the CXQ70116. · Dual data bus in EXU · Effective address generator · 16/32-bit temporary registers/shifters (TA. TB) · 16-bit loop counter · PC and PFP
Dual Data Bus Method To reduce the number of processing steps for instruction execution, the dual data bus method has been
adopted for the CXQ70116 (figure 1). The two data buses (the main data bus and the subdata bus) are both 16 bits wide. For addition/subtraction and logical and comparison operations, processing time has been speeded up some 30% over single-bus systems.

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CX070116
Fig. 1. Dual Data Buses
16

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Fig. 2. Effective Address Generator
First and second byte of instruclion

EA Generator

l!ffectlve ·ddreH

SUbdatabus

Main data bus

Example ADD AW, BW Single Bus Step 1 TA – AW Step 2 TB – BW Step 3 AW – TA +

;AW – AW+ BW Dual Bus TA – AW, TB – BW AW+– TA+ TB TB

Effective Address Generator This circuit (figure 2) performs high-speed processing to calculate effective addresses for accessing
memory. Calculating an effective address by the microprogramming method normally requires 5 to 12 clock cycles.
This circuit requires only two clock cycles for addresses to be generated for any addressing mode. Thus, processing is several times faster.

16/32· Bit Temporary Registers/Shifters [TA. TB] These 16-bit temporary registers/shifters (TA. TB) are provided for multiplication/division and shift/rotation
instructions. These circuits have decreased the execution time of multiplication/division instructions. In fact, these
instructions can be executed about four times faster than with the microprogramming method. TA + TB: 32-bit temporary register/shifer for multiplication and division instructions. TB: 16-bit temporary register/shifter for shift/rotation instructions.

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Loop Counter [LC] This counter is used to count the number of loops for a primitive block transfer instruction controlled by a
repeat prefix instruction and the number of shifts that will be performed for a multiple bit shift/rotation instruction.
The processing performed for a multiple bit rotation of a register is shown below. The average speed is approximately doubled over the microprogram method.

Example RORC AW.CL; CL= 5
+ Microprogram method
8 (4 X 5) = 28 clocks

LC method
+ 7 5 = 12 clocks

Program Counter and Prefetch Pointer [PC and PFP] The CXQ70116 microprocessor has a program counter (PC), which addresses the program memory
location of the instruction to be executed next, and a prefetch pointer (PFP), which addresses the program memory location to be accessed next. Both functions are provided in hardware. A time saving of several clocks is realized for branch, call, return, and break instruction execution, compared with microprocessors that have only one instruction pointer.

Enhanced Instructions
In addition to the 8088/86 instructions, the CXQ70116 has the following enhanced instructions.

Instruction PUSH imm PUSH R POP imm POP R
MUL imm SHL imm8 SHR imm8 SHRA imm8 ROL imm8 ROR imm8 ROLC imm8 RORC imm8
CH KIND INM OUTM PREPARE DISPOSE

Function Pushes immediate data onto stack Pushes 8 general registers onto stack Pops immediate data onto stack Pops 8 general registers from stack Executes 16-bit multiply of register or memory contents by immediate data
Shifts/rotates register or memory by immediate value
Checks array index against designated boundaries Moves a string from an 1/0 port to memory Moves a string from memory to an 1/0 port Allocates an area for a stack frame and copies previous frame pointers Frees the current stack frame on a procedure exit

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Enhanced Stack Operation Instructions
PUSH imm/POP imm These instructions allow immediate data to be pushed onto or popped from the stack.

PUSH R/POP R These instructions allow the contents of the eight general registers to be pushed onto or popped from the
stack with a single instruction.

Enhanced Multiplication Instructions MUL reg16, imm16/MUL mem16, imm16
These instructions allow the contents of a register or memory location to be 16-bit multiplied by
immediate data.

Enhanced Shift and Rotate Instructions SHL reg, imm8/SHR reg, imm8/SHRA reg, imm8
These instructions allow the contents of a register to be shifted by the number of bits defined by the
immediate data.

ROL reg, imm8/ROR reg. imm8/ROLC reg, imm8/RORC reg, imm8

These instructions allow the contents of a register to be rotated by the number of bits defined by the

immediate data.

Check Array Boundary Instruction CHKIND reg16, mem32

This instruction is used to verify that index values pointing to the elements of an array data structure are

within the defined range. The lower limit of the array should be in memory location mem32, the upper lmit
+ in mem32 2. If the index value in reg16 is not between these limits when CH KIND is executed, a BRK 5

will occur. This causes a jump to the location in interrupt vector 5.

Block 1/0 Instructions OUTM OW, src-block/INM dst-block, OW
These instructions are used to output or input a string to or from memory. when preceded by a repeat
prefix.

Stack Frame Instructions PREPARE imm16, imm8
This instruction is used to generate the stack frames required by block-structures languages, such as PASCAL and Ada. The stack frame consists of two area. One area has a pointer that points to another frame which has variables that the current frame can access. The other is a local variable area for the current procedure.
DISPOSE This instruction releases the last stack frame generated by the PREPARE instruction. It returns the stack
and base pointers to the values they had before the PREPARE instruction was used to call a procedure.

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Unique Instructions

In addition to the 8088/86 instructions and the enhanced instructions, the CXQ70116 has the following unique instructions.

Instruction INS EXT ADD4S SUB4S CMP4S ROL4 ROR4 TEST1 NOT1 CLR1 SET1 REPC RE PNC FP02

Function Insert bit field Extract bit field Adds packed decimal strings Subtracts one packed decimal string from another Compares two packed decimal strings Rotates one BCD digit left through AL lower 4 bits Rotates one BCD digit right through AL lower 4 bits Tests a specified bit and sets/resets Z flag Inverts a specified bit Clears a specified bit Sets a specified bit Repeats next instruction until CY flag is cleared Repeats next instruction until CY flag is set Additional floating point processor call

Variable Length Bit Field Operation Instructions This category has two instructions: INS (Insert Bit Field) and EXT (Extract Bit Field). These instructions
are highly effective for computer graphics and high· level languages. They can, for example, be used for data structures such as packed arrays and record type data used in PASCAL.

INS reg8, regB/INS reg8, imm4

This instruction (figure 3) transfers low bits from the 16-bit AW register (the number of bits is specified

by the second operand) to the memory location specified by the segment base (DS1 regist~

plus the byte

offset (IY register). The starting bit position within this byte is specified as an offset by the lower 4-bits of

the first operand.

After each complete data transfer, the IY register and the register specified by the first operand are

automatically updated to point to the next bit field.

Either immediate data or a register may specify the number of bits transferred (second operand). Because

the maximum transferable bit length is 16-bits, only the lower4·bits of the specified register (OOH to OFH)

will be valid.

Bit field data may overlap the byte boundary of memory.

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Fig. 3. Bit Field Insertion
15
AW

Btt-h

V(Il~-

rBit offset Byte boundary

Byleolfset(IY)

:’I.

Memory

‘

Segment base (DS1)

EXT reg8. reg8/ EXT reg8, imm4

This instruction (figure 4) loads to the AW register the bit field data whose bit length is specified by the

second operand of the instruction from the memory location that is specified by the DSo segment register

(segment base), the IX index register (byte offset), and the lower 4-bits of the first operand (bit offset).

After the transfer is complete, the IX register and the lower 4-bits of the fi’rst operand are automatically

updated to point to the next bit field.

Either immediate data or a register may be specified for the second operand. Because the maximum transferrable bit length is 16 bits, however, only the lower4-bits of the specified register(OH to OFH) will be
valid. Bit field data may overlap the byte boundary of memory.

Fig. 4. Bit Field Extraction
i
15
AWi

ij(J lBtt-

1 0
V/111

Byte Boundary

Byle-(IX)

·,

:: t Segmeot base (OSOi

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Packed BCD Operation Instructions
The instructions described here process packed BCD data either as strings (ADD4S, SUB4S, CMP4S) or byte-format operands (ROR4, ROL4). Packed BCD strings may be from 1 to 255 digits in ~ngth.
When the number of digits is even, the zero and carry flags will be set according to the result of the operation. When the number of digits is odd, the zero and carry flags may not be set correctly in this case, (CL= odd), the zero flag will not be set unless the upper4 bits of the highest byte are all zero. The carry flag will not be set unless there is a carry out of the upper 4 bits of the highest byte. When CL is odd, the contents of the upper 4 bits of the highest byte of the result are undefined.

ADD4S This instruction adds the packed BCD string addressed by the IX index register to the packed BCD string
addressed by the IY index register, and stores the result in the string addressed by the IY register. The length of the string (number of BCD digits) is specified by the CL register, and the result of the operation will affect the carry flag (CY) and zero flag (Z).
+ BCD string (IY, CL) – BCD string (IY, CL) BCD string (IX, CL)

SUB4S This instruction subtracts the packed BCD string addressed by the IX index register from the packed BCD
string addressed by the IY index register, and stores the result in the string addressed by the IY register. The length of the string (number of BCD digits) is specified by the CL register, and the result of the operation will affect the carry flag (CY) and zero flag (Z).
BCD string (IY, CL) – BCD string (IY, CL) – BCD String (IX, CL)

CMP4S This instruction performs the same operation as SUB4S except that the result is not stored and only carry
flags (CY) and zero flag (Z) are affected. BCD string (IY, CL) – BCD string (IX, CL)

ROL4 This instruction (figure 5) treats the byte data of the register or memory directly specified by the instruction
byte as BCD data and uses the lower 4 bits of the AL register (ALL) to rotate that data one BCD digit to the left. Fig. 5. BCD Rotate Left (ROL4)

reg/mem

ROR4 This instruction (figure 6) treats the byte data of the register or memory directly specified by the instruction
byte as BCD data and uses the lower 4 bits of the AL register (ALL) to rotate that data one BCD digit to the right. Fig. 6. BCD Rotate Right (ROR4)
AL

Bit Manipulation Instructions
TEST1 This instruction tests a specific bit in a register or memory location. If the bit is 1, the Z flag is reset to O.
If the bit is 0, the Z flag is set to 1.
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NOT1 This instruction inverts a specific bit in a register or memory location.

CLR1
This instruction clears a specific bit in a register or memory location.

SET1 This instruction sets a specific bit in a register or memory location.

Repeat Prefix Instructions
REPC
This instruction causes the CXQ70116 to repeat the following primitive block transfer instruction until the CY flag becomes cleared or the CW register becomes zero.

REPNC
This instruction causes the CXQ70116 to repeat the following primitive block transfer instruction until the CY flag becomes set or the CW register becomes zero.

Floating Point Instruction

FP02

This instruction is in addition to the 8088/86 floating point instruction, FP01. These instructions are covered in a later section.

Mode Operation Instructions

The CXQ70116 has two operating modes (figure 7). One is the native mode which executes 8088/86, enhanced and unique instructions. The other is the 8080 emulation mode in which the instruction set of the 8080 is emulated. A mode flag (MD) is provided to select between these two modes. Native mode is selected when MD is 1 and emulation mode when MD is 0. MD is set and reset. directly and indirectly, by executing the mode manipulation instructions.
Two instructions are provided to switch operation from the native mode to the emulation mode and back: BRKEM (Break for Emulation), and RETEM (Return from Emulation).
Two instructions are used to switch from the emulation mode to the native mode and back: CALLN (Call Native Routine), and RETI (Return from Interrupt).
The system will return from the 8080 emulation mode to the native mode when the RESET signal is present, or when an external interrupt ( NMI or INT) is present.

Fig. 7. Operating Modes

HOLD REOJHOLD ACK

8080 Mode
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BRKEM imm8 This is the basic instruction used to start the 8080 emulation mode. This instruction operates exactly the
same as the BRK instruction, except that BRKEM resets the mode flag (MD) to 0. PSW, PS and PC are saved to the stack. MD is then reset and the interrupt vector specified by the operand imm8 of this command is loaded into PS and PC.
The instruction codes of the interrupt processing routine jumped to are then fetched. Then the CPU executes these codes as 8080 instructions.
In 8080 emulation mode, registers and flags of the 8080 are performed by the following registers and flags of the CXQ70116.

8080

CXQ70116

Registers:

Flags:

In the native mode, SP is used for the stack pointer. In the 8080 emulation mode this function is performed by BP.
This use of independent stack pointers allows independent stack areas to be secured for each mode and keeps the stack of one of the modes from being destroyed by an erroneous stack operation in the other mode.
The SP, IX, IY and AH registers and the four segment registers (PS, SS, DSo, and DS1) used in the native mode are not affected by operations in 8080 emulation mode.
In the 8080 emulation mode, the segment register for instructions is determined by the PS register (set automatically by the interrupt vector) and the segment register for data is the DSo register (set by the programmer immediately before the 8080 emulation mode is entered).

RETEM [no operand] When RETEM is executed in 8080 emulation mode (interpreted by the CPU as 8080 instruction), the
CPU restores PS, PC, and PSW (as it would when returning from an interrupt processing routine), and returns to the native mode. At the same time, the contents of the mode flag (MD) which was saved to the stack by the BRKEM instruction, is restored to MD = 1. The CPU is set to the native mode.

CALLN imm8 This instruction makes it possible to call the native mode subroutines from the 8080 emulation mode. To
return from subroutine to the 8080 emulation mode, the RETI instruction is used. The processing performed when this instruction is executed in the 8080 emulation mode (it is interpreted
by the CPU as 8080 instruction), is similar to that performed when a BRK instruction is executed in the

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native mode. The imm8 operand specifies an interrupt vector type. The contents of PS. PC, and PSW are pushed on the stack and an MD flag value of 0 is saved. The mode flag is set to 1 and the interrupt vector specified by the operand is loaded into PS and PC.
RETI [no operand] This is a general-purpose instruction used to return from interrupt routines entered by the BRK instruction
or by an external interrupt in the native mode. When this instruction is executed at the end of a subroutine entered by the execution of the CALLN instruction, the operation that restores PS, PC, and PSW is exactly the same as the native mode execution. When PSW is restored, however, the 8080 emulation mode value of the mode flag (MD) is restored, the CPU is set in emulation mode, and all subsequent instructions are interpreted and executed as 8080 instructions.
RETI is also used to return from an interrupt procedure initiated by an NMI or INT interrupt in the emulation mode.

Floating Point Operation Chip Instructions

FP01 fp-op, mem/FP02 fp-op, mem

These instructions are used for the external floating point processor. The floating point operation is

passed to the floating point processor when the CPU fetches one of these instructions. From this point the

CPU performs only the necessary auxiliary processing (effective address calculation, generation of physical

addresses, and start-up of the memory read cycle). The floating point processor always monitors the instructions fetched by the CPU. When it interprets one
as an instruction to itself, it performs the appropriate processing. At this time, the floating point processor chip uses either the address alone or both the address and read data of the memory read cycle executed by

the CPU. This difference in the data used depends on which of these instructions is executed.

Note: During the memory read cycle initiated by the CPU for FP01 or FP02 execution, the CPU does not

accept any read data on the data bus from memory. Although the CPU generates the memory

address, the data is used by the floating point processor.

Interrupt Operation

The interrupts used in the CXQ70116 can be divided into two types: interrupts generated by external interrupt requests and interrupts generated by software processing. These are the classifications.

External interrupts (a) NMI input (nonmaskable) (b) INT input (maskable)

Software processing As the result of instruction execution -When a divide error occurs during execution of the DIV or DIVU instruction -When a memory-boundary-over error is detected by the CHKIND instruction Conditional break instruction – When V = 1 during execution of the BRKV instruction Unconditional break instructions -1-byte break instruction: BRK3 -2-byte break instruction: BAK imm8 Flag processing -When stack operations are used to set the BRK flag 8080 Emulation mode instructions -BRKEM imm8 -CALLN imm8

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Interrupt vectors Starting addresses for interrupt processing routines are either determined automatically by a single
location of the interrupt vector table or selected each time interrupt processing is entered. The interrupt vector table is shown in figure 8. The table uses 1 K bytes of memory addresses OOOH to
3 FFH and can store starting address data for a maximum of 256 vectors (4 bytes per vector). The corresponding interrupt sources for vectors 0 to 5 are predetermined and vectors 6 to 31 are
reserved. These vectors consequently cannot be used for general applications. The BR KEM instruction and CALLN instruction (in the emulation mode) and the INT input are available for
general applications for vectors 32 to 255. A single interrupt vector is made up of 4 bytes (figure g). The 2 bytes in the low addresses of memory are
loaded into PC as the offset, and the high 2 bytes are loaded into PS as the base address. The bytes are combined in reverse order. The lower-order bytes in the vector become the most significant bytes in the PC and PS, and the higher-order bytes become the least significant bytes.

Fig. 8. Interrupt Vector Table

OOOH 004H 008H OOCH 010H 014H 018H

VectorO Veclor1 Vector2 Vector3 Vector4 Yector5 Vector&

Divide Error

Break Flag

NMI Input

r=. “-_BAK 3 lnstrucllon BRKV Instruction

Dedicated

07CH 080H
3FCH

Vector31 Vector32
Vector225

Gene<alUse
} · BAK imma Instruction · BRKEM lnslruction · INT Input [External) · CALLN Instruction

Fig. 9. Interrupt Vector 0

002H

PS ~(03H.

002H)

PC ~ (001H. OOOH)

001H 003H

Based on this format, the contents of each vector should be initialized at the beginning of the program. The basic steps to jump to an interrupt processing routine are now shown.
(SP -1, SP -2) PSW (SP -3, SP -4) PS (SP -5. SP -6) PC SP +- SP -6 IE +- 0, BRK +- 0, MD PS vector high bytes PC +- vector low bytes

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Standby Function
The CXQ70116 has a standby mode to reduce power consumption during program wait states. This mode is set by the HALT instruction in both the native and the emulation mode.
In the standby mode, the internal clock is supplied only to those circuits related to functions required to release this mode and bus hold control functions. As a result, power consumption can be reduced to 1/10 the level of normal operation in either native or emulation mode.
The standby mode is released by inputting a RESET signal or an external interrupt (NMI, INT). The bus hold function is effective during standby mode. The CPU returns to standby mode when the bus hold request is removed. During standby mode, all control outputs are disabled and the address/data bus will be either high or low.

Instruction Set

The following tables briefly describe the CXQ70116’s instruction set.

· Operation and Operand Types – difines abbreviations used in the Instruction Set table.

· Flag Operations – difines the symbols used to describe flag operations.

· Memory Addressing – shows how mem and mod combinations specify memory addressing modes.

· Selection of 8- and 16-Bit Registers – shows how reg and W select a register when mod = 111 .

· Selection of Segment Registers – shows how sreg selects a segment register. · Instruction Set – shows the instruction mnemonics, their effect their operation codes the number of
bytes in the instruction, the number of clocks required for execution, and the effect on the CXQ70116

flags.

Operation and Operand Types

Identifier reg reg8 regl 6 dmem mem mem8 mem16 mem32 imm imm16 imm8 imm4 imm3 ace sreg src-table

Description 8- or 16-bit general-purpose register 8-bit general-purpose register 16-bit general-purpose register 8- or 16-bit direct memory location 8- or 16-bit memory location 8- bit memory location 16-bit memory location 32-bit memory location Constant (0 to FFFFH) Constant (0 to FFFFH) Constant (0 to FFH) Constant (0 to FH) Constant (0 to 7) AW or AL register Segment register Name of 256-byte translation table

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Identifier src-block dst-block near-proc far-proc near-label short-label far-label
memptr16
memptr32
regptrl 6
pop-value
fp-op
R
w
reg mem mod S:W
X, XXX, YYY, zzz
AW AH AL BW
cw
CL
ow
SP PC PSW IX IY

Description
Name of block addressed by the IX register Name of block addressed by the IY register Procedure within the current program segment Procedure located in another program segment Label in the current program segment Label between -128 and +127 bytes from the end of instruction Label in another program segment Word containing the offset of the memory location within the current program segment to which control is to be transferred Double word containing the offset and segment base address of the memory location to which control is to be transferred 16-bit register containing the offset of the memory location within the program segment to which control is to be transferred Number of bytes of the stack to be discarded (0 to 64 K bytes, usually even addresses) Immediate data to identify the instruction code of the external floating point operation Register set Word/byte field (0 to 1) Register field (000 to 111) Memory field (000 to 111) Mode field (00 to 10) When S:W=01 or 11, data=l 6 bits. At all other times, data=8 bits. Data to identify the instruction code of the external floating point arithmetic chip Accumulator (16 bits) Accumulator (high byte) Accumulator (low byte) BW register (16 bits)
cw register (16 bits)
CW register (low byte) OW register (16 bits) Stack pointer (16 bits) Program counter (16 bits) Program status word (16 bits) Index register (source) (16 bits) Index register (destination) (16 bits)

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CX070116
Identifier PS SS DSo DS1 AC
CY
p
s z
DIR IE
v
BRK MD
( … )
disp ext-disp8 temp tmpcy seg offset
~
+
x
% AND OR XOR XXH XXXXH

SONY@
Description Program segment register (16 bits) Stack segment register (16 bits) Data segment 0 register (16 bits) Data segment 1 register (16 bits) Auxiliary carry flag Carry flag Parity flag Sign flag Zero flag Direction flag Interrupt enable flag Overflow flag Break flag Mode flag Values in parentheses are memory contents Displacemerit (8 or 16 bits) 16-bit displacement (sign-extension byte +8-bit displacement) Temporary register (8/16/32 bits) Temporary carry flag (1 bit) Immediate segment data (16 bits) Immediate offset data (16 bits) Transfer direction Addition Subtraction Multiplication Division Modulo Logical product Logical sum Exclusive logical sum Two-digit hexadecimal value Four-digit hexadecimal value

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Flag Operations
Identifier (blank)
0 1
x u
R

Description No change Cleared to 0 Set to 1 Set or cleared according to the result Undefined Value saved earlier is restored

Memory Addressing

mem
000 001 010 011 100 101 110 111

00 BW +IX BW+ IY BP+ IX BP+ IY IX IY Direct address BW

mod 01
BW +IX+ disp8 BW + IY + disp8 BP+ IX+ disp8 BP+ IY + disp8 IX+ disp8 IY + disp8 BP+ disp8 BW + disp8

10 BW +IX+ disp16 BW + IY + disp16 BP+ IX+ ·disp16 BP+ IY + disp16 IX+ disp16 IY + disp16 BP+ disp16 BW + disp16

Selection of 8-and 16-Bit Registers (mod 11)

reg

W=O

W=1

000

001

010

011

100

101

110

111

Selection of Segment Registers

sreg

DS1

DSo

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The table on the following pages shows the instruction set. At “No. of Clocks,” for instructions referencing memory operands, the left side of the slash(/) is the number of clocks for byte operands or word operands of an even address, and the right side is for word operands of an odd address. For conditional control transfer instructions, the left side of the slash(/) is the number of clocks if a control transfer takes place. The right side is the number of clocks when no control transfer or branch occurs. Some instructions show a range of clock times, separated by a hyphen. The execution time of these instructions varies from the minimum value to the maximum, depending on the operands involved.
Note: Add four clocks to these times for each word transfer made to an odd address.
“No. of Clocks” includes these times: · Decoding · Effective address generation · Operand fetch · Execution It assumes that the instruction bytes have been prefetched.

-101 –

Mnemonic Operand

MOV

reg, reg

mem, reg

Operation
reg – reg (mem)-reg

Operation Code

No. of No. of

Flags

x()

7 6 5 4 3 2 I D 7 6 5 4 3 2 I D Clocks Bytes AC CY v p s z

p
-.I

Data Transfer Instructions

!::

1 0 0 0 1 0 1 w 1 1 reg

reg 2

“‘

1 0 0 0 1 o O W mod reg

mem 9/13

2-4

reg, mem

reg-(mem)

1 0 0 0 1 0 1 W mod reg

mem 11/15 2-4

mem, imm reg, imm ace, dmem
dmem, ace

(mem)-imm

1 1 0 0 0 1 1 W mod 0 0 0 mem 11/15 3-6

reg -imm

1 0 1 1 w reg

2-3

When W= 0 AL – (dmem) When W= 1 AH – (dmem + 1), AL – (dmem)

1 0 1 0 0 00 w

10/14 3

When W= 0 (dmem) – AL When W= 1 (dmem + 1) – AH, (dmem) – AL

10 10 0 01 w

9/13

sreg, reg16

sreg – reg16

sreg : SS. OSO, OS1 1 0 0 0 1 1 1 0 1 1 0 sreg reg 2

sreg, mem16

sreg – (mem16)

sreg : SS, OSO, OS1 1 0 0 0 1 1 1 0 mod 0 sreg mem 11/15 2-4

reg16, sreg

reg16-sreg

1 0 0 0 1 1 0 0 1 1 0 sreg reg 2

mem16, sreg

(mem16) – sreg

1 0 0 0 1 1 0 0 mod 0 sreg mem 10/14 2-4

OSO, reg16, mem32

reg16 – (mem32) OSO – (mem32 + 2)

1 1 0 0 0 1 0 1 mod reg mem 18/26 2-4

0 N

OS1, reg16,

reg16 – (mem32)

mem32

OS1 – (mem32 + 2)

1 1 0 0 0 1 0 0 mod reg

mem 18/26 2-4

AH, PSW

AH – S, Z, x, AC, x, P, x, CY

100 11111

1 x x xxx

PSW, AH

S, Z, x, AC, x, P, x, CY – AH

100 11110

1 x x xxx

LOEA

reg16, mem16

reg16 – mem16

1 0 0 0 1 1 0 1 mod reg mem 4

2-4

TRANS

src-table

AL-(BW+ AL)

11 0 10 111

XCH

reg, reg

reg-reg

1 0 0 0 0 1 1 W1 1 reg

reg 3

mem, reg or reg, mem

(mem)-reg

1 0 0 0 0 1 1 W mod reg mem 16/24 2-4

AW, reg16 or reg16, AW

AW-reg16

1 0 0 1 0 reg

Repeat Prefixed

REPC

While CW = 0, the following primitive block 0 1 1 0 0 1 0 1

transfer instruction is executed and cw is

decremented (- 1). If there is a waiting interrupt it

is processed. When CY = 1, exit the loop.

RE PNC

While CW = 0, the following primitive block
transfer instruction is executed and cw is
decremented (- 1). If there is a waiting interrupt it
is processed. When CY = 0, exit the loop.

0 1 1 0 0 1 0 0

0 z
~

Mnemonic Operand
REP REPE REPZ
~· REPNZ

Operation Code

No.of No. ol

Flags

x(“)

Operation

7 6 5 4 3 2 I 0 7 6 5 4 3 2 I 0 Clocks Bytes AC CY v p s z

.0…

Repeat Prefixed (cont)

!:!

While CW .= O. the following primitive block 1 1 1 1 0 0 1 1

transfer instruction is executed and CW is

decremented (- 1). If there is a waiting interrupt, 11 is

processed. If the primitive block transfer instruction

is CMPBK or CMPM and Z # 1, exit the loop.

While CW # 0, the following primitive block 1 1 1 1 0 0 1 0 transfer instruction is executed and CW is decremented (- 1). If there is a waiting interrupt, it is processed. If the primitive block transfer instruction is CMPBK or CMPM and Z # 0, exit the loop.

Primitive Block Transfer Instructions

MOVBK

dst-block,

When W= 0 (IY) – (IX)

src-block

DIR= 0: IX – IX+ 1, IY – IY + 1

DIR= 1: IX – IX -1, IY – IY- 1

When W= 1 (IY + 1, IY) – (IX+ 1, IX)

DIR = 0: IX – IX + 2, IY – IY + 2

t-CMPBK

dst-block,

DIR= 1: IX – IX – 2, IY – IY – 2 When W = 0 (IX) – (IY)

src-block

DIR= 0: IX – IX+ 1, IY – IY + 1

0 w

DIR= 1: IX – IX – 1, IY – IY – 1 When W= 1 (IX+ 1, IX) – (IY -t 1, IY)

DIR= 0: IX – IX + 2, IY – IY + 2
DIR= 1: IX -1x – 2, IY -1v – 2

1 0 1 0 0 10 w 10 1 0 0 11w

CMPM

dst-block

When W = 0 AL- (IY) DIR =0: IY-IY + 1; DIR= 1: IY-IY-1
When W= 1 AW- (IY + 1, IY) DIR= O: IY – IY + 2; DIR= 1: IY – IY – 2

10 1 0 1 11 w

LDM

src-block

When W = 0 AL – (IX)

1 0 1 0 1 10 w

DIR= 0: IX – IX+ 1; DIR= 1: IX – IX – 1

When W = 1 AW – (IX+ 1, IX)

DIR = 0: IX – IX + 2; DIR= 1 IX – IX – 2

STM

dst-block

When W = 0 (IY)-AL

10 10 101w

DIR= 0: IY – IY + 1; DIR= 1: IY – IY – 1

When W = 1 (IY+ 1, IY)-AW

DIR= 0 IY-IY + 2; DIR= 1: IY-IY-2

n: number of transfers

11+8n 1 7 + 14n 1 x x x x x x 7+10n 1 x x x x x x 7 + 9n 1 7 + 4n 1

Bit Field Transfer Instructions

INS

reg8, reg8

16-Bit field – AW

0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 31-117 3

reg8, imm4

16-Bit field – AW

1 1 reg

reg

/35-133

0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 1 67-87 4

0 z

1 1 0 0 0 reg

/75-103

Mnemonic Operand

EXT

regs, regs

Operation
AW+- 16-Bit field

Operation Code

No.of No.of

Flags

x()

765432 I 0 765432 I 0 Bit Field Transfer Instructions (cont!

Clocks Bytes AC CYVPSZ

.gp…

0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 26-55 3

“‘

1 1 reg

reg

/34-59

regs, imm4

AW +- 16-Bit field

0 0 0 0 1 1 1 1 0 0 1 1 1 0 1 1 21-44 4

1 1 0 0 0 reg

/25-52

1/0 Instructions

ace, immS

When W = O AL +- (imm8)

1 1 1 0 0 10 w

When W= 1 AH+- (immS + 1), AL+- (immS)

ace, OW

When W= 0 Al +- (OW) When W = 1 AH +- (OW+ 1), Al+- (OW)

1 1 1 0 1 10 w

OUT

imms. ace

When W= O (immS) +- AL

11 10 0 11w

When W = 1 (imm8 + 1) +- AH, (imm8) +-Al

OW, ace

When W = 0 (OW) +- Al When W= 1 (OW+ 1) +-AH, (OW) +- Al

11 1 0 1 11w

9/13

8/12

Primitive 1/0 Instructions

INM

dsl-block, OW

When W = 0 (IV) +- (OW)

0 1 1 0 1 10 w

DIR= O: IV+- IV+ 1; DIR= 1: IV+- IV – 1

When W= 1 (IV+ 1, IY) +-(OW+ 1, OW)

0
.j:>.

DIR = 0: IV +- IV+ 2; DIR= 1: IV +- IV – 2

OUTM

OW, src-block

When W= 0 (OW) +- (IX)

0 1 1 0 1 11 w

DIR = O: IX +- IX + 1; DIR = 1: IX +- IX – 1

When W= 1 (OW+ 1, OW)+- (IX+ 1, IX)

DIR = 0: IX +- IX + 2; DIR = 1: IX +- IX – 2

n: number of transfers

9 +Sn 1 9+ 8n 1

Addition/Subtraction Instructions

ADD

reg, reg

reg +- reg + reg

0000001 W1 1 reg

reg 2

2 x x xxxx

mem,reg

(mem) +- (mem) + reg

O 0 0 0 0 0 0 W mod reg mem 16/24 2-4 x x x x x x

reg, mem

reg +- reg + (mem)

0000001 W mod reg mem 11 /15 2-4 x x x x x x

reg, imm

reg +- reg + imm

1 OOOOOSW1 1 0 0 0 reg 4

3-4 x x x x x x

mem, imm

(mem)+-(mem)+imm

1 0 0 0 0 0 S W mod 0 0 0 mem 18/26 3-6 x x x x x x

ace, imm

When W = 0 Al +- Al + imm WhenW=l AW+-AW+imm

0000010W

2-3 x x x x x x

ADDC

reg, reg

reg +- reg + reg + CY

0 0 0 1 0 0 1 W1 1 reg

reg 2

2 x x xxxx

mem, reg reg, mem reg, imm mem, imm

(mem) +- (mem) +reg + CY reg +- reg + (mem) +CY reg +- reg + imm +CY (mem) +- (mem) + imm + CY

0 0 0 1 O O O W mod reg mem 16/24 2-4 x x x x x x

0 0 0 1 0 0 1 W mod reg

mem

100000SW1 1 0 1 0 reg

11/15 4

2-4 x x x x x x 3-4 x x x x x x

0 z

1 0 0 0 0 0 S W mod 0 1 0 mem 18/26 3-6 x x x x x x

Mnemonic Operand

ADDC

ace, imm

Operation

Operation Code

No.of No.of

Flags

7 6 5 4 3 2 I 0 7 6 5 4 3 2 I 0 Clocks Bytes AC CY v p s z

n x

Addition/Subtraction Instructions !cont)

.p… ‘.:

When W = 0 AL +–AL – imm – CY When W= 1 AW+– AW – imm – CY

0 0 0 1 0 10 w

2-3 x x x x x x

“‘

SUB

reg, reg

reg +– reg – reg

mem, reg

(mem) +– (mem) – reg

0 0 1 0 1 0 1 W1 1 reg
0 0 1 o· 1 0 0 W mod reg

reg 2 mem 16/24

2 x x xxxx 2-4 x x x x x x

SUBC

reg, mem reg, imm mem, imm ace, imm
reg, reg

reg +–reg – (mem) reg +– reg – imm (mem)+-(mem)-imm
When W= 0 AL+– AL – imm WhenW= 1 AW+-AW-imm reg +– reg – reg – CY

0 0 1 0 1 0 1 W mod reg

mem

s 1 0 0 0 0 0 W1 1 1 0 1 reg

s 1 0 0 0 0 0 W mod 1 0 1 mem

0 0 1 0 1 10 w

11/15 4 18/26 4

w 0 0 0 1 1 0 1 1 1 reg

reg 2

2-4 x x x x x x 3-4 x x x x x x 3-6 x x x x x x 2-3 x x x x x x
2 x x xxxx

mem, reg

(mem) +– (mem) – reg – CY

0 0 0 1 1 O O W mod reg

mem 16/24 2-4 x x x x x x

reg, mem

reg +– reg – (mem) – CY

0 0 0 1 1 0 1 W mod reg

mem 11/15 2-4 x x x x x x

reg, imm

reg +– reg – imm – CY

s w 1 0 0 0 0 0

1 1 0 1 1 reg 4

3-4 x x x x x x

mem, imm

(mem) +– (mem) – imm – CY

s 1 0 0 0 0 0 W mod 0 1 1 mem 18/26 3-6 x x x x x x

ace, imm

When W = 0 AL+– AL+ imm +CY

0 0 0 1 1 10 w

2-3 x x x x x x

WhenW= 1 AW +–AW+ imm +CY

BCD Operation Instructions

ADD4S

dst BCD string …….. dst BCD string + src BCD string

0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 7+19n 2 u x u u u x

SUB4S

dst BCD string …….. dst BCD string – src BCD string

0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 7+19n 2 u x u u u x

CMP4S

dst BCD string – src BOC string

0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 7+19n 2 n: number of BCD numerals divided by 2

u x uu ux

ROL4

reg8

7 AL

mem8 7 AL
I

AL,

H 0

I I· ‘”9
Uppe<4bits L.ower4bits

0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 25
I 1 1 0 0 0 reg

H I I· I 0
AL,

mem Uppe< 4 bits Lower 4 bits

0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 28 mod 0 0 0 mem

3
I
l
I 3-5

ROR4

reg8

7 AL
I

AL,

H 0

I I ‘”9
Uppe<4btts Lower4btts

0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0 29 1 1 0 0 0 reg

00
0 z

mem8 7 AL
I

AL,

H 0

I I mem
Uppe<4btts Lower4bits

0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0 33 mod 0 0 0 mem

3-5

Mnemonic Operand

ING

reg8

mem

Operation
reg8 +- reg8 + 1 (mem) ……. (mem) + 1

Operation Code

No. of No.of

Flags

7 6 5 4 3 2 I 0 7 6 5 4 3 2 I 0 Clocks Bytes AC CY v p s z

n x .0….

Increment/Decrement Instructions (cont)

1 1 1 1 1 1 1 0 1 1 0 0 0 reg 2

2 x

x x x x

“‘

1 1 1 1 1 1 1 W mod 0 0 0 mem 16/24 2·4 x

x x x x

reg16

reg16 – reg16 + 1

0 1 0 0 0 reg

1 x

x x x x

DEG

reg8

reg8 ……. reg8 – 1

1 1 1 1 1 1 1 0 1 1 0 0 1 reg 2

2 x

x x x x

mem

(mem) ……. (mem) – 1

1 1 1 1 1 1 1 W mod 0 0 1 mem 16/24 2·4 x

x x x x

reg16

reg16 ……. reg16 – 1

0 ·1 0 0 1 reg

1 x

x x x x

Multiplication Instructions

MULU

reg8

AW+-ALx reg8 AH = 0: CY ……. O. V +- 0 AH.CO: GY +-1, V +-1

1 1 1 1 0 1 1 0 1 1 1 0 0 reg 21-22

2 u x xuuu

mem8

AW+- AL x (mem8) AH = 0: CY ……. 0, V ……. 0 AH.CO: GY +-1, V +-1

1 1 1 1 0 1 1 0 mod 1 0 0 mem 27-28

2-4 u x x u u u

reg16

DW, AW +-AW x reg16 DW = O: CY +- 0, V ……. 0 DW.cO: GY +-1, V +-1

1 1 1 1 0 1 1 1 1 1 1 0 0 reg 29-30

2 u x xuuu

0
°I ‘

mem16

DW, AW+- AW x (mem16) DW = 0: CY ……. 0, V ……. 0 DW.cO: CY +-1, V+-1

1 1 1 1 0 1 1 1 mod 1 0 0 mem 35-36 /39-40

2-4 u x x u u u

MUL

reg8

AW +-ALx reg8 AH = AL sign expansion: CY ……. 0, V +- O AH ,c AL sign expansion: CY ……. 1, V +- 1

1 1 1 1 0 1 1 0 1 1 1 0 1 reg 33-39

2 u x xuuu

mem8

AW +-AL x (mem8) AH = AL sign expansion: CY +- 0. V ……. 0 AH # AL sign expansion: CY +- 1, V ……. 1

1 1 1 1 0 1 1 0 mod 1 0 1 mem 39-45

2-4 u x x u u u

reg16

DW, AW +-AW x reg16 DW =AW sign expansion: CY +- 0. V +– 0 DW ,c AW sign expansion: CY ……. 1, V +- 1

1 1 1 1 0 1 1 1 1 1 1 0 1 reg 41-47

2 u x xuuu

mem16

DW, AW+- AW x (mem16) DW =AW sign expansion: CY ……. 0, V +- O DW #AW sign expansion: CY ……. 1, V +– 1

1 1 1 1 0 1 1 1 mod 1 0 1 mem 47-53 /51-57

2-4 u x x u u u

reg16, (reg16,) imm8
reg16, mem16, imm8

reg16 +– reg16 x imm8 Product,.; 16 bits: CY +- 0, V +- O Product> 16 bits: CY +- 1, V +– 1
reg16 +- (mem16) x imm8 Product,.; 16 bits: CY +- 0, V ……. 0 Product> 16 bits: CY +- 1, V ……. 1

0 1 1 0 1 0 1 1 1 1 reg

reg 28-34

3 u x xuuu

0 1 1 0 1 0 1 1 mod reg

mem 34-40 /38-44

3-5 u x x u u u

0 z

Mnemonic Operand

MUL

reg16,

(reg16,)

imm16

Operation

Operation Code

No.of No.of

Flags

7 6 5 4 3 2 I 0 7 6 5 4 3 2 I 0 Clocks Bytes AC CY v p s z

(.0x.).

reg16 ……. reg16 x imm16

Multiplication Instructions (cont) 0 1 1 0 1 0 0 1 1 1 reg

reg

1 36-42

u x xuuu

~
“‘

Product,,:; 16 bits: CY ……. 0, V ……. 0

Product> 16 bits: CY ……. 1, V ……. 1

reg16, mem16, imm16

reg16 ……. (mem16) x imm16 Product,,:; 16 bits: CY ……. 0, V ……. O Product> 16 bits: CY ……. 1, V ……. 1

0 1 1 0 1 0 0 1 mod reg

mem 42·48 /46·52

4-6 u x x u u u

Unsigned Division Instructions

DIVU

reg8

temp ……. AW
When temp+ reg8 > FFH (SP – 1, SP – 2) ……. PSW, (SP – 3, SP – 4) ……. PS (SP – 5, SP – 6) ……. PC, SP ……. SP – 6 IE ……. 0, BRK ……. 0, PS +- (3, 2), PC ……. (1, 0) All other times AH ……. temp % reg8, AL ……. temp + reg8

1 1 1 1 0 1 1 0 1 1 1 1 0 reg

2 u u uuuu

‘

mem8

temp ……. AW

1 1 1 1 0 1 1 0 mod 1 1 0 mem 25

2-4 u u u u u u

When temp+ (mem8) > FFH

(SP – 1, SP – 2) +- PSW, (SP – 3, SP – 4) ……. PS

(SP – 5, SP – 6) ……. PC, SP ……. SP – 6

IE ……. 0, BRK ……. 0, PS ……. (3, 2), PC ……. (1, 0)

All other times

-J

AH ……. temp% (mem8), AL ……. temp+ (mem8)

reg16

temp +-AW

1 1 1 1 0 1 1 1 1 1 1 1 0 reg

When temp+ reg16 > FFFFH

(SP – 1, SP – 2) ……. PSW, (SP – 3, SP – 4) ……. PS

(SP – 5, SP – 6) ……. PC, SP ……. SP – 6

IE ……. 0, BRK ……. 0, PS +- (3, 2), PC ……. (1, 0)

All other times

AH ……. temp% reg16, AL ……. temp+ reg16

2 u u uuuu

mem16

temp +-AW When temp+ (mem16) > FFFFH (SP – 1, SP – 2) ……. PSW, (SP – 3. SP – 4) ……. PS (SP – 5, SP – 6) ……. PC, SP ……. SP – 6 IE ……. 0, BRK ……. 0, PS ……. (3, 2), PC ……. (1, 0)
All other times AH ……. temp% (mem16), AL ……. temp+ (mem16)

1 1 1 1 0 1 1 1 mod 1 1 0 mem

31/35

2-4 u u u u u u

Signed Division Instructions

DIV

reg8

temp +-AW

1 1 1 1 0 1 1 0 1 1 1 1 1 reg

29·34

2 u u uuuu

fl}

When temp + reg8 > Oand temp + reg8 > 7FH or
temp+ reg8 < 0 and temp+ reg8:;;: 0 · 7FH – 1
(SP – 1, SP – 2) ……. PSW, (SP – 3, SP – 4) ……. PS
(SP – 5, SP – 6) ……. PC, SP ……. SP – 6 IE ……. 0, BRK ……. 0, PS +- (3, 2), PC ……. (1, 0)

0 z
~

All other times

AH ……. temp% reg8, AL ……. temp+ reg8

Mnemonic Operand

DIV

mem8

Operation

Operation Code

No.of No.of

Flags

x(‘)

7 6 5 4 3 2 1 0 7 6 5 4 3 2 I 0 Clocks Bytes AC CY V P S Z

.0…

Signed Division Instructions (cont)

temp <–AW

1 1 1 1 0 1 1 0 mod 1 1 1 mem 35-40

2-4 u u u u u u

When temp+ (mem6) > 0 and temp+ (mem6) > 7FH
or temp + (memB) < 0 and

temp+ (mem8)::; 0 – 7FH – 1

(SP – 1, SP – 2) …_ PSW, (SP – 3, SP – 4) …_ PS

(SP – 5, SP – 6) …_ PC, SP …_ SP – 6

IE …_ 0, BAK …_ 0, PS …_ (3, 2), PC…_ (1, 0)

All other times

AH – temp% (mem8), AL – temp+ (mem8)

reg16

temp-AW

1 1 1 1 0 1 1 1 1 1 1 1 1 reg

When temp+ reg16 > Oand temp+ reg16 > 7FFFH
or temp + reg16 < O and

temp+ reg16 ,;;O- 7FFFH – 1

(SP – 1, SP – 2) …_ PSW, (SP – 3, SP – 4) …_ PS

(SP – 5, SP – 6) …_ PC, SP…_ SP – 6

IE…_ 0, BAK…_ 0, PS…_ (3, 2), PC<– (1, 0)

All other times

AH – temp% reg16, AL …_ temp+ reg 16

38-43

2 u u uuuu

mem16

temp-AW

1 1 1 1 0 1 1 1 mod 1 1 1 mem 44-49 2-4 u u u u u u

When temp+(mem16)>0 and temp+(mem16)>7FFFH

0 00

or temp+ (mem16) < 0 and temp+ (mem16)

o>O-?FFFH-1

/48-53

(SP – 1, SP – 2) – PSW, (SP – 3, SP – 4) – PS

(SP – 5, SP – 6) …_ PC, SP – SP – 6

IE…_ 0, BAK…_ 0, PS – (3, 2), PC – (1, 0)

All other times

AH – temp% (mem16), AL…_ temp+ (mem16)

BCD Complement Instructions

ADJ BA

When (AL AND OFH) > 9 or AC = 1, AL – AL+ 6, AH…_ AH+ 1, AC…_ 1, CY …_ AC, AL …_ AL AND OFH

00 110111

1 x x uuuu

ADJ4A

When (AL AND OFH) > 9 or AC= 1, AL…_ AL+ 6, CY …_CY OR AC, AC…_ 1, When AL> 9FH, or CY= 1 AL…_ AL+ 60H, CY …_ 1

00 100 111

1 x x uxxx

ADJ BS ADJ4S

When (AL AND OFH) > 9 or AC = 1, AL…_ AL – 6, AH…_ AH – 1, AC – 1, CY …_AC, AL – AL AND OFH
When (AL AND OFH) > 9 or AC= 1, AL-AL-6, CY <–CY OR AC, AC <–1 When AL > 9FH or CY = 1 AL …_ AL – 60H, CY …_ 1

00 11 11 11 00 10 1111

1 x x uuuu

1 x x uxxx

0 z

Mnemonic Operand CVTBD

Operation

Operation Code 76 5 4 32 I0 76 5 4 32 I 0
Data Conversion Instructions

No.of No. of

Flags

Clocks Bytes AC CY v p s z

s(x.p.’.).

AH – AL+ OAH, AL – AL %OAH

1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 15

2 u u uxxx

“‘

CVTDB

AH – 0, AL – AH x OAH + AL

1101010100001010 7

2 u u uxxx

GVTBW

When AL< 80H, AH – 0, all other times AH – FFH

10 0 1 10 0 0

CVTWL

When AL< 8000H, OW – 0, all other times DW – FFFFH

100 110 01

4-5

CMP

reg, reg

reg – reg

Comparison Instructions
w 0 0 1 1 1 0 1 1 1 reg

reg 2

2 x x xxxx

mem, reg

(mem) – reg

0 0 1 1 1 0 0 W mod reg

mem 11/15

2-4 x x x x x x

reg, mem reg, imm mem, imm ace, imm

reg-(mem)
reg-imm (mem)-imm
When W= 0, AL – imm When W= 1, AW-imm

0 0 1 1 1 0 1 W mod reg

mem

w s 1 0 0 0 0 0

1 1 1 1 1 reg

s 1 0 0 0 0 0 W mod 1 1 1 mem

w 0 0 1 1 1 1 0

11/15 4 13/17 4

2-4 x x x x x x 3-4 x x x x x x 3-6 x x x x x x 2-3 x x x x x x

0 D

NOT

reg

mem

NEG

reg

reg – reg (mem) – (mem) reg – reg+ 1

Complement Instructions
w 1 1 1 1 0 1 1 1 1 0 1 0 reg
1 1 1 1 0 1 1 W mod 0 1 0 mem
w 1 1 1 1 0 1 1 1 1 0 1 1 reg

2 16/24 2

2 2-4 2 x x xxxx

mem

(mem) – (mem) + 1

1 1 1 1 0 1 1 W mod 0 1 1 mem 16/24 2-4 x x x x x x

TEST

reg, reg

reg AND reg

Logical Operation Instructions
w 1 0 0 0 0 1 0 1 1 reg

reg 2

2 u 0 0x xx

mem, reg or reg, mem
reg, imm

(mem) AND reg reg AND imm

1 0 0 0 0 1 0 W mod reg

mem

w 1 1 1 1 0 1 1 1 1 0 0 0 reg

10/14 4

2-4 u 0 0 x x x 3-4 u 0 0 x x x

mem. imm

(mem) AND imm

ace, imm

When W = 0, AL AND imm8 When W = 1, AW AND imm8

AND

reg, reg

reg – reg AND reg

1 1 1 1 0 1 1 W mod 0 0 0 mem
w 1 0 1 0 1 0 0

w 0 0 1 0 0 0 1 1 1 reg

reg

11/15 4
2

u 0 0xxx

2-3 u 0 0 x x x

2 u 0 0x xx

mem. reg reg, mem reg, imm mem, imm ace, imm

(mem) – (mem) AND reg reg – reg AND (mem) reg – reg AND imm (mem) – (mem) AND imm
When W = 0, AL – AL AND imm8 When W = 1, AW -AW AND imm16

0 0 1 0 0 0 0 W mod reg

mem 16/24

2-4 u 0 0 x x x

0 0 1 0 0 0 1 W mod reg

mem

w 1 0 0 0 0 0 0 1 1 1 0 0 reg

1 0 0 0 0 0 0 W mod 1 1 0 mem
w 0 0 1 0 0 1. 0

11/15 4 18/26 4

2-4 u 0 0 x x x

3-4 u 0 0 x x x

u 0 0x xx

2-3 u 0 0 x x x

en
0 z
~

Mnemonic Operand

reg, reg

Operation reg – reg OR reg

Operation Code

No. of No. of

Flags

7 6 5 4 3 2 I 0 7 6 5 4 3 2 I 0 Clocks Bytes AC CY y p s z

x() .0…

Logical Operation Instructions [contl

0 0 0 0 1 0 1 W1 1 reg

reg 2

2 u 0 0xxx

mem, reg

(mem) – (mem) OR reg

0 0 0 0 1 0 0 W mod reg

rnem 16/24 2-4 u 0 0 x x x

reg, mem reg, imm

reg – reg OR (mem) reg – reg OR imm

0 0 0 0 1 0 1 W mod reg

mem

w 1 0 0 0 0 0 0 1 1 0 0 1 reg

11/15 4

2-4 u 0 0 x x x
3-4 u 0 0 x x x

mem, imm ace, imm

(mem) +– (mem) OR imm
When W = 0, AL +– AL OR imm8 When W = 1, AW +–AW OR imm16

1 0 0 0 0 0 0 W mod 0 0 1 mem
0 0 0 0 1 10 w

18/26 4

3-6 u 0 0 x x x 2-3 u 0 0 x x x

XOR

reg, reg

reg +– reg XOR reg

0 0 1 1 0 0 1 W1 1 reg

reg 2

2 u 0 0xx x

mem, reg

(mem) ,..__ (mem) XOR reg

0 0 1 1 0 0 0 W mod reg

mem 16/24

2-4 u 0 0 x x x

reg, mem reg, imm

reg ,..__ reg XOR (mem) reg +– reg XOR imm

0 0 1 1 0 0 1 W mod reg

mem

w 1 0 0 0 0 0 0 1 1 1 1 0 reg

11/15 4

2-4 u 0 0 x x x 3-4 u 0 0 x x x

mem, imm ace, imm

(mem)+–(mem)XORimm
When W= 0, AL+– AL XOR imm8 When W = 1, AW+– AW XOR imm16

1 0 0 0 O O O W mod 1 1 0 mem
0 0 1 1 0 10 w

18/26 4

3-6 u 0 0 x x x 2-3 u 0 0 x x x

Bit Operation Instructions

TEST1

reg8, CL

reg8 bit no. CL = O: Z +– 1 reg8 bit no. CL = 1: Z ,..__ O

2nd byte·

3rd byte·

0 0 0 1 0 0 0 0 1 1 0 0 0 reg 3

3 u 0 0uux

memB, CL

(mem8) bit no. CL= O: Z ,..__ 1 (mem8) bit no. CL= 1: Z – O

0 0 0 1 0 0 0 0 mod 0 0 0 mem 12

3-5 u 0 0 u u x

reg16, CL

reg16 bit no. CL= O: Z ,..__ 1 reg16 bit no. CL= 1: Z ,..__ O

0 0 0 1 0 0 0 1 1 1 0 0 0 reg 3

3 u 0 0uux

mem16, CL

(mem16) bit no. CL= 0: Z +– 1 (mem16) bit no. CL= 1: Z ,..__ 0

0 0 0 1 0 0 0 1 mod 0 0 0 mem 12/16 3-5 u 0 0 u u x

reg8, imm3

reg8 bit no. imm3 = 0: Z +- 1 reg8 bit no. imm3 = 1: Z +–0

0 0 0 1 1 0 0 0 1 1 0 0 0 reg 4

4 u 0 0uux

mem8, imm3

[mem8) bit no. imm3 = O: Z ,..__ 1 (mem8) bit no. imm3 = 1: Z +– 0

0 0 0 1 1 0 0 0 mod 0 0 0 mem 13

4-6 u 0 0 u u x

reg16, imm4 mem16, imm4

reg16 bit no. imm4 = 0: Z +– 1 reg16 bit no. imm4 = 1: Z +– 0
(mem16) bit no. imm4 = 0: Z +– 1 (mem16) bit no. imm4 = 1: Z ,..__ O

0 0 0 1 1 0 0 1 1 1 0 0 0 reg 4

4 u 0 0uux

0 0 0 1 1 0 0 1 mod 0 0 0 mem 13/17 4-6 u 0 0 u u x

2nd byte* ‘Note: First byte= OFH

3rd byte’

0 z

Mnemonic Operand

Operation

Operation Code

No. of No. of

Flags

x()

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Clocks Bytes AC CY ‘ p s z

0
-.J

Bit Operation lnslructions fcontl

😕

2nd byte’

3rd byte’

NOT1

regs. CL

regs bit no. CL – regs bit no. CL

0 0 0 1 0 1 1 0 1 1 0 0 0 reg 4

memS, CL

(memS) bit no. CL – (memS) bit no. CL

0 0 0 1 0 1 1 0 mod 0 0 0 mem 1S

3-5

reg16, CL

reg16 bit no. CL – reg16 bit no. CL

0 0 0 1 0 1 1 1 1 1 0 0 0 reg 4

mem16, CL

(mem16) bit no. CL – (mem16) bit no. CL

0 0 0 1 0 1 1 1 mod 0 0 0 mem 18/26 3-5

regS, imm3

regs bit no. imm3 – regs bit no. imm3

0 0 0 1 1 1 1 0 1 1 0 0 0 reg 5

memS, imm3

(memS) bit no. imm3 – (mem8) bit no. imm3

0 0 0 1 1 1 1 0 mod 0 0 0 mem 19

4-6

reg16, imm4

reg16 bit no. imm4 – (reg16) bit no. imm4

0 0 0 1 1 1 1 1 1 1 0 0 0 reg 5

mem16, imm4

(mem16) bit no. imm4 – (mem16) bit no. imm4

0 0 0 1 1 1 1 1 mod 0 0 0 mem.J 19/27 4-6

CY+- CY

2nd byte’ ·Note: First byte = OFH

3rd byte’

1 1 1 1 0 1 0 1

2ndjyte’

3rd _’!.Yte’

CLR1

reg8, CL

regs bit no. CL – 0

memS, CL

(memS) bit no. CL – 0

reg16, CL

reg16 bit no. CL – 0

mem16, CL

(mem16) bit no. CL – 0

reg8, imm3

reg8 bit no. imm3 – 0

memS, imm3

(memS) bit no. imm3 – 0

reg16, imm4

reg16 bit no. imm4 – O

mem16, imm4

(mem16) bit no. imm4 – 0

CY-a

DIR

DIR-a

0 0 0 1 0 0 1 0 1 1 0 0 0 reg 5

0 0 0 1 0 0 1 0 mod 0 0 0 mem 14

3-5

0 0 0 1 0 0 1 1 1 1 0 0 0 reg 0 0 0 1 0 0 1 1 mod 0 0 0 mem

l 14/22 3-5

0 0 0 1 1 0 1 0 1 1 0 0 0 reg 6

0 0 0 1 1 0 1 0 mod 0 0 0 mem 15

4-6

0 0 0 1 1 0 1 1 1 1 0 0 0 reg 6

0 0 0 1 1 0 1 11Lmod 0 0 0 mem 15/27

4-6

2nd byte· ·Note: First byte= OFH

3rd byte’

11 1 1 10 00

11 111 100

rn
0 z
~

Mnemonic Operand

Operation

Operation Code

No. of No. of

Flags

x()

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Clocks Bytes AC CY V P S Z

.0…

Bit Operation Instructions (cont)

2ndjyte·

3rd byte·

“‘

SET1

reg8, CL

reg8 bit no. CL+- 1

mem8, CL

(mem8) bit no. CL +- 1

reg16, CL

reg16 bit no. CL+- 1

mem16, CL

(mem16) bit no. CL+- 1

reg8, imm3

reg8 bit no. imm3 +- 1

mem8, imm3

(mem8) bit no. imm3 +- 1

reg16, imm4

reg16 bit no. imm4 +- 1

mem16, imm4

(mem16) bit no. imm4 +- 1

0 0 0 1 0 1 0 0 1 1 0 0 0 reg 4

0 0 0 1 0 1 0 0 mod 0 0 0 niem 13

3.5

0 0 0 1 0 1 0 1 1 1 0 0 0 reg 4

0 0 0 1 0 1 0 1 mod 0 0 0 mem 13/21 3.5

0 0 0 1 1 1 0 0 1 1 0 0 0 reg 5

0 0 0 1 1 1 0 0 mod 0 0 0 mem 14

4-6

0 0 0 1 1 1 0 1 1 1 0 0 0 reg 5

0 0 0 1 1 1 0 1 mod 0 0 0 mem 14/22 4-6

2nd byte· ·Note: First byte = OFH

3rd byte·

CY +-1

1 1 1 1 1 0 0 1

DIR

DIR+- 1

1 1 1 1 1 1 0 1

Shift Instructions

SHL

reg, 1

CY +- MSB of reg, reg +- reg x 2

When MSB of reg# CY, V +- 1

w 0 1 0 0 0 1 1 1 0 0 reg 2 2

u xx x x x

When MSB of reg= CY, V +- 0

mem, 1 reg, CL

CY +- MSB of (mem), (mem) +- (mem) x 2 When MSB of (mem) #CY, V +- 1 When MSB of (mem) =CY, V +- O
temp +- CL, while temp “” 0, repeat this operation: CY +- MSB of reg, reg +- reg x 2, temp +-temp – 1

1 1 0 1 OOOWmod 1 0 0 mem 16/24 2-4 u x x x x x

w 1 1 0 1 0 0 1 1 1 1 0 0 reg 7+n

2 uxuxxx

mem, CL

temp +- CL, while temp# 0, repeat this operation: CY +- MSB of (mem), (mem) +- (mem) x 2, temp +-temp – 1

1 1 0 1 0 0 1 W mod 1 0 0 mem 19/27
+ n

2-4 u x u x x x

reg, immB

temp+- imm8, while temp# 0, repeat this operation: CY+- MSB of reg, reg +- reg x 2, temp +-temp – 1

1 1 OOOOOW1 1 1 0 0 reg 7+n

3 uxuxxx

mem, immB

temp+- imm8, while temp# 0,

1 1 0 0 0 0 0 W mod 1 0 0 mem 19/27 3.5 u x u x x x

SHR

reg, 1

repeat this operation: CY +- MSB of (mem), (mem) +- (mem) x 2, temp +- temp – 1

+ n
n: number of shifts

CY +- LSB of reg, reg +- reg + 2 When MSB oi reg #bit following MSB

w 1 1 0 1 0 0 0 1 1 1 0 1 reg 2

2 uxxxxx

0 z

of reg: V +-1 When MSB of reg = bit following MSB

of reg: V +-0

Mnemonic Operand

SHR

mem, 1

reg, CL

Operation

Operation Code

No.DI No.DI

flags

x()

7 6 5 4 3 2 I 0 7 6 5 4 3 2 I 0 Clocks Bytes AC CY v p s z

.0…

Shih lnstrucllons (conl)

:1 en

CY+– LSB of (mem), (mem) +– (mem) + 2

1 1 0 1 0 0 0 W mod 1 0 1 mem 16/24 2-4 u x x x x x

When MSB of (mem) ‘°bit following MSB

of (mem): V +– 1
When MSB of (mem) = bit following MSB

of (mem): V +– 0

temp +–CL, while temp’° 0,

w 1 1 0 1 0 0 0 1 1 1 0 1 reg 7+n

2 u x uxxx

repeat this operation: CY +– LSB of reg,

reg +– reg + 2, temp +–temp – 1

mem,CL

temp +–CL, while temp’° 0, repeat this operation: CY+– LSB of (mem), (mem) +– (mem) + 2, temp+– temp – 1

1 1 0 1 0 0 1 W mod 1 0 1 mem 19/27
+ n

2-4 u x u x x x

reg, imm8

temp +– imm8, while temp ‘° 0, repeat this operation: CY +– LSB of reg, reg +– reg + 2, temp +– temp – 1

1 1 0 0 0 0 0 W1 1 1 0 1 reg 7+n

3 u x uxx x

mem, imm8

temp +– imm8, while temp ‘° 0, repeat this operation; CY +– LSB of (mem),

1 1 0 0 OOOWmod 1 0 1 mem 19/27
+ n

3-5 u x u x x x

(mem) – (mem) + 2, temp – temp – 1

n: number of shifts

SHRA

reg, 1

CY +– LSB of reg, reg +– reg + 2, V +– 0

w 1 1 0 1 0 0 0 1 1 1 1 1 reg 2

u x 0 X- X x

MSB of operand does not change

mem, 1

CY+– LSB of (mem), (mem) – (mem) + 2,

1 1 0 1 0 0 0 W mod 1 1 1 mem 16/24 2-4 u x 0 x x x

V +– 0, MSB of operand does not change

reg, CL

temp – CL, while temp ‘° 0,

w 1 1 0 1 0 0 1 1 1 1 1 1 reg 7+n

2 u x ux xx

repeat this operation: CY +– LSB of reg,

reg +- reg + 2, temp +– temp – 1

MSB of operand does not change

mem, CL

temp – CL, while temp ‘° 0, repeat this operation: CY +– LSB of (mem), (mem) +– (mem) + 2, temp – temp – 1 MSB of operand does not change

1 1 0 1 0 0 1 W mod 1 1 1 mem

19/27
+ n

2-4 u x u x x x

reg, imm8

temp +– imm8, while temp ‘° 0,
repeat this operation: CY – LSB of reg, reg +- reg + 2, temp +– temp – 1
MSB of operand does not change

1 1 OOOOOW1 1 1 1 1 reg 7+n

3 u x ux xx

mem, imm8

temp +– imm8, while temp “” 0, repeat this operation: CY+- LSB of (mem), (mem) +– (mem) + 2, temp – temp – 1 MSB of operand does not change

1 1 0 0 OOOWmod 1 1 1 mem 19/27
+ n

3-5 u x u x x x

n: number of shifts
–

en
0 z
~

Mnemonic Operand

ROL

reg, 1

Operation

Operation Code

Na.of Na.of

Flags

7 & 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Clocks Byles AC CY V P S Z

()
.~ …

Rotation Instructions

CY +- MSB of reg, reg +- reg x 2 + CV

1 1 0 1 0 0 0 w 1 1 0 0 0 reg 2

x x

“‘

MSB of reg 7′ CV: V +-1
MSB of reg =CV· V +- 0

mem, 1 reg, CL

CY +- MSB of (mem), (mem) +- (mem) x 2 +CY MSB of (mem) 7′ CY: V +- 1
MSB of (mem) =CY: V +- 0
temp +- CL, while temp 7′ 0, repeal this operation: CY +- MSB of reg, reg +-regx2+CY temp +- temp – 1

1 1 0 1 OOOWmodOOO mem 16/24 2-4

x x

1 1 0 1 0 0 1 w 1 1 0 0 0 reg 7+n

x u

mem, CL

temp +- CL, while temp 7′ 0, repeat this operation: CY +- MSB of (mem), (mem) +- (mem) x 2 +CY temp +- temp – 1

1 1 0 1 0 0 1 WmodOOO reg 19/27 2-4 + n

x u

reg, imm8

temp +- imm8, while temp 7′ 0, repeat this operation: CY +- MSB of reg, reg+-regx2+CY temp +- temp – 1

1 1 OOOOOW1 1 0 0 0 reg 7+n

x u

.j::>.

mem, imm8

temp +- imm8, while temp 7’ 0,

1 1 O 0 O 0 O W mod 0 0 0 mem 19/27 3-5

x u

repeal this operation: CY+- MSB of (mem),

+ n

(mem) +- (mem) x 2 +CY

temp +- temp – 1

n: number of shifts

ROR

reg, 1

CY +- LSB of reg, reg +- reg “‘ 2

1 1 0 1 0 0 0 w 1 1 0 0 1 reg 2

x x

MSB of reg +- CV

MSB of reg 7’ bit following MSB of reg: V +- 1
MSB of reg = bit 1ollowing MSB of reg: V +- 0

mem, 1

CY +- LSB of (mem), (mem) +- (mem) “‘2 MSB of (mem) +-CY

1 1 0 1 OOOWmod 0 0 1 mem 16/24 ·2-4

x x

MSB of (mem),,. bit following MSB

of (mem): V +- 1
MSB o1 (mem) =bit following MSB

of (mem): V +- 0

reg, CL

temp +- CL, while temp 7’ 0,

w 1 1 0 1 0 0 1 1 1 0 0 1 reg 7+n

x u

repeat this operation: CY +- LSB of reg,

reg +- reg “‘ 2, MSB of reg +- CY

mem, CL

temp +- tP,mp – 1
temp +- CL, while temp 7’ 0, repeat this operation: CY +- LSB of (mem). (mem) +- (mem) “‘2, MSB of (mem) +-CY

1 1 0 1 0 0 1 W mod 0 0 1 mem 19/27 2-4 + n

x u

Cll
0 z

temp +-temp – 1

n:number of shifts

Mnemonic Operand

Operation

Operation Code

No.of No.of

Flags

x(“)

7 6 5 4 3 2 1 0 7 6 5 4 3 2 I 0 Clocks Bytes AC CY ‘ p s z

Rotation Instructions (cont)

ROA

reg, imm8

temp +- imm8, while temp 7′ 0,

w 1 1 0 0 0 0 0 1 1 0 0 1 reg 7+n

x u

repeat this operation: CY +- LSB of reg,

reg +- reg + 2, MSB of reg +- CY

temp +- temp – 1

mem, imm8

temp +- imm8, while temp,. 0, repeat this operation: CY+- LSB of (mem), (mem) +- (mem) + 2 temp +- temp – 1

1 1 0 0 0 0 0 W mod 0 0 1 mem 19/27 3-5
+ n
n: number of shifts

x u

ROLC

reg, 1

tmpcy +-CY, CY+- MSB of reg reg +- reg x 2 + tmpcy MSB of reg = CY: V +- 0
MSB of reg 7′ CY: V +- 1

Rotate Instruction

w 1 1 0 1 0 0 0 1 1 0 1 0 reg 2

x x

mem, 1

tmpcy +-CY, CY+- MSB of (mem)

1 1 0 1 0 0 0 W mod 0 1 0 mem 16/24 2-4

x x

(mem) +- (mem) x 2 + tmpcy

MSB of (mem) =CY: V +- 0

MSB of (mem) 7′ CY: V +- 1

reg, CL

temp +- CL, while temp 7′ 0,

w 1 1 0 1 0 0 1 1 1 0 1 0 reg 7+n

x u

repeat this operation: tmpcy +-CY,

CY +- MSB of reg, reg +- reg x 2 + tmpcy

temp +- temp – 1

mem,CL

temp +- CL, while temp 7′ 0, repeat this operation:tmpcy +-CY, CY +- MSB of (mem), (mem) +- (mem) x 2 + tmpcy temp +- temp – 1

1 1 0 1 0 0 1 W mod 0 1 0 mem 19/27 2-4
+ n

x u

reg, imm8

temp +- imm8, while temp 7′ 0,
repeat this operation: tmpcy +- CY, CY +- MSB of reg, reg +- reg x 2 + tmpcy temp +- temp – 1

1 1 OOOOOW1 1 0 1 0 reg 7+n

x u

mem, imm8

temp +- imm8, while temp 7’ 0, repeat this operation: tmpcy +-CY, CY +- MSB of (mem) (mem) +- (mem) x 2 + tmpcy temp +- temp – 1

1 1 0 0 0 0 0 W mod 0 1 0 mem 19/27 3-5
+ n
n: number of shifts

x u

m
0 z
~

Mnemonic Operand

RORC

reg, 1

Operation

Operation Code

No.of No.of

Flags

(“) )(

7 6 5 4 3 2 1 0 7 6 5 4 3 2 I 0 Clocks Bftes AC CT V P S Z

.p…

Rotate Instructions (cont)

tmpcy – CY, CY – LSB of reg

1 1 0 1 0 0 0 w 1 1 0 1 1 reg 2

x x

“‘

reg – reg + 2, MSB of reg – tmpcy

MSB of reg# bit following MSB of reg: V – 1

MSB of reg =bit following MSB of reg: V – 0

mem, 1 reg, CL

tmpcy – CY, CY – LSB of (mem) (mem) – (mem) + 2, MSB of (mem) MSB of (mem) ,e bit following MSB
of (mem): V – 1 MSB of (mem) = bit following MSB
of (mem): V – 0

tmpcy

temp – CL, while temp ,e 0, repeat this operation: tmpcy – CY, CY – LSB of reg, reg – reg + 2, MSB of reg – tmpcy, temp – temp -1

1 1 0 1 OOOWmod 0 1 1 mem 16/24 2-4

1 1 0 1 0 0 1 w 1 1 0 1 1 reg 7+n

x x x u

mem, CL

temp – CL, while temp ,e 0,
repeat this operalion;tmpcy – CY, CY – LSB of (mem), (mem) – (mem) + 2 MSB of (mem) – tmpcy, temp – temp – 1

1 1 0 1 0 0 1 W mod 0 1 1 mem 19/27 2-4
+ n

x u

reg, imm8

temp – imm8, while temp ,e O

1 1 OOOOOW1 1 0 1 1 reg 7+n

x u

0
I

repeat this operation:tmpcy – CV, CY – LSB of reg, reg – reg + 2 MSB of reg – tmpcy, temp – temp – 1

mem, imm8

temp – imm8, while temp ,e 0, repeat this operation:tmpcy – CY, CY +- LSB of (mem), (mem) – (mem) + 2 MSB of (mem) – tmpcy, temp – temp – 1

1 1 0 O 0 0 O W mod 0 1 1 mem 19/27 3-5
+ n
n: number of shifts

x u

Subroutine Control Instructions

CALL

near-proc

(SP-1, SP-2) – PC, SP-SP-2 PC-PC+disp

1 1 1 0 1 0 0 0

16/20 3

regptr16

(SP-1, SP-2)- PC, SP-SP-2 PC – reg ptr16

1 1 1 1 1 1 1 1 1 1 0 1 0 reg 14/18 2

memptr16

(SP-1, SP-2)- PC, SP-SP-2 PC +- (memptr16)

1 1 1 1 1 1 1 1 mod 0 1 0 mem 23/31 2-4

far-proc memptr32

(SP – 1, SP – 2) – PS, (SP – 3, SP – 4) – PC SP – SP – 4, PS – seg, PC – offset
(SP – 1, SP – 2) – PS, (SP – 3, SP – 4) +-PC SP – SP – 4, PS – (memptr32 + 2), PC – (memptr32)

100 11010

21/29 5

1 1 1 1 1 1 1 1 mod 0 1 1 mem 31/47 2-4

m
· – 0z ~

Mnemonic Operand

Operation

Operation Code

No. of ~ No. of

Flags

x()

7 6 5 4 3 2 1 0 7 6 5 4 3 2 I 0 Clocks · Bytes AC CY V P S Z

.0..,

Subroutine Control Instructions (cont)

RET

PC …… (SP+ 1. SP), SP …… SP+ 2

11000 0 11

I 15119 1

pop-value

PC …… (SP+ 1, SP)

1100 0 0 10

T 20124 3

SP …… SP+ 2, SP …… SP+ pop-value PC …… (SP+ 1, SP), PS …… (SP+ 3, SP+ 2)

1100 10 11

T I
21129 1

SP …… SP+ 4

pop-value

PC …… (SP+ 1, SP), PS …… (SP+ 3, SP+ 2) SP …… SP + 4, SP …… SP + pop-value

1100 10 10

24/32 3

PUSH

mem16

Stack Manipulation Instructions

(SP-1, SP – 2) …… (mem16), SP …… SP-2

1 1 1 1 1 1 1 1 mod 1 1 0 mem

T 18126 2-4

reg16

(SP – 1, SP – 2) …… reg16, SP+- SP – 2

0 1 0 1 0 reg

8/12

sreg

(SP- 1, SP- 2) …… sreg, SP …… SP – 2

OOOsreg 1 1 0

8/12

PSW

(SP-1, SP-2) +- PSW, SP +-SP-2

100 11100

8/12

Push registers on the stack

0 1 1 0 0 0 0 0

imm

(SP – 1, SP – 2) – imm, SP – SP – 2,

0 110 10s 0

When S = 1, sign extension

35/67 1

7/11

2-3

or 8/12

–l

POP

mem16

(mem16) …… (SP+ 1, SP), SP …… SP+ 2

reg16

reg16 …… (SP+ 1, SP), SP …… SP+ 2

1 0 0 0 1 1 1 1 mod 0 0 0 mem 0 1 0 1 1 reg

17/25 2-4
8/12 : 1

sreg

sreg …… (SP+ 1, SP) sreg : SS, DSO, DS1

0 0 0 sreg 1 1 1

SP +-SP+ 2

8/12 1 1

PREPARE

PSW
R
imm16, imm8

PSW +-(SP+ 1, SP), SP +-SP+2 Pop registers from the slack Prepare new stack frame

DISPOSE

Dispose of stack frame

1 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 11001000

8/12 l 1
.43/75 1 ! 4

·: imm8 = 0: 12/16

imm8 z1: 22 + 20 x (imm8 -1): Odd Address

18 + 12 X (imm8 – 1): Even Address

Il 1 1 0 0 1 0 0 1

6110

R R RRRR

Branch Instruction

near-label

PC- PC+ disp

short-label

PC …… PC + ext-disp8

regptr16

PC …… regptr16

memptr16

PC …… (memptr16)

1 1 1 0 1 0 0 1 111010 11 1 1 1 1 1 1 1 1 1 1 1 0 0 reg 1 1 1 1 1 1 1 1 mod 1 0 0 mem

I 12 I 12 I 11 I 20124

3 2 2 2-4

far-label memptr32

PS …… seg, PC …… offset PS …… (memptr32 + 2), PC …… (memptr32)

1110 10 10

-1 1 1 1 1 1 1 1 mod 1 0 1

mem

27/35

2-4

00
0 z
~

Mnemonic Operand

short-label

Operation
If V = 1, PC – PC + ext-disp8

Operation Code

No.of No.of

Flags

7 6 5 4 3 2 1 0 7 6 5 4 3 2 I 0 Clocks Bytes AC CYVPSZ

…x(“‘)
D

Conditional Brarn:h Instructions

:;1;;

0 1 1100 00

14/4

BNV

short-label

If V = 0, PC – PC + ext-disp8

0 1 1 1 0 0 0 1

14/4

BC, BL

short-label

If CY = 1, PC – PC + ext-disp8

011100 10

14/4

BNC,BNL short-label

If CY = 0, PC – PC + ext-disp8

011100 11

14/4

BE, BZ

short-label

If Z = 1, PC – PC + ext-disp8

0 1 1 1 0 1 0 0

14/4

BNE,BNZ BNH BH BN

short-label short-label short-label short-label

If Z = 0, PC – PC + ext-disp8 If CY OR Z = 1, PC – PC + ext-disp8 If CY OR Z = 0, PC – PC+ ext-disp8 If S = 1, PC – PC + ext-disp8

0 1 1 1 0 1 0 1 01110 110 0 1 1 1 0 1 1 1 0 1 1 1 10 00

14/4

short-label

If S = 0, PC – PC + ext-disp8

0 1 1 1 10 0 1

BPE

short-label

If P= 1, PC – PC + ext-disp8

011110 10

BPO

short-label

If P= 0, PC – PC + ext-disp8

011110 11

BLT

short-label

If S XOR V = 1, PC – PC+ ext-disp8

0 1 11 1100

BGE

short-label

If S XOR V = 0, PC – PC + ext-disp8

0 1 1 1 1 10 1

BLE

short-label

If (S XOR V) OR Z = 1, PC – PC+ ext-disp8

0 1 1 1 1 1 10

BGT

short-label

If (S XOR V) OR Z = 0, PC – PC+ ext-disp8

0 1 1 1 1 1 1 1

14/4

OBNZNE

short-label

cw-cw-1
If Z = 0 and CW # 0, PC – PC + ext-disp8

11 10 0 0 0 0

14/5

OBNZE

short-label

cw-cw-1
If Z = 1 and CW # 0, PC – PC + ext-disp8

1 1 10 0 0 0 1

14/5

OBNZ BCWZ

short-label short-label

cw-cw-1 If CW# 0, PC –
If CW = 0, PC –

PC+ ext-disp8 PC + ext-disp8

111000 10 111000 11

13/5

Interrupt Instructions

BRK

(SP – 1, SP – 2) – PSW, (SP – 3, SP – 4) – PS, (SP – 5, SP – 6) – PC, SP – SP – 6 IE-0,BRK-O PS – (15, 14), PC – (13, 12)

1100 1100

38/50 1

imm8

(SP – 1, SP – 2) – PSW, (SP – 3, SP – 4) – PS, 1 1 0 0 1 1 0 1

38/50 2

(#3)

(SP – 5, SP – 6) – PC, SP – SP – 6

IE-0,BRK-O

PC – (n x 4 + 1 n x 4)
PS – (n x 4 + 3, n x 4 + 2) n = imm8

rn
0 z

Mnemonic Operand BRKV

Operation

Operation Code

No. of No.of

Flags

Cx’l

7 6 5 4 3 2 I 0 7 6 5 4 3 2 I 0 Clocks Bytes AC CY V P S Z lnlerrupt Instructions (cont)

8s:
o;

When V = 1

1100 1110

40/52 1

(SP – 1, SP – 2) – PSW. (SP – 3, SP – 4) – PS,

(SP – 5, SP – 6) – PC, SP – SP – 6

IE-0, BRK-0

PS – (19, 18), PC – (17, 16)

RETI CH KIND

reg16, mem32

PC- (SP+ 1, SP), PS – (SP+ 3, SP+ 2),

1100 1111

PSW – (SP+ 5, SP+ 4), SP – SP+ 6

When (mem32) > reg16 or (mem32 -+- 2) < reg16

0 1 1 0 0 0 1 0 mod reg

(SP – 1, SP – 2) – PSW, (SP – 3, SP – 4) – PS,

(SP – 5, SP – 6) – PC, SP – SP – 6

IE – 0, BRK – 0, PS – (23, 22), PC – (21, 20)

27/39 1 R R R R R R
mem 53-56 2-4 /73-76 18/26

BR KEM

imm8

(SP – 1, SP – 2) – PSW, (SP – 3, SP – 4) – PS, 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 38/50 3 (SP – 5, SP – 6) – PC, SP – SP — 6 MD – 0, PC – (n x 4 + 1, n x 4)
PS – (n x 4 + 3, n x 4 + 2), n = imm8

CPU Control Instructions

HALT

CPU Halt

11 11 0 100

BUSLOCK

FP01

Ip-op

Bus Lock Prefix No Operation

1 1 1 1 0 0 0 0

1 1 0 1 1 x x x 1 1YYYZZZ 2

Ip-op, mem

data bus – (mem)

FP02

Ip-op

No Operation

1 1 0 1 1 X X X mod Y Y Y mem 11/15 2-4

x 0 1 1 0 0 1 1 1 1YYYZZZ 2

Ip-op, mem

data bus – (mem)

0 1 1 0 0 1 1 X mod Y Y Y mem 11/15 2-4

POLL

Poll and wait

100 110 11 n: number of times POLL pin is sampled

2 +Sn 1

NOP

No Operation

1 0 0 1 0 0 0 0

IE-0

111110 10

IE-1

11 1110 11

8080 Mode Instructions

RETEM

PC – (SP+ 1, SP), PS – (SP i” 3, SP+ 2), PSW – (SP+ 5, SP+ 4), SP – SP+ 6

1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 27/39 2 R R R R R R

CALLN

imm8

(SP – 1, SP – 2) – PSW, (SP – 3, SP – 4)

1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 38/58 3

– PS, (SP – 5, SP – 6) – PC, SP – SP – 6

MD -1. PC – (n x 4 + 1, n x 4)
PS – ( n x 4 + 3, n x 4 + 2), n = imm8

0 z

CX070116
Package Outline
40 pin DIP (Plastic)

SONY@

40 pin DIP (Ceramic)

Unit: mm

– 120-

Documents / Resources

SONY CXQ70116 16 Bit Microprocessor [pdf] User Guide
CXQ70116, CXQ70116 16 Bit Microprocessor, CXQ70116, 16 Bit Microprocessor, Bit Microprocessor, Microprocessor

References

User Manual

CXQ70116 16 Bit Microprocessor

Specifications

Product Usage Instructions

Description

Features

Pin Configuration (Top View)

Block Diagram

Pin Identification

Pin Functions

FAQ

1. How to connect IC pin?

2. What is the clock speed supported by the
microprocessor?

3. Can the CXQ70116 emulate an 8080 processor?

Documents / Resources

References

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