Intel FPGA Integer Arithmetic IP Cores User Guide

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1 FPGA Integer Arithmetic IP Cores

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FPGA Integer Arithmetic IP Cores

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Intel FPGA Integer Arithmetic IP Cores Mushandisi Wekushandisa
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1. Intel FPGA Integer Arithmetic IP Cores……………………………………………………………….. 5
2. LPM_COUNTER (Counter) IP Core……………………………………………………………………….. 7 2.1. Features ……………………………………………………………………………………………………… Verilog HDL Prototype………………………………………………………………………………….. 7 2.2. VHDL Component Declaration………………………………………………………………………….8 2.3. VHDL LIBRARY_USE Declaration……………………………………………………………………………………………………………………………………………………………… 8 2.4. Zviteshi……………………………………………………………………………………………………..9 2.5. Parameters…………………………………………………………………………………………………… 9
3. LPM_DIVIDE (Divider) Intel FPGA IP Core………………………………………………………….. 12 3.1. Features ………………………………………………………………………………………………………. 12 3.2. Verilog HDL Prototype………………………………………………………………………………… 12 3.3. VHDL Component Declaration……………………………………………………………………….. 13 3.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 13 3.5. Zviteshi……………………………………………………………………………………………………… 13 3.6. Parameters………………………………………………………………………………………………… 14
4. LPM_MULT (Multiplier) IP Core………………………………………………………………………………. 16 4.1. Features ………………………………………………………………………………………………………. 16 4.2. Verilog HDL Prototype………………………………………………………………………………… 17 4.3. VHDL Component Declaration……………………………………………………………………….. 17 4.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 17 4.5. Zviratidzo……………………………………………………………………………………………………… 18 4.6. Maparamita eStratix V, Arria V, Cyclone V, uye Intel Cyclone 10 LP Devices ……………… 18 4.6.1. General Tab……………………………………………………………………………………18 4.6.2. Zvakawanda 2 Tab………………………………………………………………………………… 19 4.6.3. Pipelining Tab………………………………………………………………………………… 19 4.7. Maparamita eIntel Stratix 10, Intel Arria 10, uye Intel Cyclone 10 GX Devices ……….. 20 4.7.1. General Tab……………………………………………………………………………………20 4.7.2. Zvakawanda 2 Tab………………………………………………………………………………… 20 4.7.3. Kupomba ………………………………………………………………………………………
5. LPM_ADD_SUB (Adder/Subtractor)…………………………………………………………………… 22 5.1. Features ………………………………………………………………………………………………………. 22 5.2. Verilog HDL Prototype………………………………………………………………………………… 23 5.3. VHDL Component Declaration……………………………………………………………………….. 23 5.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 23 5.5. Zviteshi……………………………………………………………………………………………………… 23 5.6. Parameters……………………………………………………………………………………………… 24
6. LPM_COMPARE (Muenzanisi)…………………………………………………………………………… 26 6.1. Features ………………………………………………………………………………………………………. 26 6.2. Verilog HDL Prototype…………………………………………………………………………………… 27 6.3. VHDL Component Declaration……………………………………………………………………….. 27 6.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 27 6.5. Zviteshi…………………………………………………………………………………………………… 27 6.6. Parameters………………………………………………………………………………………………… 28

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7. ALTECC (Kururamisa Kodhi: Encoder/Decoder) IP Core ……………………………………… 30.
7.1. ALTECC Encoder Features……………………………………………………………………………..31 7.2. Verilog HDL Prototype (ALTECC_ENCODER)…………………………………………………………. 32 7.3. Verilog HDL Prototype (ALTECC_DECODER)…………………………………………………………. 32 7.4. VHDL Component Declaration (ALTECC_ENCODER)…………………………………………………33 7.5. VHDL Component Declaration (ALTECC_DECODER)………………………………………………33 7.6. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 33 7.7. Encoder Ports…………………………………………………………………………………………… 33 7.8. Decoder Ports…………………………………………………………………………………………34 7.9. Encoder Parameters…………………………………………………………………………………… 34 7.10. Decoder Parameters …………………………………………………………………………………… 35
8. Intel FPGA Kuwanza Adder IP Core………………………………………………………………………… 36
8.1. Features ………………………………………………………………………………………………………. 37 8.1.1. Pre-adder………………………………………………………………………………….. 38 8.1.2. Systolic Delay Register……………………………………………………………………….. 40 8.1.3. Pre-load Constant…………………………………………………………………………… 43 8.1.4. Double Accumulator ……………………………………………………………………… 43
8.2. Verilog HDL Prototype………………………………………………………………………………… 44 8.3. VHDL Component Declaration……………………………………………………………………….. 44 8.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 44 8.5. Zviratidzo…………………………………………………………………………………………………… 44 8.6. Parameters……………………………………………………………………………………………… 47
8.6.1. General Tab…………………………………………………………………………………47 8.6.2. Extra Modes Tab…………………………………………………………………………….. 47 8.6.3. Multipliers Tab…………………………………………………………………………….. 49 8.6.4. Preadder Tab……………………………………………………………………………………. 51 8.6.5. Accumulator Tab…………………………………………………………………………….. 53 8.6.6. Systolic/Chainout Tab…………………………………………………………………………. 55 8.6.7. Pipelining Tab………………………………………………………………………………… 56
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core …………………… 57
9.1. Features ………………………………………………………………………………………………………. 57 9.2. Verilog HDL Prototype………………………………………………………………………………… 58 9.3. VHDL Component Declaration……………………………………………………………………….. 58 9.4. Zviteshi……………………………………………………………………………………………………… 59 9.5. Parameters………………………………………………………………………………………………… 59
10. ALTMULT_ACCUM (Wanza-Unganidze) IP Core………………………………………………… 61
10.1. Features ……………………………………………………………………………………………….. 62 10.2. Verilog HDL Prototype……………………………………………………………………………..62 10.3. VHDL Component Declaration………………………………………………………………………… 63 10.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………… Zviteshi………………………………………………………………………………………………………………………………………………………. 63 10.5. Parameters………………………………………………………………………………………………. 63
11. ALTMULT_ADD (Multiply-Adder) IP Core……………………………………………………………..69
11.1. Features ……………………………………………………………………………………………….. 71 11.2. Verilog HDL Prototype………………………………………………………………………………..72 11.3. VHDL Component Declaration………………………………………………………………………… 72 11.4. VHDL LIBRARY_USE Declaration………………………………………………………………………

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11.5. Zviteshi………………………………………………………………………………………………………………………………………………………. 72 11.6. Parameters………………………………………………………………………………………………. 73
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core……………………………………………… 86 12.1. Complex Multiplication………………………………………………………………………………. 86 12.2. Canonical Representation…………………………………………………………………………… 87 12.3. Conventional Representation ………………………………………………………………………. 87 12.4. Features……………………………………………………………………………………………….. 88 12.5. Verilog HDL Prototype………………………………………………………………………………..88 12.6. VHDL Component Declaration……………………………………………………………………… 89 12.7. VHDL LIBRARY_SHANDISA Chiziviso…………………………………………………………………………89 12.8. Zviratidzo………………………………………………………………………………………………………. 89 12.9. Parameters………………………………………………………………………………………………. 90
13. ALTSQRT (Integer Square Root) IP Core……………………………………………………………… Features ……………………………………………………………………………………………….. 92 13.1. Verilog HDL Prototype………………………………………………………………………………..92 13.2. VHDL Component Declaration………………………………………………………………………… 92 13.3. VHDL LIBRARY_SHANDISA Chiziviso…………………………………………………………………………93 13.4. Zviteshi………………………………………………………………………………………………………………………………………………………. 93 13.5. Parameters………………………………………………………………………………………………. 93
14. PARALLEL_ADD (Parallel Adder) IP Core……………………………………………………….. 95 14.1. Nyaya……………………………………………………………………………………………….95 14.2. Verilog HDL Prototype……………………………………………………………………………..95 14.3. VHDL Component Declaration………………………………………………………………………… 96 14.4. VHDL LIBRARY_SHANDISA Chiziviso…………………………………………………………………………96 14.5. Zviteshi………………………………………………………………………………………………………………………………………………………. 96 14.6. Parameters………………………………………………………………………………………………. 97
15. Integer Arithmetic IP Cores User Guide Document Archives ………………………………… 98
16. Gwaro Revision Nhoroondo yeIntel FPGA Integer Arithmetic IP Cores User Guide…. 99

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1. Intel FPGA Integer Arithmetic IP Cores

Unogona kushandisa Intel® FPGA integer IP cores kuita masvomhu mudhizaini yako.

Aya mabasa anopa akanyatsoita logic synthesis uye kusetwa kwechishandiso pane kukodha mabasa ako. Iwe unogona kugadzirisa iyo IP cores kuti ienderane nedhizaini yako zvinodiwa.

Intel integer arithmetic IP cores yakakamurwa kuita zvikamu zviviri zvinotevera: · Raibhurari yeparameterized modules (LPM) IP cores · Intel-specific (ALT) IP cores.

Tafura inotevera inonyora nhamba yakazara arithmetic IP cores.

Tafura 1.

Rondedzero yeIP Cores

IP Cores

LPM IP cores

LPM_COUNTER

LPM_DIVIDE

LPM_MULT

LPM_ADD_SUB
LPM_COMPARE
Intel-specific (ALT) IP cores ALTECC

Basa Kupfuuraview Counter Divider Multiplier
Adder kana subtractor Comparator
ECC Encoder/Decoder

Inotsigirwa Chishandiso
Arria® II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone® IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP,
Intel Cyclone 10 GX, MAX® II, MAX V, MAX 10, Stratix® IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V,Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V yakaenderera…

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

ISO 9001:2015 Yakanyoreswa

1. Intel FPGA Integer Arithmetic IP Cores 683490 | 2020.10.05

IP Cores Intel FPGA Kuwanza Adder kana ALTERA_MULT_ADD ALTMEMMULT
ALTMULT_ACCUM ALTMULT_ADD ALTMULT_COMPLEX
ALTSQRT
PARALLEL_ADD

Basa Kupfuuraview Multiplier-Adder
Memory-based Constant Coefficient Multiplier
Multiplier-Accumulator Multiplier-Adder
Complex Multiplier
Integer Square-Root
Parallel Adder

Inotsigirwa Chishandiso
Arria V, Stratix V, Cyclone V, Intel Stratix 10, Intel Arria 10, Intel Cyclone
10 GX
Arria II GX, Arria II GZ, Arria V, Intel Arria 10 (Intel Quartus® Prime Standard Edition), Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 LP, MAX II, MAX V, MAX 10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX,Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Intel Arria 10, Arria V, Arria V GZ, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 GX, Intel Cyclone 10 LP, MAX 10, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP,Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V

Related Information
· Intel FPGAs uye Programmable Devices Release Notes
· Nhanganyaya kuIntel FPGA IP Cores Inopa rumwe ruzivo nezve Intel FPGA IP Cores.
· Inoyangarara-Point IP Cores Mushandisi Yekushandisa Inopa rumwe ruzivo nezve Intel FPGA Inoyangarara-Point IP cores.
· Nhanganyaya kuIntel FPGA IP Cores Inopa ruzivo rwese nezvese Intel FPGA IP cores, kusanganisira parameterizing, kugadzira, kusimudzira, uye kutevedzera IP cores.
Kugadzira Shanduro-Yakazvimirira IP uye Qsys Simulation Scripts Gadzira zvinyorwa zvekutevedzera zvisingade zvigadziriso zvemaoko zvesoftware kana IP vhezheni yekuvandudza.
· Project Management Yakanakisa Maitiro Madhiraivha ekutungamira kwakanaka uye kutakurika kweprojekiti yako uye IP files.
· Integer Arithmetic IP Cores User Guide Document Archives iri papeji 98 Inopa runyoro rwemadhairekitori evashandisi veshanduro dzakapfuura dzeInteger Arithmetic IP cores.

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2. LPM_COUNTER (Counter) IP Core

Mufananidzo 1.

Iyo LPM_COUNTER IP core ibhinari counter inogadzira macounter, pasi pasi uye kumusoro kana pasi macounter ane zvinobuda zvinosvika 256 bits zvakafara.

Nhamba inotevera inoratidza madoko eLPM_COUNTER IP musimboti.

LPM_COUNTER Zviteshi

LPM_COUNTER

ssclr sload seti data[]

q[]

kuvandudzwa

cout

aclr aload asset

clk_en cnt_en cin
inst

2.1. Zvimiro
Iyo LPM_COUNTER IP core inopa zvinotevera: · Inogadzira kumusoro, pasi, uye kumusoro/pasi makaunda · Inogadzira anotevera marudzi emakaunda:
-Plain bhinari- iyo counter increments inotangira pazero kana kudzikiswa kubva pa255
- Modulus- iyo counter increments kune kana kudzikisira kubva pamutengo wemodulus inotsanangurwa nemushandisi uye inodzokorora
· Inotsigira sarudzo synchronous yakajeka, kuremedza, uye kuseta zviteshi zvekupinza · Inotsigira sarudzo asynchronous yakajeka, kutakura, uye kuseta zviteshi zvekupinza · Inotsigira sarudzo yekuverenga gonesa uye wachi inogonesa madoko ekupinza · Inotsigira sarudzo yekutakura uye yekutakura-kunze madoko

ISO 9001:2015 Yakanyoreswa

2. LPM_COUNTER (Counter) IP Core
683490 | 2020.10.05
2.2. Verilog HDL Prototype
Iyi inotevera Verilog HDL prototype iri muVerilog Dhizaini File (.v) lpm.v mune edasynthesis directory.
module lpm_counter (q, data, wachi, cin, cout, clk_en, cnt_en, updown, aset, aclr, aload, sset, sclr, sload, eq); parameter lpm_type = "lpm_counter"; parameter lpm_width = 1; parameter lpm_modulus = 0; parameter lpm_direction = "USINA KUSHANDISWA"; parameter lpm_avalue = "USINA KUSHANDISWA"; parameter lpm_svalue = "USINA KUSHANDISWA"; parameter lpm_pvalue = "USINA KUSHANDISWA"; parameter lpm_port_updown = "PORT_CONNECTIVITY"; parameter lpm_hint = "USINA KUSHANDISWA"; kubuda [lpm_width-1:0] q; output cout; kubuda [15:0] eq; input cin; kuisa [lpm_width-1:0] data; wachi yekupinda, clk_en, cnt_en, kumusoro pasi; input asset, aclr, aload; kuisa sset, sclr, sload; endmodule
2.3. VHDL Chikamu Chiziviso
Iyo VHDL chikamu chiziviso chiri muVHDL Dhizaini File (.vhd) LPM_PACK.vhd mune libraryvhdllpm directory.
component LPM_COUNTER generic ( LPM_WIDTH : natural; LPM_MODULUS : natural := 0; LPM_DIRECTION : string := "USUSED"; LPM_AVALUE : tambo := "isina KUSHANDISWA"; LPM_SVALUE : tambo := "USINA KUSHANDISWA"; LPM_PORTIVPD ; LPM_PVALUE : string := "USINA KUSHANDISWA"; LPM_TYPE : string := L_COUNTER; LPM_HINT : string := "USUSED"); port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0):= (OTHERS =>
'0'); WACHI: in std_logic; CLK_EN : in std_logic := '1'; CNT_EN : in std_logic := '1'; UPDOWN : in std_logic := '1'; SLOAD : in std_logic := '0'; SSET : in std_logic := '0'; SCLR : in std_logic := '0'; ALOAD : in std_logic := '0'; ASET : in std_logic := '0'; ACLR : in std_logic := '0'; CIN : in std_logic := '1'; COUT : out std_logic := '0'; Mubvunzo: kunze std_logic_vector (LPM_WIDTH-1 kusvika 0); EQ: kunze std_logic_vector (15 downto 0));
end component;

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2. LPM_COUNTER (Counter) IP Core 683490 | 2020.10.05

2.4. VHDL LIBRARY_USE Declaration
VHDL LIBRARY-SHANDISA chiziviso hachidiwe kana ukashandisa VHDL Component Declaration.
LIBRARY lpm; SHANDISA lpm.lpm_components.all;

2.5. Zviteshi

Matafura anotevera anonyora ekuisa uye kubuda madoko eLPM_COUNTER IP musimboti.

Tafura 2.

LPM_COUNTER Input Ports

Port Name

Zvinodiwa

Tsanangudzo

data[]

Aihwa

Parallel data kuisa kune iyo counter. Saizi yenzvimbo yekupinza inotsamira pane LPM_WIDTH parameter kukosha.

wachi

Ehe

Positive-edge-triggered clock input.

clk_en

Aihwa

Wachi inogonesa kupinza kuti igonese zviitiko zvesynchronous. Kana ikasiiwa, kukosha kwekutanga ndeye 1.

cnt_en

Aihwa

Verenga gonesa kuisa kudzima kuverenga kana yakanzi yakaderera pasina kukanganisa sload, sset, kana sclr. Kana ikasiiwa, kukosha kwekutanga ndeye 1.

kuvandudzwa

Aihwa

Inodzora nzira yekuverenga. Kana yanzi yakakwira (1), nhamba yekuverenga inokwira, uye kana yanzi yadzikira (0), nhamba yekuverenga iri pasi. Kana iyo LPM_DIRECTION parameter ikashandiswa, chiteshi chepamusoro hachigone kubatana. Kana LPM_DIRECTION ikasashandiswa, chinokwidibira chinogoneka. Kana ikasiiwa, kukosha kwekutanga kuri kumusoro (1).

cin

Aihwa

Pinda-mukati kune yakaderera-odha bit. Kuma counters, maitiro ekuisa cin ndee

zvakafanana nemaitiro eiyo cnt_en yekupinza. Kana ikasiiwa, kukosha kwekutanga ndeye 1

(VCC).

aclr

Aihwa

Asynchronous yakajeka kuisa. Kana zvese aset uye aclr zvikashandiswa uye zvichinzi, aclr inodarika aset. Kana ikasiiwa, kukosha kweiyo 0 (yakaremara).

asset

Aihwa

Asynchronous set input. Inotsanangura q[] zvabuda sema 1 ese, kana kukosha kwakatsanangurwa neLPM_AVALUE parameter. Kana zvese zviri zviviri asset neaclr zviteshi zvikashandiswa uye zvichinzi, kukosha kweaclr port kunodarika kukosha kweaset port. Kana ikasiiwa, kukosha kweiyo 0, kwakavharwa.

aload

Aihwa

Asynchronous load yekupinda iyo asynchronously inotakura iyo counter ine kukosha pane iyo data yekuisa. Kana chiteshi chekutakura chikashandiswa, data[] chiteshi chinofanira kubatana. Kana ikasiiwa, kukosha kweiyo 0, kwakavharwa.

sclr

Aihwa

Synchronous clear input inobvisa kaunda pane inotevera inoshanda wachi. Kana zvese sset nesclr zviteshi zvikashandiswa uye zvichinzi, kukosha kwe sclr port kunodarika kukosha kwesset port. Kana ikasiiwa, kukosha kweiyo 0, kwakavharwa.

sset

Aihwa

Synchronous set input inoseta kaunda pamucheto unotevera wewachi. Inotsanangura kukosha kwe q zvabuda sema 1 ese, kana kukosha kwakatsanangurwa neLPM_SVALUE parameter. Kana ese ari maviri sset uye sclr ports akashandiswa uye akasimbiswa,
kukosha kwe sclr port kunodarika kukosha kwe sset port. Kana ikasiiwa, kukosha kweiyo 0 (yakaremara).

sload

Aihwa

Synchronous load input inotakura kaunda nedata[] pamupendero wewachi inotevera. Kana iyo sload port ichishandiswa, data[] port inofanirwa kubatana. Kana ikasiiwa, kukosha kweiyo 0 (yakaremara).

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2. LPM_COUNTER (Counter) IP Core 683490 | 2020.10.05

Tafura 3.

LPM_COUNTER Zviteshi zvekubuda

Port Name

Zvinodiwa

Tsanangudzo

q[]

Aihwa

Data yakabuda kubva pakaunda. Saizi yechiteshi chinobuda zvinoenderana neiyo

LPM_WIDTH parameter value. Pamwe q[] kana imwe chete ye eq[15..0] zviteshi

inofanira kunge yakabatana.

eq[15..0]

Aihwa

Counter decode kubuda. Iyo eq[15..0] chiteshi haisvikike muparameter mupepeti nekuti parameter inongotsigira AHDL.
Iyo q[] chiteshi kana eq[] chiteshi inofanira kubatana. Kusvika kune c eq ports inogona kushandiswa (0 <= c <= 15). Chete gumi nenhanhatu dzakaderera kuverenga dzakatemwa. Kana kukosha kwekuverenga kuri c, iyo eqc inobuda inosimbiswa yakakwira (16). For example, kana kuverenga kuri 0, eq0 = 1, kana kuverenga kuri 1, eq1 = 1, uye kana kuverenga kuri 15, eq 15 = 1. Decoded inobuda yekuverenga kukosha kwe16 kana kupfuura inoda decoding yekunze. Izvo eq[15..0] zvinobuda zvine asynchronous kune q[] zvakabuda.

cout

Aihwa

Chengetedza kunze kwekaunda yeMSB bit. Inogona kushandiswa kubatanidza kune imwe counter kugadzira counter hombe.

2.6. Paramita

Tafura inotevera inoronga maparameter eiyo LPM_COUNTER IP core.

Tafura 4.

LPM_COUNTER Parameters

Parameter Zita

Type

LPM_WIDTH

Integer

LPM_DIRECTION

String

LPM_MODULUS LPM_AVALUE

Integer
Integer/ Tambo

LPM_SVALUE LPM_HINT

Integer/ Tambo
String

LPM_TYPE

String

Inodiwa Hongu Kwete Kwete Kwete
Kwete Kwete
Aihwa

Tsanangudzo
Inotsanangura upamhi hwe data[] uye q[] zviteshi, kana zvichishandiswa.
Mitemo iri UP, PASI, uye USINA KUSHANDISWA. Kana iyo LPM_DIRECTION parameter ikashandiswa, chiteshi chepamusoro hachigone kubatana. Kana iyo chiteshi chepamusoro chisina kubatana, iyo LPM_DIRECTION parameter default kukosha ndeye UP.
The maximum count, plus one. Huwandu hwematunhu akasiyana mukutenderera kwekaunda. Kana kukosha kwekuremerwa kwakakura kupfuura LPM_MODULUS parameter, maitiro epakaunda haana kutaurwa.
Ukoshi hwenguva dzose hunoiswa kana aset ichinzi yakakwira. Kana kukosha kwataurwa kwakakura pane kana kuenzana na , hunhu hwekaunda ndeye isina kutsanangurwa (X) logic level, kupi iri LPM_MODULUS, kana iripo, kana 2 ^ LPM_WIDTH. Intel inokurudzira kuti utaure kukosha uku senhamba yedesimali yeAHDL magadzirirwo.
Ukoshi hwenguva dzose hunoiswa pamupendero unokwira wewachi chiteshi kana sset port yanzi yakakwirira. Intel inokurudzira kuti utaure kukosha uku senhamba yedesimali yeAHDL magadzirirwo.
Paunosimbisa raibhurari yeparameterized modules (LPM) basa muVHDL Dhizaini File (.vhd), unofanira kushandisa LPM_HINT parameter kutsanangura Intel-specific parameter. For example: LPM_HINT = “CHAIN_SIZE = 8, ONE_INPUT_IS_CONSTANT = YES”
Iko kukosha kwekutanga ndeye UNUSED.
Inozivisa raibhurari yeparameterized modules (LPM) zita rechikamu muVHDL dhizaini files.
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Parameter Zita INTENDED_DEVICE_FAMILY CARRY_CNT_EN
LABWIDE_SCLR
LPM_PORT_UPDOWN

Type String String
String
String

Inodiwa Nha
Aihwa
Aihwa

Tsanangudzo
Iyi parameter inoshandiswa kuenzanisa uye maitiro ekufananidza zvinangwa. Iyi parameter inoshandiswa kuenzanisa uye maitiro ekufananidza zvinangwa. Iyo parameter editor inoverenga kukosha kweiyi parameter.
Intel-specific parameter. Unofanira kushandisa LPM_HINT parameter kutsanangura CARRY_CNT_EN parameter muVHDL dhizaini. files. Values ndeye SMART, ON, OFF, uye USUSED. Inogonesa basa reLPM_COUNTER kuparadzira chiratidzo che cnt_en kuburikidza necheni yekutakura. Dzimwe nguva, iyo CARRY_CNT_EN parameter kuseta inogona kuita kakukanganisa kumhanya, saka ungangoda kuidzima. Iko kukosha kweiyo SMART, iyo inopa yakanakisa kutengeserana pakati pehukuru nekumhanya.
Intel-specific parameter. Unofanira kushandisa LPM_HINT parameter kutsanangura LABWIDE_SCLR parameter muVHDL design. files. Values ndeye ON, OFF, kana USINA KUSHANDISWA. Iko kukosha kwekutanga ndeye ON. Inokutendera kuti udzime kushandiswa kweiyo LABwide sclr chimiro chinowanikwa mumhuri dzakasakara dzemidziyo. Kudzima sarudzo iyi kunowedzera mikana yekushandisa zvizere maLABs akazadzwa zvishoma, uye nekudaro zvinogona kubvumira density yepamusoro kana SCLR isingashande kuLAB yakazara. Iyi parameter inowanikwa yekudzokera kumashure, uye Intel inokurudzira kuti usashandise iyi parameter.
Inotsanangura mashandisirwo enzvimbo yekuisa kumusoro. Kana yasiiwa kukosha kwekutanga ndiko PORT_CONNECTIVITY. Kana kukosha kwechiteshi kwaiswa kuPORT_USED, chiteshi chinobatwa sekushandiswa. Kana kukosha kwechiteshi kwaiswa kuPORT_UNUSED, chiteshi chinotorwa sechisina kushandiswa. Kana kukosha kwechiteshi kwaiswa kuPORT_CONNECTIVITY, kushandiswa kwechiteshi kunotariswa nekutarisa kubatana kwechiteshi.

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3. LPM_DIVIDE (Divider) Intel FPGA IP Core

Mufananidzo 2.

Iyo LPM_DIVIDE Intel FPGA IP musimboti inoshandisa divider kugovera kukosha kwenhamba yekupinda nedhinominator yekuisa kukosha kuburitsa quotient uye yasara.

Nhamba inotevera inoratidza madoko eLPM_DIVIDE IP musimboti.

LPM_DIVIDE Zviteshi

LPM_DIVIDE

nhamba[] denom[] wachi

quotient[]sara[]

clken aclr

inst

3.1. Zvimiro
Iyo LPM_DIVIDE IP core inopa zvinotevera zvinhu: · Inogadzira divider inopatsanura kukosha kwekupinza nhamba nedhinominator.
kukosha kuburitsa quotient uye yasara. · Inotsigira data hupamhi hwe1 bits. · Inotsigira yakasainwa uye isina kusaina data inomiririra fomati yeese manhamba
uye denominator values. · Inotsigira nzvimbo kana kumhanya optimization. · Inopa sarudzo yekutsanangura yasara yakanaka inobuda. · Inotsigira pipelining inogadziriswa inobuda latency. · Inotsigira sarudzo asynchronous yakajeka uye wachi inogonesa madoko.

3.2. Verilog HDL Prototype
Iyi inotevera Verilog HDL prototype iri muVerilog Dhizaini File (.v) lpm.v mune edasynthesis directory.
module lpm_divide ( quotient, sara, nhamba, denom, wachi, clken, aclr); parameter lpm_type = "lpm_divide"; parameter lpm_widthn = 1; parameter lpm_widthd = 1; parameter lpm_nrepresentation = "UNSIGNED"; parameter lpm_drepresentation = "UNSIGNED"; parameter lpm_remainderpositive = "CHOKWADI"; parameter lpm_pipeline = 0;

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3. LPM_DIVIDE (Divider) Intel FPGA IP Core 683490 | 2020.10.05

parameter lpm_hint = "USINA KUSHANDISWA"; wachi yekupinda; input clken; input aclr; kuisa [lpm_widthn-1:0] nhamba; kuisa [lpm_widthd-1:0] denom; kubuda [lpm_widthn-1:0] quotient; kubuda [lpm_widthd-1:0] kusara; endmodule

3.3. VHDL Chikamu Chiziviso
Iyo VHDL chikamu chiziviso chiri muVHDL Dhizaini File (.vhd) LPM_PACK.vhd mune libraryvhdllpm directory.
chikamu LPM_DIVIDE generic (LPM_WIDTHN : natural; LPM_WIDTHD : natural;
LPM_NREPRESENTATION : string := "UNSIGNED"; LPM_DREPRESENTATION : string := "UNSIGNED"; LPM_PIPELINE : natural := 0; LPM_TYPE : string := L_DIVIDE; LPM_HINT : tambo := "USINA KUSHANDISWA"); port (NUMER : in std_logic_vector(LPM_WIDTHN-1 downto 0); DENOM : in std_logic_vector(LPM_WIDTHD-1 downto 0); ACLR : in std_logic:= '0'; CLOCK : in std_logic := '0 logic: LK : := '1'; QUOTIENT : out std_logic_vector(LPM_WIDTHN-1 downto 0); REMAIN : out std_logic_vector(LPM_WIDTHD-1 downto 0)); end component;

3.4. VHDL LIBRARY_USE Declaration
VHDL LIBRARY-SHANDISA chiziviso hachidiwe kana ukashandisa VHDL Component Declaration.
LIBRARY lpm; SHANDISA lpm.lpm_components.all;

3.5. Zviteshi

Matafura anotevera anoronga zvekupinza uye zvinobuda zveLPM_DIVIDE IP core.

Tafura 5.

LPM_DIVIDE Input Ports

Port Name

Zvinodiwa

nhamba[]

Ehe

denom[]

Ehe

Tsanangudzo
Kuiswa kwenhamba yedata. Saizi yenzvimbo yekupinza inotsamira pane LPM_WIDTHN parameter kukosha.
Denominator data input. Saizi yenzvimbo yekupinza inotsamira pane LPM_WIDTHD parameter kukosha.
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Port Name wachi clken
aclr

Inodiwa Nha
Aihwa

Tsanangudzo
Kuisa wachi yekushandiswa kwepaipi. Kune LPM_PIPELINE ma values asiri 0 (default), wachi inofanira kugoneswa.
Wachi inogonesa kushandiswa kwepaipi. Kana iyo clken port ichinzi yakakwira, kupatsanurwa kunoitika. Kana chiratidzo chiri pasi, hapana kushanda kunoitika. Kana ikasiiwa, kukosha kwekutanga ndeye 1.
Asynchronous clear port inoshandiswa chero nguva kuseta pombi kune ese '0's asynchronously kune yekuisa wachi.

Tafura 6.

LPM_DIVIDE Zviteshi zvekubuda

Port Name

Zvinodiwa

Tsanangudzo

quotient[]

Ehe

Data kubuda. Saizi yechiteshi chinobuda zvinoenderana neLPM_WIDTHN

parameter value.

sara[]

Ehe

Data kubuda. Saizi yechiteshi chinobuda zvinoenderana neLPM_WIDTHD

parameter value.

3.6. Paramita

Tafura inotevera inonyora maparamendi eLPM_DIVIDE Intel FPGA IP musimboti.

Parameter Zita

Type

Zvinodiwa

Tsanangudzo

LPM_WIDTHN

Integer

Ehe

Inotsanangura upamhi hwenhamba[] uye

quotient[] ports. Hwaro 1 kusvika 64.

LPM_WIDTHD

Integer

Ehe

Inotsanangura upamhi hwedenom[] uye

sarai[] zviteshi. Hwaro 1 kusvika 64.

LPM_NREPRESENTATION LPM_DREPRESENTATION

String String

Aihwa

Saina inomiririra yeinopinza nhamba.

Hunhu AKASAIWA uye HAZVISINA KUSINA. Kana izvi

parameter yakaiswa kuti SIGNED, iyo divider

inodudzira nhamba[] yekupinda seyakasainwa maviri

mubatsiri.

Aihwa

Saina inomiririra yeinopinza denominator.

Hunhu AKASAIWA uye HAZVISINA KUSINA. Kana izvi

parameter yakaiswa kuti SIGNED, iyo divider

inoturikira dhinom[] semasainwa maviri

mubatsiri.

LPM_TYPE

String

Aihwa

Inozivisa raibhurari yeparameterized

modules (LPM) zita rechikamu muVHDL dhizaini

files (.vhd).

LPM_HINT

String

Aihwa

Paunosimudzira raibhurari ye

parameterized modules (LPM) basa mune a

VHDL Dhizaini File (.vhd), unofanira kushandisa iyo

LPM_HINT parameter kutsanangura Intel-

chaiyo parameter. For example: LPM_HINT

= “CHAIN_SIZE = 8,

ONE_INPUT_IS_CONSTANT = HONGU” The

default value is UNUSED.

LPM_REMAINDERPOSITIVE

String

Aihwa

Intel-specific parameter. Unofanira kushandisa

LPM_HINT parameter kutsanangura iyo

LPM_REMAINDERPOSITIVE parameter mukati

VHDL dhizaini files. Mitemo iCHOKWADI kana NHEMA.

Kana iyi parameter yakaiswa kuti TRUE, ipapo iyo

kukosha kwechasara[] chiteshi chinofanira kunge chakakura

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Parameter Zita

Type

MAXIMIZE_SPEED

Integer

LPM_PIPELINE

Integer

INTENDED_DEVICE_FAMILY SKIP_BITS

String Integer

Inodiwa Nha
Kwete Kwete Kwete

Tsanangudzo
kupfuura kana kuenzana ne zero. Kana iyi parameter ikaiswa kuti TRUE, saka kukosha kweyasara[] chiteshi iti zero, kana kukosha ichiratidzo chimwechete, chakanaka kana chakaipa, sekukosha kwenhamba yechiteshi. Kuti uderedze nharaunda uye uvandudze kumhanya, Intel inokurudzira kuseta iyi paramende kune TRUE mumashandisirwo apo inosara inofanirwa kuve yakanaka kana kuti yasara isina kukosha.
Intel-specific parameter. Unofanira kushandisa LPM_HINT parameter kutsanangura MAXIMIZE_SPEED parameter muVHDL dhizaini. files. Mitemo ndeye [0..9]. Kana ikashandiswa, iyo Intel Quartus Prime software inoedza kukwidziridza imwe muenzaniso yeLPM_DIVIDE basa rekumhanyisa kwete kuchinjika, uye inodarika kuseta kweiyo Optimization Technique logic sarudzo. Kana MAXIMIZE_SPEED isina kushandiswa, kukosha kweOptimization Technique sarudzo ndiyo inoshandiswa pachinzvimbo. Kana kukosha kwe MAXIMIZE_SPEED kuri 6 kana kudarika, Compiler inogonesa LPM_DIVIDE IP core yekumhanya zvakanyanya nekushandisa cheni dzekutakura; kana kukosha kuri 5 kana zvishoma, mugadziri anoshandisa dhizaini pasina cheni dzekutakura.
Inotsanangura huwandu hwemawachi ekutenderera kwakabatana nequotient[] uye kusara[] zvabuda. Kukosha kwe zero (0) kunoratidza kuti hapana latency iripo, uye kuti basa rakabatana rakaitwa. Kana ikasiiwa, kukosha kweiyo 0 (isina pipelined). Haukwanise kudoma kukosha kweLPM_PIPELINE parameter iri pamusoro peLPM_WIDTHN.
Iyi parameter inoshandiswa kuenzanisa uye maitiro ekufananidza zvinangwa. Iyo parameter editor inoverenga kukosha kweiyi parameter.
Inobvumira kuti pave nekunyatsoita kupatsanurwa kwechidimbu kukwenenzvera kukwenenzvera pane inotungamira mabhiti nekupa huwandu hweinotungamira GND kune LPM_DIVIDE IP core. Taura nhamba yekutungamira GND pane quotient inobuda kune iyi parameter.

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4. LPM_MULT (Multiplier) IP Core

Mufananidzo 3.

Iyo LPM_MULT IP musimboti inoshandisa mupupuri kuti iwanze maviri ekuisa data kukosha kugadzira chigadzirwa sekubuda.

Iyi inotevera nhamba inoratidza madoko eLPM_MULT IP musimboti.

LPM_Mult Ports

LPM_MULT dataa yewachi[] mhedzisiro[] datab[] aclr/sclr clken
inst

Ruzivo Rwunofambidzana Mamiriro ezvinhu ari papeji 71

4.1. Zvimiro
Iyo LPM_MULT IP musimboti inopa zvinhu zvinotevera: · Inogadzira inowanza iyo inowanza maviri ekuisa data kukosha · Inotsigira data hupamhi hwe1 bits · Inotsigira yakasainwa uye isina kusaina yekumiririra data fomati · Inotsigira nzvimbo kana kukurumidza optimization · Inotsigira pipelining ine configurable inobuda latency · Inopa sarudzo yekushandisa mune yakatsaurirwa dhijitari chiratidzo chekugadzirisa (DSP)
block circuitry kana logic elements (LEs) Cherekedza: Paunenge uchivaka zviwanziri zvakakura kupfuura saizi inotsigirwa nekuzvarwa panogona/
ichave chiitiko chekuita chinobva mukudonha kwemabhuroko eDSP. · Inotsigira sarudzo asynchronous yakajeka uye wachi inogonesa kupinza madoko · Inotsigira sarudzo synchronous yakajeka yeIntel Stratix 10, Intel Arria 10 uye Intel Cyclone 10 GX zvishandiso.

ISO 9001:2015 Yakanyoreswa

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05
4.2. Verilog HDL Prototype
Iyi inotevera Verilog HDL prototype iri muVerilog Dhizaini File (.v) lpm.v mune edasynthesis directory.
module lpm_mult ( mhedzisiro, dataa, datab, sum, wachi, clken, aclr ) parameter lpm_type = "lpm_mult"; parameter lpm_widtha = 1; parameter lpm_widthb = 1; parameter lpm_widths = 1; parameter lpm_widthp = 1; parameter lpm_representation = "UNSIGNED"; parameter lpm_pipeline = 0; parameter lpm_hint = "USINA KUSHANDISWA"; wachi yekupinda; input clken; input aclr; kuisa [lpm_widtha-1:0] dataa; kuisa [lpm_widthb-1:0] datab; kuisa [lpm_widths-1:0] sum; kubuda [lpm_widthp-1:0] mhedzisiro; endmodule
4.3. VHDL Chikamu Chiziviso
Iyo VHDL chikamu chiziviso chiri muVHDL Dhizaini File (.vhd) LPM_PACK.vhd mune libraryvhdllpm directory.
chikamu LPM_MULT generic ( LPM_WIDTHA : natural; LPM_WIDTHB : natural; LPM_WIDTHS : natural := 1; LPM_WIDTHP : natural;
LPM_REPRESENTATION : string := "UNSIGNED"; LPM_PIPELINE : natural := 0; LPM_TYPE: tambo := L_MULT; LPM_HINT : tambo := "USINA KUSHANDISWA"); port ( DATAA : in std_logic_vector (LPM_WIDTHA-1 downto 0); DATAB : in std_logic_vector (LPM_WIDTHB-1 downto 0); ACLR : in std_logic:= '0'; CLOCK : in std_logic := '0 logic: CLOCK : in std_logic: := '1'; SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0'); RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0)); end component;
4.4. VHDL LIBRARY_USE Declaration
VHDL LIBRARY-SHANDISA chiziviso hachidiwe kana ukashandisa VHDL Component Declaration.
LIBRARY lpm; SHANDISA lpm.lpm_components.all;

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4.5. Signals

Tafura 7.

LPM_MULT Input Signals

Zita rechiratidzo

Zvinodiwa

Tsanangudzo

data[]

Ehe

Kuiswa kwedata.

Kune Intel Stratix 10, Intel Arria 10, uye Intel Cyclone 10 GX zvishandiso, saizi yechiratidzo chekuisa inoenderana neiyo Dataa upamhi paramende kukosha.

Kune ekare uye Intel Cyclone 10 LP zvishandiso, saizi yechiratidzo chekuisa inoenderana neLPM_WIDTHA paramende kukosha.

datab[]

Ehe

Kuiswa kwedata.

Kune Intel Stratix 10, Intel Arria 10, uye Intel Cyclone 10 GX zvishandiso, saizi yechiratidzo chekuisa inoenderana neiyo Datab upamhi paramende kukosha.

Kune ekare uye Intel Cyclone 10 LP zvishandiso, saizi yechiratidzo chekuisa inotsamira

paLPM_WIDTHB parameter value.

wachi

Aihwa

Kuisa wachi yekushandiswa kwepaipi.

Kune ekare uye Intel Cyclone 10 LP zvishandiso, wachi chiratidzo chinofanirwa kugoneswa kune LPM_PIPELINE kukosha kunze kwe0 (default).

Kune Intel Stratix 10, Intel Arria 10, uye Intel Cyclone 10 GX zvishandiso, chiratidzo chewachi chinofanira kugoneswa kana Latency kukosha isiri 1 (default).

clken

Aihwa

Wachi inogonesa kushandiswa kwepaipi. Kana iyo clken chiratidzo ichinzi yakakwira, iyo

adder/subtractor operation inoitika. Kana chiratidzo chakaderera, hapana kushanda

zvinoitika. Kana ikasiiwa, kukosha kwekutanga ndeye 1.

aclr sclr

Aihwa

Asynchronous yakajeka chiratidzo chinoshandiswa chero nguva kugadzirisa pombi kune ese ma0,

asynchronously kune chiratidzo chewachi. Iyo pombi inotanga kune isina kutsanangurwa (X)

logic level. Izvo zvinobuda zvinowirirana, asi zvisiri-zero kukosha.

Aihwa

Synchronous yakajeka chiratidzo chinoshandiswa chero nguva kugadzirisa pombi kune ese ma0,

synchronously kune chiratidzo chewachi. Iyo pombi inotanga kune isina kutsanangurwa (X)

logic level. Izvo zvinobuda zvinowirirana, asi zvisiri-zero kukosha.

Tafura 8.

LPM_MULT masaini masaini

chiratidzo Zita

Zvinodiwa

Tsanangudzo

mhedzisiro[]

Ehe

Data kubuda.

Kune ekare uye Intel Cyclone 10 LP zvishandiso, saizi yeinobuda chiratidzo inoenderana neLPM_WITDHP paramende kukosha. Kana LPM_WIDTHP < max (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) kana (LPM_WIDTHA + LPM_WIDTHS), chete maLPM_WIDTHP MSB aripo.

Kune Intel Stratix 10, Intel Arria 10 uye Intel Cyclone 10 GX, saizi yemasaini ekubuda inotsamira pane Result upamhi paramende.

4.6. Maparamita eStratix V, Arria V, Cyclone V, uye Intel Cyclone 10 LP Devices

4.6.1. General Tab

Tafura 9.

General Tab

Parameter

Value

Multiplier Configuration

Wedzera 'dataa' kuiswa ne 'datab' kuisa

Default Value

Tsanangudzo

Wedzera 'dataa' kuiswa ne 'datab' kuisa

Sarudza inodiwa configuration nokuda multiplier.
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Parameter
Iko kupinza kwe'data' kunofanirwa kuve kwakakura zvakadii? Kuiswa kwe 'datab' kunofanirwa kuve kwakakura zvakadii? Kufara kwe 'zvabuda' kunofanirwa kutariswa sei? Dzora hupamhi

Value
Wedzera 'dataa' yekuisa yega (squaring operation)
1 - 256 zvishoma

Default Value

Tsanangudzo

8 zvishoma

Taura hupamhi hwechiteshi che data[].

1 - 256 zvishoma

8 zvishoma

Taura hupamhi hwedatab[] chiteshi.

Otomatiki verenga hupamhi Dzinga hupamhi
1 - 512 zvishoma

Automatic y verenga hupamhi

Sarudza nzira yaunoda kuona hupamhi hwechibairo[] chiteshi.

16 zvishoma

Taura mufarwa wemubairo[] chiteshi.
Ukoshi uhwu huchashanda chete kana ukasarudza Rega hupamhi muRudzi paramende.

4.6.2. General 2 Tab

Tafura 10. General 2 Tab

Parameter

Value

Datab Input

Bhazi rekuisa re'datab' rine kukosha kwekugara here?

Kwete Hongu

Multiplication Type

Imhando ipi ye

Haina kusaina

kuwandisa unoda here? Sainirwa

Implementation

Ndeipi dhizaini yekuwedzera inofanira kushandiswa?

Shandisa kushandiswa kwechigadziro
Shandisa iyo yakatsaurirwa kuwanda wedunhu (Haisi kuwanikwa kumhuri dzese)
Shandisa zvinhu zvine musoro

Default Value

Tsanangudzo

Aihwa

Sarudza Hongu kutsanangura kukosha kwekusingaperi kwe

`datab' yekuisa bhazi, kana iripo.

Haina kusaina

Taura chimiro chinomiririra chezvose zviri zviviri dataa[] nedatab[] zvinoiswa.

Shandisa iyo default ion yekushandisa

Sarudza nzira yaunoda kuona hupamhi hwechibairo[] chiteshi.

4.6.3. Pipelining Tab

Tafura 11. Pipelining Tab

Parameter

Iwe unoda here kupinza iyo Nha

basa?

Ehe

Value

Gadzira 'aclr'

—

asynchronous clear port

Default Value

Tsanangudzo

Aihwa

Sarudza Hongu kuti ugone kunyoresa pombi kune iyo

multiplier's kubuda uye tsanangura zvaunoda

kubuda latency mu clock cycle. Kugonesa iyo

pipeline rejista inowedzera yakawedzera latency kune iyo

output.

Zvisina kutariswa

Sarudza iyi sarudzo yekugonesa aclr port kushandisa asynchronous clear kune pombi regiji.
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Parameter
Gadzira wachi 'clken' inogonesa wachi
Optimization
Imhando ipi ye optimization yaunoda?

Value -
Default Speed Area

Default Value

Tsanangudzo

Zvisina kutariswa

Inodoma inoshanda pawachi yepamusoro inogonesa pachiteshi chewachi cherejista yepombi

Default

Taura iyo inodiwa optimization yeiyo IP musimboti.
Sarudza Default kuti urege Intel Quartus Prime software ione yakanakisa optimization yeiyo IP musimboti.

4.7. Parameters yeIntel Stratix 10, Intel Arria 10, uye Intel Cyclone 10 GX Devices

4.7.1. General Tab

Tafura 12. General Tab

Parameter

Value

Default Value

Tsanangudzo

Multiplier Configuration Type
Data Port Widths

Wedzera 'dataa' kuiswa ne 'datab' kuisa
Wedzera 'dataa' yekuisa yega (squaring operation)

Wedzera 'dataa' kuiswa ne 'datab' kuisa

Sarudza inodiwa configuration nokuda multiplier.

Dataa width

1 - 256 zvishoma

8 zvishoma

Taura hupamhi hwechiteshi che data[].

Datab width

1 - 256 zvishoma

8 zvishoma

Taura hupamhi hwedatab[] chiteshi.

Kufara kwe 'zvabuda' kunofanirwa kutariswa sei?

Type

Otomatiki verenga hupamhi
Dzora hupamhi

Automatic y verenga hupamhi

Sarudza nzira yaunoda kuona hupamhi hwechibairo[] chiteshi.

Value

1 - 512 zvishoma

16 zvishoma

Taura mufarwa wemubairo[] chiteshi.
Ukoshi uhwu huchashanda chete kana ukasarudza Rega hupamhi muRudzi paramende.

Mhedzisiro yemhedzisiro

1 - 512 zvishoma

—

Inoratidza hupamhi hunobudirira hwechibairo[] podhi.

4.7.2. General 2 Tab

Tafura 13. General 2 Tab

Parameter

Datab Input

Bhazi rekuisa re'datab' rine kukosha kwekugara here?

Kwete Hongu

Value

Default Value

Tsanangudzo

Aihwa

Sarudza Hongu kutsanangura kukosha kwekusingaperi kwe

`datab' yekuisa bhazi, kana iripo.

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Parameter

Value

Chero kukosha kunodarika 0

Multiplication Type

Imhando ipi ye

Haina kusaina

kuwandisa unoda here? Sainirwa

Implementation Style

Ndeipi dhizaini yekuwedzera inofanira kushandiswa?

Shandisa kushandiswa kwechigadziro
Shandisa yakatsaurirwa multiplier circuitry
Shandisa zvinhu zvine musoro

Default Value

Tsanangudzo

Taura kukosha kwekugara kwedatab[] port.

Haina kusaina

Taura chimiro chinomiririra chezvose zviri zviviri dataa[] nedatab[] zvinoiswa.

Shandisa iyo default ion yekushandisa

Sarudza nzira yaunoda kuona hupamhi hwechibairo[] chiteshi.

4.7.3. Pipelining

Tafura 14. Pipelining Tab

Parameter

Value

Unoda kupinza basa racho here?

Pipeline

Kwete Hongu

Latency Clear Signal Type

Chero kukosha kunodarika 0.
HAPANA ACLR SCLR

Gadzira wachi 'clken'

—

gonesa wachi

Imhando ipi ye optimization yaunoda?

Type

Default Speed Area

Default Value

Tsanangudzo

Kwete 1 HAPANA
—

Sarudza Hongu kuti ugone kugonesa kunyoreswa kwepombi kune anowanza. Kugonesa rejista yepombi kunowedzera imwe latency kune zvakabuda.
Rondedzera yaunoda kuburitsa latency muwachi kutenderera.
Taura mhando yekuseta patsva kwerejista yepombi. Sarudza HAKUNA kana usingashandisi chero rejista yepombi. Sarudza ACLR kushandisa asynchronous clear kune pombi regisita. Izvi zvinogadzira ACLR port. Sarudza SCLR kuti ushandise synchronous clear kune iyo pombi rejisita. Izvi zvinogadzira SCLR port.
Inodoma inoshanda pawachi yepamusoro inogonesa pachiteshi chewachi cherejista yepombi

Default

Taura iyo inodiwa optimization yeiyo IP musimboti.
Sarudza Default kuti urege Intel Quartus Prime software ione yakanakisa optimization yeiyo IP musimboti.

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5. LPM_ADD_SUB (Adder/Subtractor)

Mufananidzo 4.

Iyo LPM_ADD_SUB IP musimboti inoita kuti ushandise adder kana subtractor kuti uwedzere kana kubvisa seti yedata kuti ibudise inobuda ine huwandu kana mutsauko wezvakakosha zvekupinza.

Nhamba inotevera inoratidza zviteshi zveLPM_ADD_SUB IP musimboti.

LPM_ADD_SUB Zviteshi

LPM_ADD_SUB add_sub cin

data[]

wachi clken datab[] aclr

mhedzisiro[] kufashukira cout

inst

5.1. Zvimiro
Iyo LPM_ADD_SUB IP musimboti inopa zvinotevera maficha: · Inogadzira adder, subtractor, uye ine dynamically configurable adder/subtractor.
mabasa. · Inotsigira data hupamhi hwe1 bits. · Inotsigira data inomiririra fomati seyakasainwa uye isina kusaina. · Inotsigira sarudzo yekutakura-mukati (kukwereta-kunze), asynchronous yakajeka, uye wachi inogonesa
input ports. · Inotsigira sarudzo yekutakura-kunze (kukwereta-mukati) uye mafashama ekubuda madoko. ‣ Inopa chero imwe yemabhazi ekuisa data kune imwe nguva. · Inotsigira pipelining ine configurable kubuda latency.

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5.2. Verilog HDL Prototype
Iyi inotevera Verilog HDL prototype iri muVerilog Dhizaini File (.v) lpm.v mune edasynthesis directory.
module lpm_add_sub ( mhedzisiro, cout, kufashukira, wedzera_sub, cin, dataa, datab, wachi, clken, aclr); parameter lpm_type = "lpm_add_sub"; parameter lpm_width = 1; parameter lpm_direction = "USINA KUSHANDISWA"; parameter lpm_representation = "KUSAIWA"; parameter lpm_pipeline = 0; parameter lpm_hint = "USINA KUSHANDISWA"; kuisa [lpm_width-1:0] data, datab; input add_sub, cin; wachi yekupinda; input clken; input aclr; zvabuda [lpm_width-1:0] zvabuda; kubuda kwekubuda, kufashukira; endmodule
5.3. VHDL Chikamu Chiziviso
Iyo VHDL chikamu chiziviso chiri muVHDL Dhizaini File (.vhd) LPM_PACK.vhd mune libraryvhdllpm directory.
chikamu LPM_ADD_SUB generic (LPM_WIDTH : natural;
LPM_DIRECTION : string := "USINA KUSHANDISWA"; LPM_REPRESENTATION: tambo := "AKASAIWA"; LPM_PIPELINE : natural := 0; LPM_TYPE : string := L_ADD_SUB; LPM_HINT : tambo := "USINA KUSHANDISWA"); port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0); DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0' mu CLK_logic := '1'; CIN : in std_logic := 'Z'; ADD_SUB : in std_logic := '1'; RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0); COUT : out std_logic; OVERFLOW: out std_logic); end component;
5.4. VHDL LIBRARY_USE Declaration
VHDL LIBRARY-SHANDISA chiziviso hachidiwe kana ukashandisa VHDL Component Declaration.
LIBRARY lpm; SHANDISA lpm.lpm_components.all;
5.5. Zviteshi
Matafura anotevera anonyora ekuisa uye kubuda madoko eLPM_ADD_SUB IP musimboti.

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Tafura 15. LPM_ADD_SUB IP Core Input Ports

Port Name

Zvinodiwa

Tsanangudzo

cin

Aihwa

Pinda-mukati kune yakaderera-odha bit. Zvekuwedzera maoperation, iyo default value ndeye 0. For

Kubvisa mashandiro, kukosha kweiyo default ndeye 1.

data[]

Ehe

Kuiswa kwedata. Saizi yenzvimbo yekupinza inotsamira pane LPM_WIDTH parameter kukosha.

datab[]

Ehe

Kuiswa kwedata. Saizi yenzvimbo yekupinza inotsamira pane LPM_WIDTH parameter kukosha.

add_sub

Aihwa

Sarudzo yekupinza chiteshi kuti igone kugonesa kuchinja pakati peadder uye subtractor

mabasa. Kana LPM_DIRECTION parameter ikashandiswa, add_sub haigone kushandiswa. Kana

yasiiwa, kukosha kweiyo default ndeye ADD. Intel inokurudzira kuti ushandise iyo

LPM_DIRECTION parameter kutsanangura kushanda kweLPM_ADD_SUB basa,

pane kugovera nguva dzose kune add_sub port.

wachi

Aihwa

Input yekushandisa pombi. Chiteshi chewachi chinopa mapindiro ewachi yepombi

kushanda. Kune LPM_PIPELINE ma values asiri 0 (default), wachi inofanira kuva

enabled.

clken

Aihwa

Wachi inogonesa kushandiswa kwepaipi. Kana iyo clken port ichinzi yakakwirira, adder /

subtractor oparesheni inoitika. Kana chiratidzo chiri pasi, hapana kushanda kunoitika. Kana

yakasiiwa, kukosha kweiyo 1.

aclr

Aihwa

Asynchronous clear yekushandisa pombi. Iyo pombi inotanga kune isina kutsanangurwa (X)

logic level. Iyo aclr port inogona kushandiswa chero nguva kuseta pombi kune ese ma0s,

asynchronously kune chiratidzo chewachi.

Tafura 16. LPM_ADD_SUB IP Core Output Ports

Port Name

Zvinodiwa

Tsanangudzo

mhedzisiro[]

Ehe

Data kubuda. Saizi yechiteshi chinobuda zvinoenderana neLPM_WIDTH parameter

value.

cout

Aihwa

Kutakura-kunze (kukwereta-mukati) kweiyo inonyanya kukosha bit (MSB). Iyo cout port ine yemuviri

kududzira sekutakura-kuita (kukwereta-mukati) kweMSB. Iyo cout port inoona

kufashukira mumabasa asina KUSINA. Iyo cout port inoshanda nenzira imwechete ye

KUSAIWA uye KUSINA KUSINA mashandiro.

kufashukira

Aihwa

Optional overflow exception output. Chiteshi chekufashukira chine dudziro yepanyama se

iyo XOR yekutakura-mukati kuenda kuMSB nekutakura-kunze kweMSB. Chiteshi chekufashukira

inosimbisa kana mibairo ichipfuura iyo chaiyo iripo, uye inoshandiswa chete kana iyo

LPM_REPRESENTATION parameter value is SIGNED.

5.6. Paramita

Tafura inotevera ine LPM_ADD_SUB IP core parameters.

Tafura 17. LPM_ADD_SUB IP Core Parameters

Parameter Zita LPM_WIDTH

Type Integer

Zvinodiwa Hongu

Tsanangudzo
Inotsanangura upamhi hwe dataa[], datab[], uye mhedzisiro[] zviteshi.

LPM_DIRECTION

String

Aihwa

Mitemo ndeye ADD, SUB, uye UNUSED. Kana ikasiiwa, kukosha kweiyo DEFAULT, iyo inotungamira parameter kuti itore kukosha kwayo kubva kune add_sub port. Iyo add_sub port haigone kushandiswa kana LPM_DIRECTION ikashandiswa. Intel inokurudzira kuti ushandise LPM_DIRECTION parameter kutsanangura kushanda kweLPM_ADD_SUB basa, pane kugovera nguva dzose kune add_sub port.
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Parameter Zita LPM_REPRESENTATION LPM_PIPELINE LPM_HINT LPM_TYPE ONE_INPUT_IS_CONSTANT MAXIMIZE_SPEED
INTENDED_DEVICE_FAMILY

Type String Integer String String String Integer
String

Inodiwa Kwete Kwete Kwete Kwete Kwete Kwete
Aihwa

Tsanangudzo
Inotsanangura mhando yekuwedzera yaitwa. Hunhu AKASAIWA uye HAZVISINA KUSINA. Kana ikasiiwa, kukosha kweiyo default kunosaina. Kana iyi parameter yaiswa kuti KUSINA, adder/subtractor inoturikira kupinza kwedata sekusainwa kwembiri.
Inotsanangura nhamba ye latency clock cycles ine chekuita nemhedzisiro[] yabuda. Kukosha kwe zero (0) kunoratidza kuti hapana latency iripo, uye kuti basa rakanyatsobatanidzwa richasimbiswa. Kana ikasiiwa, kukosha kweiyo 0 (isina-pipelined).
Inokutendera kuti utaure Intel-chaiyo paramita muVHDL dhizaini files (.vhd). Iko kukosha kwekutanga ndeye UNUSED.
Inozivisa raibhurari yeparameterized modules (LPM) zita rechikamu muVHDL dhizaini files.
Intel-specific parameter. Unofanira kushandisa LPM_HINT parameter kutsanangura ONE_INPUT_IS_CONSTANT parameter muVHDL dhizaini. files. Mitemo ndeye YES, NO, uye USINA KUSHANDISWA. Inopa optimization yakakura kana imwe yekuisa ichigara. Kana ikasiiwa, kukosha kweiyo default NO.
Intel-specific parameter. Unofanira kushandisa LPM_HINT parameter kutsanangura MAXIMIZE_SPEED parameter muVHDL dhizaini. files. Unogona kudoma kukosha kuri pakati pe0 ne10. Kana ikashandiswa, Intel Quartus Prime software inoedza kukwenenzvera imwe nguva yeLPM_ADD_SUB basa rekumhanya kwete kurongeka, uye inodarika marongero eOptimization Technique logic sarudzo. Kana MAXIMIZE_SPEED isina kushandiswa, kukosha kweOptimization Technique sarudzo ndiyo inoshandiswa pachinzvimbo. Kana marongero eMAXIMIZE_SPEED ari 6 kana kupfuura, Compiler inokwenenzvera LPM_ADD_SUB IP core kuitira kumhanya kwakanyanya uchishandisa cheni dzekutakura; kana kuseta kuri 5 kana zvishoma, Iyo Compiler inoshandisa dhizaini pasina cheni dzekutakura. Iyi parameter inofanirwa kutsanangurwa yeCyclone, Stratix, uye Stratix GX zvishandiso chete kana iyo add_sub port isiri kushandiswa.
Iyi parameter inoshandiswa kuenzanisa uye maitiro ekufananidza zvinangwa. Iyo parameter editor inoverenga kukosha kweiyi parameter.

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6. LPM_COMPARE (Muenzanisi)

Mufananidzo 5.

Iyo LPM_COMPARE IP musimboti inofananidza kukosha kwemaseti maviri e data kuona hukama pakati pavo. Muchimiro chayo chakareruka, unogona kushandisa yakasarudzika-OR gedhi kuona kana mabhiti maviri edata akaenzana.

Iyi inotevera nhamba inoratidza madoko eLPM_COMPARE IP musimboti.

LPM_COMPARE Zviteshi

LPM_COMPARE

clken

alb

aeb

data[]

agb

datab[]

ageb

wachi

aneb

aclr

aleb

inst

6.1. Zvimiro
Iyo LPM_COMPARE IP musimboti inopa anotevera maficha: · Inogadzira basa rekuenzanisa kuenzanisa seti mbiri dzedata · Inotsigira data hupamhi hwe1 bits · Inotsigira data inomiririra fomati seyakasainwa uye isina kusaina · Inoburitsa anotevera marudzi ekubuda:
— alb (yekupinza A ishoma pane yekupinda B) — aeb (yekupinza A yakaenzana neinopinza B) — agb (yekupinda A yakakura pane yekupinda B) — ageb (yekupinda A yakakura kupfuura kana yakaenzana nekuisa B) — aneb ( kuisa A haina kuenzana nekuisa B) — aleb (yekupinza A ishoma pane kana kuenzana nekuisa B) · Inotsigira sarudzo asynchronous yakajeka uye wachi inogonesa zviteshi zvekupinza · Inopa iyo datab[] yekuisa kune inongogara · Inotsigira pipelining ine configurable inobuda latency

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6. LPM_COMPARE (Comparator) 683490 | 2020.10.05
6.2. Verilog HDL Prototype
Iyi inotevera Verilog HDL prototype iri muVerilog Dhizaini File (.v) lpm.v mune edasynthesis directory.
module lpm_compare (alb, aeb, agb, aleb, aneb, ageb, dataa, datab, wachi, clken, aclr); parameter lpm_type = "lpm_compare"; parameter lpm_width = 1; parameter lpm_representation = "UNSIGNED"; parameter lpm_pipeline = 0; parameter lpm_hint = "USINA KUSHANDISWA"; kuisa [lpm_width-1:0] data, datab; wachi yekupinda; input clken; input aclr; goho alb, aeb, agb, aleb, aneb, ageb; endmodule
6.3. VHDL Chikamu Chiziviso
Iyo VHDL chikamu chiziviso chiri muVHDL Dhizaini File (.vhd) LPM_PACK.vhd mune libraryvhdllpm directory.
chikamu LPM_COMPARE generic (LPM_WIDTH : natural;
LPM_REPRESENTATION : string := "UNSIGNED"; LPM_PIPELINE : natural := 0; LPM_TYPE: tambo := L_COMPARE; LPM_HINT : tambo := "USINA KUSHANDISWA"); port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0); DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0' mu CLK_logic := '1'; AGB : out std_logic; AGEB : out std_logic; AEB : out std_logic; ANEB : out std_logic; ALB : out std_logic; ALEB : out std_logic); end component;
6.4. VHDL LIBRARY_USE Declaration
VHDL LIBRARY-SHANDISA chiziviso hachidiwe kana ukashandisa VHDL Component Declaration.
LIBRARY lpm; SHANDISA lpm.lpm_components.all;
6.5. Zviteshi
Matafura anotevera anonyora ekuisa uye kubuda madoko eiyo LMP_COMPARE IP musimboti.

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Tafura 18. LPM_COMPARE IP core Input Ports

Port Name

Zvinodiwa

Tsanangudzo

data[]

Ehe

Kuiswa kwedata. Saizi yenzvimbo yekupinza inotsamira pane LPM_WIDTH parameter kukosha.

datab[]

Ehe

Kuiswa kwedata. Saizi yenzvimbo yekupinza inotsamira pane LPM_WIDTH parameter kukosha.

wachi

Aihwa

Kuisa wachi yekushandiswa kwepaipi. Chiteshi chewachi chinopa mapindiro ewachi yepombi

kushanda. Kune LPM_PIPELINE ma values asiri 0 (default), wachi inofanira kuva

enabled.

clken

Aihwa

Wachi inogonesa kushandiswa kwepaipi. Kana iyo clken port ichinzi yakakwira, iyo

kuenzanisa kushanda kunoitika. Kana chiratidzo chiri pasi, hapana kushanda kunoitika. Kana

yakasiiwa, kukosha kweiyo 1.

aclr

Aihwa

Asynchronous clear yekushandisa pombi. Iyo pombi inotanga kune isina kutsanangurwa (X) logic

level. Iyo aclr port inogona kushandiswa chero nguva kuseta pombi kune ese ma0s,

asynchronously kune chiratidzo chewachi.

Tafura 19. LPM_COMPARE IP core Output Ports

Port Name

Zvinodiwa

Tsanangudzo

alb

Aihwa

Chiteshi chekubuda chemuenzanisi. Zvinonzi kana yaiswa A ishoma pane yekuisa B.

aeb

Aihwa

Chiteshi chekubuda chemuenzanisi. Zvinonzi kana yaiswa A yakaenzana nekuisa B.

agb

Aihwa

Chiteshi chekubuda chemuenzanisi. Zvinotemerwa kuti kana yaiswa A yakakura pane yekuisa B.

ageb

Aihwa

Chiteshi chekubuda chemuenzanisi. Zvinotemerwa kuti kana A akakurisa kana kuenzana nekuisa

aneb

Aihwa

Chiteshi chekubuda chemuenzanisi. Zvinonzi kana yaiswa A isina kuenzana nekuisa B.

aleb

Aihwa

Chiteshi chekubuda chemuenzanisi. Zvinotemerwa kuti kana yaiswa A ishoma pane kana kuenzana nekuisa B.

6.6. Paramita

Tafura inotevera inoronga maparameter eiyo LPM_COMPARE IP core.

Tafura 20. LPM_COMPARE IP core Parameters

Parameter Zita

Type

Zvinodiwa

LPM_WIDTH

Integer Hongu

LPM_REPRESENTATION

String

Aihwa

LPM_PIPELINE

Nhamba nhamba

LPM_HINT

String

Aihwa

Tsanangudzo
Inotsanangura upamhi hwe dataa[] uye datab[] zviteshi.
Inotsanangura rudzi rwekuenzanisa kwakaitwa. Hunhu AKASAIWA uye HAZVISINA KUSINA. Kana ikasiiwa, iyo default value haina KUSVIKA. Kana iyi parameter kukosha yaiswa KUSINA, muenzanisi anodudzira iyo data yekuisa seyakasainwa maviri anozadzisa.
Inotsanangura huwandu hwemawachi ekutenderera anoenderana nealb, aeb, agb, ageb, aleb, kana aneb kubuda. Kukosha kwe zero (0) kunoratidza kuti hapana latency iripo, uye kuti basa rakanyatsobatanidzwa richasimbiswa. Kana ikasiiwa, kukosha kweiyo 0 (isina pipelined).
Inokutendera kuti utaure Intel-chaiyo paramita muVHDL dhizaini files (.vhd). Iko kukosha kwekutanga ndeye UNUSED.
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Parameter Zita LPM_TYPE INTENDED_DEVICE_FAMILY
ONE_INPUT_IS_CONSTANT

Type String String
String

Inodiwa Nha
Aihwa

Tsanangudzo
Inozivisa raibhurari yeparameterized modules (LPM) zita rechikamu muVHDL dhizaini files.
Iyi parameter inoshandiswa kuenzanisa uye maitiro ekufananidza zvinangwa. Iyo parameter editor inoverenga kukosha kweiyi parameter.
Intel-specific parameter. Unofanira kushandisa LPM_HINT parameter kutsanangura ONE_INPUT_IS_CONSTANT parameter muVHDL dhizaini. files. Mitemo ndeye YES, NO, kana USINA KUSHANDISWA. Inopa optimization yakakura kana yekuisa inogara iripo. Kana ikasiiwa, kukosha kweiyo default NO.

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7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core

Mufananidzo 6.

Intel inopa iyo ALTECC IP musimboti wekushandisa iyo ECC mashandiro. ECC inoona yakaora data inoitika padivi rekugamuchira panguva yekufambisa data. Iyi nzira yekugadzirisa kukanganisa inonyatsokodzera mamiriro ezvinhu apo kukanganisa kunoitika chero nguva kwete mukuputika.

Iyo ECC inoona zvikanganiso kuburikidza nekuita kwedata encoding uye decoding. For example, kana iyo ECC ikashandiswa mukutumira application, data inoverengwa kubva kwairi inoiswa encoded isati yatumirwa kune anogamuchira. Iyo inobuda (code izwi) kubva kune encoder ine data mbishi inowedzerwa nehuwandu hweparity bits. Nhamba chaiyo yemabhiti eparity akaiswa zvinoenderana nehuwandu hwemabhiti mune data rekuisa. Izwi rekodhi rakagadzirwa rinobva raendeswa kunzvimbo yekuenda.

Anogamuchira anogamuchira izwi rekodhi uye anoritsanangura. Ruzivo rwakawanikwa nedecoder rwunoona kana kukanganisa kwaonekwa. Iyo decoder inoona imwe-bit uye kaviri-bit zvikanganiso, asi inogona chete kugadzirisa imwe-bit zvikanganiso mune yakaora data. Iyi mhando yeECC ndeye imwe kukanganisa kugadzirisa kaviri kukanganisa kuona (SECDED).

Iwe unogona kugadzirisa encoder uye decoder mabasa eAlTECC IP musimboti. Iyo data yekuisa kune encoder yakavharidzirwa kuti igadzire izwi rekodhi iro riri musanganiswa weiyo data yekuisa uye inogadzirwa parity bits. Izwi rakagadzirwa kodhi rinoendeswa kune iyo decoder module ye decoder isati yasvika kwairi kuenda. Iyo decoder inogadzira syndrome vector kuona kana paine chikanganiso mune yakagamuchirwa kodhi izwi. Iyo decoder inogadzirisa iyo data chete kana imwechete-bit kukanganisa kubva kune data bits. Hapana chiratidzo chinomisikidzwa kana chikanganiso chimwe-bit chichibva kune parity bits. Iyo decoder zvakare ine zvikwangwani zvemureza kuratidza mamiriro edata rakagamuchirwa uye chiito chakatorwa nedecoder, kana iripo.

Iwo anotevera manhamba anoratidza madoko eiyo ALTECC IP musimboti.

ALTECC Encoder Ports

ALTECC_ENCODER

data[]

q[]

wachi

aclr

inst

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7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core 683490 | 2020.10.05

Mufananidzo 7. ALTECC Decoder Ports

ALTECC_DECODER

data[] wachi

q[] err_detected err_corrected
err_fatal

aclr

inst

7.1. ALTECC Encoder Zvimiro

Iyo ALTECC encoder IP musimboti inopa zvinotevera maficha: · Inoita encoding yedata uchishandisa iyo Hamming Coding scheme · Inotsigira data hupamhi hwe2 bits · Inotsigira yakasainwa uye isina kusaina yekumiririra data fomati · Inotsigira pipelining nekubuda latency yeimwe kana maviri wachi cycles · Inotsigira sarudzo. asynchronous yakajeka uye wachi inogonesa madoko

Iyo ALTECC encoder IP musimboti inotora mukati uye inokodha iyo data uchishandisa iyo Hamming Coding scheme. Iyo Hamming Coding scheme inotora iyo parity bits uye inoawedzera kune yekutanga data kuti ibudise inobuda kodhi izwi. Huwandu hwemabhiti eparity akawedzerwa zvinoenderana nehupamhi hwe data.

Tafura inotevera inodonongodza huwandu hwemabhiti eparity akaiswa kune dzakasiyana siyana dzehupamhi hwedata. Iyo Yese Bits column inomiririra huwandu hwese hwekuisa data bits uye akawedzera parity bits.

Tafura 21.

Nhamba yeParity Bits uye Code Izwi Maererano neData Width

Data Width

Nhamba yeParity Bits

Total Bits (Code Word)

2-4

3+1

6-8

5-11

4+1

10-16

12-26

5+1

18-32

27-57

6+1

34-64

58-64

7+1

66-72

Iyo parity bit derivation inoshandisa even-parity cheki. Iyo yekuwedzera 1 bhiti (inoratidzwa patafura se +1) inowedzerwa kune parity bits seMSB yezwi rekodhi. Izvi zvinovimbisa kuti izwi rekodhi rine kunyange nhamba ye1. For example, kana hupamhi hwe data huri 4 bits, 4 parity bits inowedzerwa kune data kuti ive izwi rekodhi rine huwandu hwe8 bits. Kana 7 bits kubva kuLSB ye8-bit code word iine nhamba isina kujairika ye1's, 8th bit (MSB) yeizwi rekodhi 1 kuita nhamba yese ye1 mukodhi izwi nyangwe.
Nhamba inotevera inoratidza iyo yakagadzirwa kodhi izwi uye kurongeka kweiyo parity bits uye data bits mune 8-bit data yekuisa.

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Mufananidzo 8.

Parity Bits uye Data Bits Arrangement mu8-Bit Yakagadzirwa Code Word

MSB

LSB

4 parity bits

4 data bits

Iyo ALTECC encoder IP musimboti inogamuchira chete kupinza upamhi hwe2 kusvika 64 bits panguva imwe. Input wides of 12 bits, 29 bits, and 64 bits, ayo akanyatsokodzera kuIntel madivayiri, anogadzira zvinobuda zve18 bits, 36 bits, uye 72 bits zvakateerana. Iwe unogona kudzora iyo bitselection muganho mune parameter mupepeti.

7.2. Verilog HDL Prototype (ALTECC_ENCODER)
Iyi inotevera Verilog HDL prototype iri muVerilog Dhizaini File (.v) lpm.v mune edasynthesis directory.
module altecc_encoder #( parameter yaida_device_family = "isina kushandiswa", parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = "altecc_encoder", parameter lpm_hint = "isina kushandiswa wayareclr, kuisa waya waya wachi, waya yekupinza [width_dataword-1:0] data, waya yekubuda [width_codeword-1:0] q); endmodule

7.3. Verilog HDL Prototype (ALTECC_DECODER)
Iyi inotevera Verilog HDL prototype iri muVerilog Dhizaini File (.v) lpm.v mune edasynthesis directory.
module altecc_decoder #( parameter yaida_device_family = "isina kushandiswa", parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = "altecc_decoder", parameter lpm_hint = "isina kushandiswa waya) (waya yekupinda, yekuisa waya waya wachi, waya yekupinza [width_codeword-1:0] data, yakabuda waya err_corrected, inobuda waya err_detected, outout wire err_fatal, kubuda waya [width_dataword-1:0] q); endmodule

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7.4. VHDL Component Declaration (ALTECC_ENCODER)
Iyo VHDL chikamu chiziviso chiri muVHDL Dhizaini File (.vhd) altera_mf_components.vhd in the librariesvhdlaltera_mf directory.
chikamu altecc_encoder generic (yaida_device_family: tambo := "isina kushandiswa"; lpm_pipeline:natural:= 0; width_codeword:natural:= 8; width_dataword:natural:= 8; lpm_hint:string := "UNUSED"type:cc_stringte" ”); port( aclr: in std_logic := '0'; wachi: in std_logic := '0'; wachi: in std_logic := '1'; data:mu std_logic_vector(width_dataword-1 downto 0); q:out std_logic_vector(width_codeword) -1 kusvika pa0)); end component;
7.5. VHDL Component Declaration (ALTECC_DECODER)
Iyo VHDL chikamu chiziviso chiri muVHDL Dhizaini File (.vhd) altera_mf_components.vhd in the librariesvhdlaltera_mf directory.
chikamu altecc_decoder generic (yaida_device_family: tambo := "isina kushandiswa"; lpm_pipeline:natural := 0; width_codeword:natural:= 8; width_dataword:natural:= 8; lpm_hint:string := "UNUSED" typeal:cc_stringte ”); port( aclr: in std_logic := '0'; wachi: in std_logic := '0'; wachi: in std_logic := '1'; data: in std_logic_vector (width_codeword-1 downto 0); err_corrected: kunze std_logic; kukanganisa_kwaonekwa : kunze std_logic; q:out std_logic_vector(width_dataword-1 downto 0); syn_e: kunze std_logic); end component;
7.6. VHDL LIBRARY_USE Declaration
VHDL LIBRARY-SHANDISA chiziviso hachidiwe kana ukashandisa VHDL Component Declaration.
LIBRARY altera_mf; SHANDISA altera_mf.altera_mf_components.all;
7.7. Encoder Ports
Aya matafura anotevera anonyora ekuisa uye kubuda madoko eiyo ALTECC encoder IP musimboti.

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Tafura 22. ALTECC Encoder Input Ports

Port Name

Zvinodiwa

Tsanangudzo

data[]

Ehe

Data yekupinza port. Saizi yenzvimbo yekupinza inotsamira paWIDTH_DATAWORD

parameter value. Iyo data[] chiteshi ine data rakagadzirwa rinofanira kukodha.

wachi

Ehe

Chiteshi chekupinza chewachi chinopa chiratidzo chewachi kuwiriranisa kushanda kwe encoding.

Chimbo chewachi chinodiwa kana kukosha kweLPM_PIPELINE kwakakura kupfuura 0.

wachi

Aihwa

Clock inogonesa. Kana ikasiiwa, kukosha kwekutanga ndeye 1.

aclr

Aihwa

Asynchronous yakajeka kuisa. Iyo inoshanda yakakwira aclr chiratidzo inogona kushandiswa chero nguva ku

asynchronously bvisa marejista.

Tafura 23. ALTECC Encoder Output Ports

Port Name q[]

Zvinodiwa Hongu

Tsanangudzo
Encoded data kubuda port. Saizi yenzvimbo inobuda inotsamira pa WIDTH_CODEWORD parameter value.

7.8. Decoder Ports

Matafura anotevera anonyora ekuisa uye kubuda madoko eiyo ALTECC decoder IP musimboti.

Tafura 24. ALTECC Decoder Input Ports

Port Name

Zvinodiwa

Tsanangudzo

data[]

Ehe

Data yekupinza port. Saizi yenzvimbo yekupinza inotsamira pane WIDTH_CODEWORD parameter kukosha.

wachi

Ehe

Chiteshi chekupinza chewachi chinopa chiratidzo chewachi kuwiriranisa kushanda kwe encoding. Chimbo chewachi chinodiwa kana kukosha kweLPM_PIPELINE kwakakura kupfuura 0.

wachi

Aihwa

Clock inogonesa. Kana ikasiiwa, kukosha kwekutanga ndeye 1.

aclr

Aihwa

Asynchronous yakajeka kuisa. Iyo inoshanda yakakwira aclr chiratidzo inogona kushandiswa chero nguva kuti asynchronously kujekesa marejista.

Tafura 25. ALTECC Decoder Output Ports

Port Name q[]

Zvinodiwa Hongu

Tsanangudzo
Decoded data output port. Saizi yechiteshi chinobuda zvinoenderana neWIDTH_DATAWORD parameter value.

err_detected Yes

Mureza chiratidzo kuratidza mamiriro e data yakagamuchirwa uye inotsanangura chero kukanganisa kwawanikwa.

err_correcte Hongu d

Mureza chiratidzo kuratidza mamiriro e data ragamuchirwa. Zvinoreva kukanganisa kwekamwe-bit kwakawanikwa nekugadziriswa. Unogona kushandisa iyo data nekuti yakatogadziriswa.

err_fatal

Ehe

Mureza chiratidzo kuratidza mamiriro e data ragamuchirwa. Zvinoreva kukanganisa-kaviri kwawanikwa, asi kusina kugadziriswa. Iwe haufanirwe kushandisa iyo data kana chiratidzo ichi chakasimbiswa.

syn_e

Aihwa

Chiratidzo chinobuda chinoenda kumusoro pese kana chikanganiso chimwe chete chikaonekwa pane parity

bits.

7.9. Encoder Parameters
Tafura inotevera inonyora maparamendi eiyo ALTECC encoder IP musimboti.

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Tafura 26. ALTECC Encoder Parameters

Parameter Zita

Type

Zvinodiwa

Tsanangudzo

WIDTH_DATAWORD

Integer Hongu

Inotsanangura hupamhi hwe data raw. Hwaro hunobva pa 2 kusvika pa 64. Kana ikasiiwa, kukosha kwe 8.

WIDTH_CODEWORD

Integer Hongu

Inotsanangura upamhi hwezwi rekodhi rinoenderana. Hwaro hunoshanda hunobva pa6 kusvika pa72, tisingasanganisire 9, 17, 33, uye 65. Kana zvikasiiwa, kukosha kwekutanga ndi13.

LPM_PIPELINE

Nhamba nhamba

Inotsanangura pombi yedunhu. Mitemo inobva ku0 kusvika ku2. Kana kukosha kuri 0, zviteshi hazvina kunyoreswa. Kana kukosha kuri 1, zviteshi zvinobuda zvinonyoreswa. Kana kukosha kuri 2, iyo yekupinza uye yekubuda ports inonyoreswa. Kana ikasiiwa, kukosha kweiyo 0.

7.10. Decoder Parameters

Tafura inotevera inonyora ALTECC decoder IP core parameter.

Tafura 27. ALTECC Decoder Parameters

Parameter Zita WIDTH_DATAWORD

Type Integer

Zvinodiwa

Tsanangudzo

Ehe

Inotsanangura hupamhi hwe data raw. Hunhu 2 kusvika 64. The

default kukosha i8.

WIDTH_CODEWORD

Integer

Ehe

Inotsanangura upamhi hwezwi rekodhi rinoenderana. Mitemo ndeye 6

kusvika 72, kusanganisa 9, 17, 33, uye 65. Kana ikasiiwa, kukosha kwekutanga

iri 13.

LPM_PIPELINE

Integer

Aihwa

Inotsanangura rejista yedunhu. Values kubva 0 kusvika 2. Kana iyo

kukosha ndeye 0, hapana rejista inoitwa. Kana kukosha kuri 1, the

kubuda kunonyoreswa. Kana kukosha kuri 2, zvese zvinopinza uye iyo

zvinobuda zvakanyoreswa. Kana kukosha kwakakura kudarika 2, kuwedzera

marejista anoitwa pazvinobuda pakuwedzera

latencies. Kana ikasiiwa, kukosha kweiyo 0.

Gadzira 'syn_e' port

Integer

Aihwa

Batidza iyi parameter kuti ugadzire chiteshi che syn_e.

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683490 | 2020.10.05 Tumira Mhinduro

8. Intel FPGA Kuwanza Adder IP Core

Mufananidzo 9.

Iyo Intel FPGA Yakawedzera Adder (Intel Stratix 10, Intel Arria 10, uye Intel Cyclone 10 GX zvishandiso) kana ALTERA_MULT_ADD (Arria V, Stratix V, uye Cyclone V zvishandiso) IP musimboti inokutendera iwe kuita yakawedzera-adhi.

Iyi inotevera nhamba inoratidza madoko eIntel FPGA Multiply Adder kana ALTERA_MULT_ADD IP musimboti.

Intel FPGA Kuwanza Adder kana ALTERA_MULT_ADD Ports

Intel FPGA Kuwanza Adder kana ALTERA_MULT_ADD

dataa[] signa datab[] signb datac[] coefsel0[] coefsel1[] coefsel2[] coefsel3[] addnsub1 addnsub3 aclr/sclr[] scanina[] wachi0 wachi1 wachi2 ena0 ena1 ena2 sload_accum
accum_sload chainin[]

scanouta[] zvabuda[]

acl0 aclr1

inst
Adder-adder inogamuchira mapeya ezvinopinza, inowanza kukosha pamwe chete uye yobva yawedzera kana kubvisa kubva kune zvigadzirwa zvezvimwe zvese zviviri.
Kana ese ekuisa data upamhi ari 9-bits yakafara kana idiki, basa rinoshandisa iyo 9 x 9 bit yekuwedzera yekuwedzera configuration muDSP block yemidziyo inotsigira 9 x 9 configuration. Kana zvisina kudaro, iyo DSP block inoshandisa 18 × 18-bit mabhii ekuwedzera kugadzirisa data nehupamhi pakati pegumi mabhiti negumi nemasere. Kana akawanda Intel FPGA Multiply Adder kana ALTERA_MULT_ADD IP cores ikaitika mudhizaini, mabasa anogoverwa se.

ISO 9001:2015 Yakanyoreswa

8. Intel FPGA Kuwanza Adder IP Core 683490 | 2020.10.05
akawanda akasiyana DSP mabhuroko sezvinobvira kuitira kuti nzira yekuenda kune aya mabhuroko iwedzere kushanduka. Vashoma vanowedzera paDSP block inobvumira sarudzo dzakawanda dzekufambisa mubhuroko nekudzikisira nzira kune imwe mudziyo.
Marejista uye mamwe marejista epombi ezvikwangwani zvinotevera anoiswawo mukati meDSP block: · Kuiswa kwedata · Saina kana kusaina sarudzo · Wedzera kana kubvisa zvakasarudzwa · Zvigadzirwa zvevazhinji
Panyaya yemugumisiro wekubuda, rejisita yekutanga inoiswa muDSP block. Nekudaro iwo ekuwedzera latency marejista anoiswa mune logic zvinhu kunze kweblock. Peripheral kune iyo DSP block, inosanganisira data yekupinza kune yawandisa, kudzora masaini mapindiro, uye zvinobuda zveadder, shandisa yakajairwa routing kuti utaure nechero mudziyo. Zvese zvinongedzo mune basa zvinoshandisa yakatsaurirwa nzira mukati meDSP block. Iyi nzira yakatsaurirwa inosanganisira cheni dzemashift register paunosarudza sarudzo yekushandura data yakanyoreswa yevazhinji kubva kune imwe inowandisa kuenda kune inowandisa iri pedyo.
Kuti uwane rumwe ruzivo nezve mabhuroko eDSP mune chero eStratix V, uye Arria V mudziyo wakatevedzana, tarisa kuDSP Blocks chitsauko chemabhuku emaoko ari paLiterature neTechnical Documentation peji.
Ruzivo Rwakabatana AN 306: Kuita Zvizhinji muFPGA Zvishandiso
Inopa rumwe ruzivo nezve kuita kuwanda uchishandisa DSP uye ndangariro zvivharo muIntel FPGA zvishandiso.
8.1. Zvimiro
Iyo Intel FPGA Multiply Adder kana ALTERA_MULT_ADD IP core inopa zvinotevera maficha: · Inogadzira mupupuri kuti uite mabasa ekuwanza maviri akaomarara.
nhamba Cherechedzo: Paunenge uchivaka akawanda mahombe kupfuura saizi inotsigirwa nekuzvarwa panogona/
ichave chiitiko chekuita chinobva mukudonha kwemabhuroko eDSP. · Inotsigira data hupamhi hwe1 256 bits · Inotsigira yakasainwa uye isina kusaina yekumiririra data fomati · Inotsigira pipelining ine configurable input latency · Inopa sarudzo yekuchinja zvine simba pakati peyakasainwa uye isina kusaina rutsigiro rwedata · Inopa sarudzo yekuchinja zvine simba pakati pekuwedzera nekubvisa mashandiro sarudzo asynchronous uye synchronous clear uye wachi inogonesa maports ekupinza · Inotsigira systolic kunonoka rejista modhi · Inotsigira pre-adder ne8 pre-load coefficients paawandisa · Inotsigira pre-load nguva dzose kuti ienderane neaccumulator mhinduro.

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8.1.1. Pre-adder
Nepre-adder, kuwedzera kana kubvisa kunoitwa isati yadyisa muwedzere.
Pane shanu pre-adder modes: · Nyore modhi · Coefficient mode · Input mode · Square mode · Constant mode

Cherechedza:

Kana pre-adder inoshandiswa (pre-adder coefficient/input/square mode), zvese zvinoiswa data kune yakawandisa zvinofanirwa kunge zvine wachi imwechete.

8.1.1.1. Pre-adder Nyore Modhi

Mune iyi modhi, ese ari maviri operands anotora kubva kune yekupinza ports uye pre-adder haishandiswe kana kupfuura. Iyi ndiyo default mode.

Mufananidzo 10. Pre-adder Simple Mode
a0 b0

Mult0

mhedzisiro

8.1.1.2. Pre-adder Coefficient Mode
Mune iyi modhi, imwe yekuwedzera operand inotora kubva kune pre-adder, uye imwe operand inotora kubva mukati coefficient kuchengetedza. Iyo coefficient kuchengetedza inobvumira kusvika ku8 preset constants. Iwo coefficient sarudzo masaini ari coefsel[0..3].
Iyi modhi inoratidzwa mune inotevera equation.

Zvinotevera zvinoratidza pre-adder coefficient mode ye multiplier.

Mufananidzo 11. Pre-adder Coefficient Mode

Preadder

Mult0

+/-

mhedzisiro

coefsel0 coef

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8.1.1.3. Pre-adder Input Mode Muiyi modhi, imwe oparesheni yekuwedzera inotora kubva kune pre-adder, uye imwe operand inotora kubva kune datac[] yekupinza port. Iyi modhi inoratidzwa mune inotevera equation.

Zvinotevera zvinoratidza pre-adder yekupinda modhi yekuwandisa.

Mufananidzo 12. Pre-adder Input Mode
a0 b0

Mult0

+/-

mhedzisiro

8.1.1.4. Pre-adder Square Mode Iyi modhi inoratidzwa mune inotevera equation.

Inotevera inoratidza pre-adder square modhi yevaviri vanowedzera.

Mufananidzo 13. Pre-adder Square Mode
a0 b0

Mult0

+/-

mhedzisiro

8.1.1.5. Pre-adder Constant Mode
Mune iyi modhi, imwe yekuwedzera operand inotora kubva kune yekupinza port, uye imwe operand inotora kubva mukati coefficient kuchengetedza. Iyo coefficient kuchengetedza inobvumira kusvika ku8 preset constants. Iwo coefficient sarudzo masaini ari coefsel[0..3].
Iyi modhi inoratidzwa mune inotevera equation.

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Mufananidzo unotevera unoratidza pre-adder inongogara modhi yekuwandisa.

Mufananidzo 14. Pre-adder Constant Mode
a0

Mult0

mhedzisiro

coefsel0
coef
8.1.2. Systolic Kunonoka Register
Mune systolic architecture, iyo data yekupinda inopihwa mune cascade yemarejista anoita se data buffer. Rejista yega yega inopa sample kumuwanziridzi apo inopetwa nekoyefiti yakafanira. Cheni adder inochengeta zvawanikwa zvakasanganiswa zvishoma nezvishoma kubva pakuwandisa uye zvakambonyoreswa zvawanikwa kubva kuchainin[] port port kuti igadzire mhinduro yekupedzisira. Chimwe nechimwe chekuwedzera-kuwedzera chinhu chinofanirwa kunonoka nedenderedzwa rimwe chete kuitira kuti mibairo iwirirane zvakakodzera kana yawedzerwa pamwechete. Kunonoka kwega kwega kunotevedzana kunoshandiswa kugadzirisa ese ari maviri coefficient memory uye data buffer yezvazvo zvakawandisa-add zvinhu. For example, kunonoka kumwe chete kwechipiri kuwedzera wedzera chinhu, kunonoka kuviri kwechitatu wedzera-kuwedzera chinhu, zvichingodaro.
Mufananidzo 15. Systolic Registers
Systolic zvinyorwa

x(t) c(0)

S -1

c(1)

S -1

c(2)

S -1

c(N-1)

S -1

S -1 y(t)

x(t) inomiririra mibairo kubva kune inoenderera mberi yekupinda samples uye y (t)
inomiririra kupfupikiswa kweseti yekupinza sampuye nekufamba kwenguva, yakawedzera nekwavo
zvichienderana coefficients. Zvose zvinopinza uye zvinobuda zvinoyerera kubva kuruboshwe kuenda kurudyi. Iko c(0) kusvika kuc(N-1) inoreva makobiri. Iyo systolic kunonoka marejista inoratidzwa neS-1, nepo 1 inomiririra kunonoka kwewachi imwe chete. Systolic kunonoka marejista anowedzerwa pa
izvo zvinopinda uye zvinobuda zvepipelining nenzira inovimbisa mhedzisiro kubva ku
multiplier operand uye sums dzakaunganidzwa dzinogara musync. Ichi chekugadzirisa chinhu
inodzokororwa kuita dunhu rinoverengera basa rekusefa. Basa iri
inoratidzwa muequation inotevera.

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N inomiririra huwandu hwematenderedzwa e data apinda mu accumulator, y(t) inomiririra yabuda panguva t, A(t) inomiririra kupinza panguva t, uye B(i) ndiwo macoefficients. Iyo t uye i muequation inoenderana neimwe nguva nenguva, saka kuverengera zvinobuda s.ample y(t) panguva t, boka rekuisa sampzvishoma paN mapoinzi akasiyana nenguva, kana A(n), A(n-1), A(n-2), … A(n-N+1) inodiwa. Boka reN yekuisa sampLes anowanziridzwa neN coefficients uye akapfupikiswa pamwechete kuti agadzire chigumisiro chekupedzisira y.
Iyo systolic rejista yedhizaini inowanikwa chete kune sum-ye-2 uye sum-ye-4 modhi. Kune ese ari maviri systolic rejista architecture modes, yekutanga ketani chiratidzo chinoda kusungirirwa ku0.
Iyi inotevera nhamba inoratidza systolic kunonoka rejista kuitiswa kwe2 vanowedzera.
Mufananidzo 16. Systolic Delay Register Implementation ye2 Multipliers
chainin

Mult0

+/-

Mult1

+/-

mhedzisiro
Huwandu hwevaviri vawandisa hunoratidzwa muequation inotevera.
Iyi inotevera nhamba inoratidza systolic kunonoka rejista kuitiswa kwe4 vanowedzera.

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Mufananidzo 17. Systolic Delay Register Implementation ye4 Multipliers
chainin

Mult0

+/-

Mult1

+/-

Mult2

+/-

Mult3

+/-

mhedzisiro
Huwandu hwezviwanziri zvina zvinoratidzwa muequation inotevera. Mufananidzo 18. Nhamba ye4 Multipliers
Zvinotevera zvinoratidza advantages of systolic rejista kuita: · Inoderedza kushandiswa kweDSP zviwanikwa.

Intel FPGA Integer Arithmetic IP Cores Mushandisi Gwaro 42

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8.1.3. Pre-load Constant
Iyo pre-mutoro inogara inodzora iyo accumulator operand uye inozadzisa iyo accumulator mhinduro. Iko LOADCONST_VALUE iripo kubva pa0. Hwaro hwekugara hwakaenzana ne64N, apo N = LOADCONST_VALUE. Kana LOADCONST_VALUE yaiswa ku 2, kukosha kwekugara kwakaenzana ne 64. Iri basa rinogona kushandiswa sekutenderera kwakarerekera.
Mufananidzo unotevera unoratidza pre-mutoro unogara uchiitwa.
Mufananidzo 19. Pre-load Constant

Accumulator mhinduro

nguva dzose

Mult0

+/-

Mult1

+/b1

mhedzisiro

accum_sload sload_accum

Tarisa kune anotevera IP cores kune mamwe akawanda mashandisirwo: · ALTMULT_ACCUM · ALTMEMMULT · LPM_MULT
8.1.4. Kaviri Accumulator
Iyo kaviri accumulator ficha inowedzera imwe rejista mune accumulator mhinduro nzira. Iyo kaviri accumulator rejisita inotevera rejista inobuda, iyo inosanganisira wachi, wachi inogonesa, uye aclr. Iyo yekuwedzera accumulator rejista inodzosa mhedzisiro nekunonoka-kutenderera kumwe. Iyi ficha inoita kuti iwe uve maviri accumulator chiteshi ane yakafanana sosi kuverenga.
Iyi inotevera nhamba inoratidza iyo kaviri accumulator kuitiswa.

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Mufananidzo 20. Double Accumulator

Dou ble Accu mulator Register

Accu mulator feedba ck

Mult0

+/-

Mult1

+/b1

Mhedzisiro yeOutput Register

8.2. Verilog HDL Prototype
Unogona kuwana Intel FPGA Kuwedzera Adder kana ALTERA_MULT_ADD Verilog HDL prototype file (altera_mult_add_rtl.v) mu raibhurari megafunctions directory.
8.3. VHDL Chikamu Chiziviso
Chiziviso chechikamu cheVHDL chiri mu altera_lnsim_components.vhd mu libraryvhdl altera_lnsim directory.
8.4. VHDL LIBRARY_USE Declaration
VHDL LIBRARY-SHANDISA chiziviso hachidiwe kana ukashandisa VHDL Component Declaration.
LIBRARY altera_mf; SHANDISA altera_mf.altera_mf_components.all;

8.5. Signals

Matafura anotevera anonyora masaini ekuisa uye ekubuda kweiyo Multiply Adder Intel FPGA IPor ALTERA_MULT_ADD IP musimboti.

Tafura 28. Wanza Adder Intel FPGA IPor ALTERA_MULT_ADD Input Signals

Signal

Zvinodiwa

Tsanangudzo

dataa_0[]/dataa_1[]/

Ehe

dataa_2[]/data_3[]

Kuisa data kune yakawandisa. Chipo chekuisa [NUMBER_OF_MULTIPLIERS * WIDTH_A – 1 … 0] yakafara
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Chiratidzo datab_0[]/datab_1[]/ datab_2[]/datab_3[] datac_0[] /datac_1[]/ datac_2[]/datac_3[] wachi[1:0] aclr[1:0] sclr[1:0] ena [1:0] chiratidzo
signb
scanina[] accum_sload

Inodiwa Hongu Kwete
Kwete Kwete Kwete Kwete
Aihwa
Kwete Kwete

Tsanangudzo
Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kutsanangurwa yekuisa kukosha (X) kune aya masaini. Paunopa X kukosha kune aya masaini, iyo X kukosha inoparadzirwa pane inobuda masaini.
Kuisa data kune yakawandisa. Chiratidzo chekupinda [NUMBER_OF_MULTIPLIERS * WIDTH_B – 1 … 0] yakafara Mutevedzeri wemodhi yeiyi IP unotsigira kukosha kusingatariswe (X) kumasigiroti aya. Paunopa X kukosha kune aya masaini, iyo X kukosha inoparadzirwa pane inobuda masaini.
Kuisa data kune yakawandisa. Chiratidzo chekuisa [NUMBER_OF_MULTIPLIERS * WIDTH_C – 1, … 0] yakafara Sarudza INPUT yeSarudza preadder mode parameter kuti zviratidzo izvi zvigone. Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kutsanangurwa yekuisa kukosha (X) kune aya masaini. Paunopa X kukosha kune aya masaini, iyo X kukosha inoparadzirwa pane inobuda masaini.
Chiteshi chekuisa wachi kurejista inoenderana. Ichi chiratidzo chinogona kushandiswa chero rejista muIP musimboti. Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kutsanangurwa yekuisa kukosha (X) kune aya masaini. Paunopa X kukosha kune aya masaini, iyo X kukosha inoparadzirwa pane inobuda masaini.
Asynchronous yakajeka kupinza kune inoenderana rejista. Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kutsanangurwa yekuisa kukosha (X) kune aya masaini. Paunopa X kukosha kune aya masaini, iyo X kukosha inoparadzirwa pane inobuda masaini.
Synchronous yakajeka kupinza kune inoenderana rejista. Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kutsanangurwa yekuisa kukosha X kune aya masaini. Paunopa X kukosha kune aya masaini, iyo X kukosha inoparadzirwa pane inobuda masaini
Gonesa kuisa chiratidzo kune rejista inoenderana. Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kutsanangurwa yekuisa kukosha (X) kune aya masaini. Paunopa X kukosha kune aya masaini, iyo X kukosha inoparadzirwa pane inobuda masaini.
Inotsanangura nhamba inomiririra yekuwedzera A. Kana chiratidzo chechiratidzo chakakwira, mupupuri anobata chiratidzo chekuwedzera A chiratidzo senhamba yakasainwa. Kana iyo signa sign yakadzikira, iyo inowandisa inobata iyo yekuwedzera yekuisa A chiratidzo senhamba isina kusaina. Sarudza VARIABLE kune Ndeipi iyo inomiririra fomati yeMultipliers A yekuisa parameter yekugonesa iyi chiratidzo. Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kuverengerwa kukosha kwekuisa (X) kune iyi chiratidzo. Paunopa X kukosha kune iyi yekuisa, iyo X kukosha inoparadzirwa pane inobuda masaini.
Inotsanangura nhamba inomiririra yekuwedzera B chiratidzo chekuwedzera. Kana chiratidzo chechiratidzo chakakwira, mupupuri anobata chiratidzo chekuwedzera B sechiratidzo chechipiri chakasainwa. Kana chiratidzo chechiratidzo chakadzikira, muwedzere anobata chiratidzo chekuwedzera B senhamba isina kusaina. Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kuverengerwa kukosha kwekuisa (X) kune iyi chiratidzo. Paunopa X kukosha kune iyi yekuisa, iyo X kukosha inoparadzirwa pane inobuda masaini.
Kupinza cheni ye scan A. Sigina yekupinda [WIDTH_A – 1, … 0] yakafara. Kana iyo INPUT_SOURCE_A parameter ine kukosha kweSCANA, scanina[] chiratidzo chinodiwa.
Dynamically inotsanangura kana kukosha kwe accumulator kunoramba kuripo. Kana iyo accum_sload siginecha yakaderera, ipapo iyo yekuwedzera inobuda inotakurwa mu accumulator. Usashandise accum_sload uye sload_accum panguva imwe chete.
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Signal sload_accum
chainin[] addnsub1
addnsub3
coefsel0[] coefsel1[] coefsel2[] coefsel3[]

Inodiwa Nha
Kwete Kwete
Aihwa
Kwete Kwete Kwete Kwete

Tsanangudzo
Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kuverengerwa kukosha kwekuisa (X) kune iyi chiratidzo. Paunopa X kukosha kune iyi yekuisa, iyo X kukosha inoparadzirwa pane inobuda masaini.
Dynamically inotsanangura kana kukosha kwe accumulator kunoramba kuripo. Kana iyo sload_acum siginecha yakakwira, saka iyo yekuwedzera inobuda inotakurwa muaccumulator. Usashandise accum_sload uye sload_accum panguva imwe chete. Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kuverengerwa kukosha kwekuisa (X) kune iyi chiratidzo. Paunopa X kukosha kune iyi yekuisa, iyo X kukosha inoparadzirwa pane inobuda masaini.
Bhazi rekuisa mhedzisiro yeAdder kubva kumas apfuuratage. Nyora chiratidzo [WIDTH_CHAININ – 1, … 0] yakafara.
Itai kuwedzera kana kubvisa kune zvakabuda kubva pavaviri vekutanga vawandisa. Input 1 kune addnsub1 siginecha yekuwedzera zvinobuda kubva kune ekutanga maviri evazhinji. Input 0 kune addnsub1 siginecha yekubvisa zvinobuda kubva kune ekutanga maviri evazhinji. Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kuverengerwa kukosha kwekuisa (X) kune iyi chiratidzo. Paunopa X kukosha kune iyi yekuisa, iyo X kukosha inoparadzirwa pane inobuda masaini.
Itai kuwedzera kana kubvisa kune zvakabuda kubva pavaviri vekutanga vawandisa. Pinza 1 kune addnsub3 chiratidzo chekuwedzera zvinobuda kubva kune yechipiri pair yevazhinji. Input 0 kune addnsub3 siginecha yekubvisa zvinobuda kubva kune ekutanga maviri evazhinji. Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kuverengerwa kukosha kwekuisa (X) kune iyi chiratidzo. Paunopa X kukosha kune iyi yekuisa, iyo X kukosha inoparadzirwa pane inobuda masaini.
Coefficient input sign[0:3] kune yekutanga kuwandisa. Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kuverengerwa kukosha kwekuisa (X) kune iyi chiratidzo. Paunopa X kukosha kune iyi yekuisa, iyo X kukosha inoparadzirwa pane inobuda masaini.
Coefficient input signal[0:3] kune yechipiri yakawedzera. Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kuverengerwa kukosha kwekuisa (X) kune iyi chiratidzo. Paunopa X kukosha kune iyi yekuisa, iyo X kukosha inoparadzirwa pane inobuda masaini.
Coefficient input sign[0:3] kune yechitatu inowandisa. Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kuverengerwa kukosha kwekuisa (X) kune iyi chiratidzo. Paunopa X kukosha kune iyi yekuisa, iyo X kukosha inoparadzirwa pane inobuda masaini.
Coefficient yekupinza chiratidzo [0:3] kune yechina yekuwedzera. Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kuverengerwa kukosha kwekuisa (X) kune iyi chiratidzo. Paunopa X kukosha kune iyi yekuisa, iyo X kukosha inoparadzirwa pane inobuda masaini.

Tafura 29. Wedzera Adder Intel FPGA IP Output Signals

Signal

Zvinodiwa

Tsanangudzo

mhedzisiro []

Ehe

Multiplier goho chiratidzo. Chiratidzo chekubuda [WIDTH_RESULT – 1 … 0] yakafara

Iyo yekunyepedzera modhi yeiyi IP inotsigira isina kutsanangurwa kukosha kwekubuda (X). Paunopa X kukosha sekupinza, kukosha kweX kunoparidzwa pane iyi chiratidzo.

scanouta []

Aihwa

Kubuda kwescan cheni A. Chiratidzo chekubuda [WIDTH_A – 1..0] yakafara.

Sarudza zvinopfuura 2 kune nhamba dzevanowedzera uye sarudza Scan cheni yekuisa kuti Chii chinopinza A chekuwedzera chakabatana neparameter kugonesa chiratidzo ichi.

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8.6. Paramita

8.6.1. General Tab

Tafura 30. General Tab

Parameter

IP Yakagadzirwa Parameter

Value

Nhamba yevawandisa ndeipi?

nhamba_ye_m 1 - 4 ultipliers

Mabhazi ekuisa maA wide_a anofanira kunge akafara zvakadii?

1-256

Mabhazi ekupinza eB width_b anofanira kunge akapamhama zvakadii?

1-256

Bhazi rinobuda ne 'result' rinofanira kunge rakafara zvakadii?

width_result

1-256

Gadzira wachi yakabatana inogonesa wachi yega yega

gui_associate On d_clock_enable Off e

8.6.2. Extra Modes Tab

Tafura 31. Extra Modes Tab

Parameter

IP Yakagadzirwa Parameter

Value

Outputs Configuration

gui_output_re On

gister

Off

Chii chinobva pakuisa wachi?

gui_output_re gister_clock

Clock0 Clock1 Clock2

Ndekupi kunobva kune asynchronous clear kupinza?

gui_output_re gister_aclr

HAPANA ACLR0 ACLR1

Ndekupi kunobva synchronous clear input?

gui_output_re gister_sclr

HAPANA SCLR0 SCLR1

Adder Operation

Ndeipi oparesheni inofanirwa kuitwa pane zvinobuda zvevaviri vekutanga vanowedzera?

gui_multiplier 1_direction

ADD, SUB, VARIABLE

Default Value 1
16

Tsanangudzo
Nhamba yevazhinji vanozowedzerwa pamwechete. Makoshi ari 1 kusvika 4. Taura hupamhi hwechiteshi chedata[].

Taura hupamhi hwedatab[] chiteshi.

Taura mufarwa wemubairo[] chiteshi.

Off

Sarudza iyi sarudzo kuti ugadzire wachi inogonesa

pawachi imwe neimwe.

Default Value

Tsanangudzo

Off Clock0
HAKUNA HAPANA

Sarudza iyi sarudzo yekugonesa kuburitsa rejista yeadder module.
Sarudza Clock0 , Clock1 kana Clock2 kugonesa uye tsanangura wachi sosi yemarejista ekubuda. Iwe unofanirwa kusarudza Rejisa kubuda kweiyo adder unit kuti ugone iyi parameter.
Inotsanangura iyo asynchronous clear source yeadder inobuda rejista. Iwe unofanirwa kusarudza Rejisa kubuda kweiyo adder unit kuti ugone iyi parameter.
Inotsanangura iyo synchronous clear source yeadder output register. Iwe unofanirwa kusarudza Rejisa kubuda kweiyo adder unit kuti ugone iyi parameter.

ADD

Sarudza oparesheni yekuwedzera kana yekubvisa kuti uite kune zvinobuda pakati pekutanga neyechipiri vawandisa.
· Sarudza ADD kuita yekuwedzera oparesheni.
· Sarudza SUB kuita oparesheni yekubvisa.
· Sarudza VARIABLE kushandisa addnsub1 chiteshi chekuwedzera / kubvisa kutonga.
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Parameter

IP Yakagadzirwa Parameter

Value

Nyora 'addnsub1' kuisa

gui_addnsub_ Pa multiplier_reg Off ister1

Chii chinobva pakuisa wachi?

gui_addnsub_ multiplier_reg ister1_clock

Clock0 Clock1 Clock2

Ndekupi kunobva kune asynchronous clear kupinza?

gui_addnsub_ multiplier_aclr 1

HAPANA ACLR0 ACLR1

Ndekupi kunobva synchronous clear input?

gui_addnsub_ multiplier_sclr 1

HAPANA SCLR0 SCLR1

Ndekupi kuvhiya kunofanirwa kuitwa pane zvinobuda zvechipiri chevanowedzera?

gui_multiplier 3_direction

ADD, SUB, VARIABLE

Nyora 'addnsub3' kuisa

gui_addnsub_ Pa multiplier_reg Off ister3

Chii chinobva pakuisa wachi?

gui_addnsub_ multiplier_reg ister3_clock

Clock0 Clock1 Clock2

Default Value
Off Clock0 HAPANA ANOWEDZERA
Off Clock0

Tsanangudzo
Kana VARIABLE kukosha kwasarudzwa: · Dhiraivha addnsub1 chiratidzo kusvika kumusoro kwe
kuwedzera kushanda. · Dhiraivha addnsub1 chiratidzo kune yakaderera kune
Kubvisa kushanda. Iwe unofanirwa kusarudza anopfuura maviri ekuwedzera kuti agonese iyi parameter.
Sarudza iyi sarudzo yekugonesa rejista yekuisa yeaddnsub1 port. Iwe unofanirwa kusarudza VARIABLE yeIi oparesheni inofanirwa kuitwa pane zvinobuda zvevaviri vekutanga vanowedzera kuti iyi parameter igone.
Sarudza Clock0 , Clock1 kana Clock2 kuti utaure chiratidzo chewachi yekupinda yeaddnsub1 rejista. Iwe unofanirwa kusarudza Nyoresa 'addnsub1' kuisa kuti uite iyi parameter.
Inotsanangura iyo asynchronous yakajeka sosi yeiyo addnsub1 rejista. Iwe unofanirwa kusarudza Nyoresa 'addnsub1' kuisa kuti uite iyi parameter.
Inotsanangura iyo synchronous yakajeka sosi yeaddnsub1 rejista. Iwe unofanirwa kusarudza Nyoresa 'addnsub1' kuisa kuti uite iyi parameter.
Sarudza oparesheni yekuwedzera kana kubvisa kuti uite kune zvinobuda pakati pechitatu nechina vawandisa. · Sarudza ADD kuti uwedzere
oparesheni. · Sarudza SUB kuita kubvisa
kushanda. · Sarudza VARIABLE kushandisa addnsub1
port for dynamic kuwedzera/kubvisa control. Kana VARIABLE kukosha kwasarudzwa: · Dhiraivha addnsub1 chiratidzo kusvika kumusoro kuti uwedzere kushanda. · Dhiraivha addnsub1 chiratidzo kune yakaderera yekubvisa mashandiro. Iwe unofanirwa kusarudza kukosha 4 kune Ndeipi nhamba yevanowedzera? kugonesa iyi parameter.
Sarudza iyi sarudzo yekugonesa rejista yekuisa yeaddnsub3 chiratidzo. Iwe unofanirwa kusarudza VARIABLE yeIi oparesheni inofanirwa kuitwa pane zvinobuda zvepairi yechipiri yevazhinji kuti vagone kuita iyi parameter.
Sarudza Clock0 , Clock1 kana Clock2 kuti utaure chiratidzo chewachi yekupinda yeaddnsub3 rejista. Iwe unofanirwa kusarudza Register 'addnsub3′ kuisa kuti uite iyi parameter.
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Parameter
Ndekupi kunobva kune asynchronous clear kupinza?

IP Yakagadzirwa Parameter

Value

gui_addnsub_ multiplier_aclr 3

HAPANA ACLR0 ACLR1

Ndekupi kunobva synchronous clear input?

gui_addnsub_ multiplier_sclr 3

HAPANA SCLR0 SCLR1

Polarity Gonesa `use_subadd'

gui_use_subn On

wedzera

Off

8.6.3. Multipliers Tab

Tafura 32. Multipliers Tab

Parameter

IP Yakagadzirwa Parameter

Value

Chii chinonzi

gui_represent

chimiro chekumiririra ation_a

zve Multipliers A zvekushandisa?

AKASAIWA, HAZVISINA KUSAINWA, ZVINOSINANA

Nyora `signa' yekupinda

gui_register_s On

igna

Off

Chii chinobva pakuisa wachi?

gui_register_s igna_clock

Clock0 Clock1 Clock2

Ndekupi kunobva kune asynchronous clear kupinza?

gui_register_s igna_aclr

HAPANA ACLR0 ACLR1

Ndekupi kunobva synchronous clear input?

gui_register_s igna_sclr

HAPANA SCLR0 SCLR1

Chii chinonzi

gui_represent

chimiro chekumiririra_b

ye Multipliers B mapinjiro?

AKASAIWA, HAZVISINA KUSAINWA, ZVINOSINANA

Nyora `signb' kuisa

gui_register_s On

igb

Off

Default Value HAPANA
HAKUNA

Tsanangudzo
Inotsanangura iyo asynchronous yakajeka sosi yeiyo addnsub3 rejista. Iwe unofanirwa kusarudza Nyoresa 'addnsub3' kuisa kuti uite iyi parameter.
Inotsanangura iyo synchronous yakajeka sosi yeaddnsub3 rejista. Iwe unofanirwa kusarudza Register 'addnsub3′ kuisa kuti uite iyi parameter.

Off

Sarudza iyi sarudzo yekudzosera kumashure basa

ye addnsub yekupinza port.

Dhiraivha addnsub kusvika kumusoro kuitira kubvisa.

Dhiraivha addnsub kusvika pasi kuti uwedzere kushanda.

Default Value

Tsanangudzo

ZVISINA KUSINA

Off

Sarudza iyi sarudzo kuti ugone kusaina

rejista.

Iwe unofanirwa kusarudza VARIABLE kukosha kweNdeipi iyo inomiririra fomati yeMultipliers A yekupinda? parameter kugonesa iyi sarudzo.

Wachi0

Sarudza Clock0, Clock1 kana Clock2 kugonesa uye kududzira chiratidzo chewachi yekupinda yekunyoresa siginecha.
Iwe unofanirwa kusarudza Nyoresa `signa' kuisa kuti ugone kuita iyi parameter.

HAKUNA

Inotsanangura asynchronous clear source yesigna register.
Iwe unofanirwa kusarudza Nyoresa `signa' kuisa kuti ugone kuita iyi parameter.

HAKUNA

Ino tsanangura iyo synchronous clear source ye signa register.
Iwe unofanirwa kusarudza Nyoresa `signa' kuisa kuti ugone kuita iyi parameter.

ZVISINA KUSIGINWA

Off

Sarudza iyi sarudzo yekugonesa signb

rejista.

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Parameter

IP Yakagadzirwa Parameter

Value

Default Value

Chii chinobva pakuisa wachi?

gui_register_s ignb_clock

Clock0 Clock1 Clock2

Wachi0

Ndekupi kunobva kune asynchronous clear kupinza?

gui_register_s igb_aclr

HAPANA ACLR0 ACLR1

Ndekupi kunobva synchronous clear input?

gui_register_s igb_sclr

HAPANA SCLR0 SCLR1

Input Configuration
Nyoresa kuisa A yekuwanda
Chii chinobva pakuisa wachi?

gui_input_reg On

ister_a

Off

gui_input_reg ister_a_clock

Clock0 Clock1 Clock2

HAKUNA HAPANA
Off Clock0

Ndekupi kunobva kune asynchronous clear kupinza?

gui_input_reg ister_a_aclr

HAPANA ACLR0 ACLR1

Ndekupi kunobva synchronous clear input?

gui_input_reg ister_a_sclr

HAPANA SCLR0 SCLR1

Nyoresa kuisa B yekuwedzeredza
Chii chinobva pakuisa wachi?

gui_input_reg On

ister_b

Off

gui_input_reg ister_b_clock

Clock0 Clock1 Clock2

HAPANA NONE Off Clock0

Ndekupi kunobva kune asynchronous clear kupinza?

gui_input_reg ister_b_aclr

HAPANA ACLR0 ACLR1

HAKUNA

Ndekupi kunobva synchronous clear input?

gui_input_reg ister_b_sclr

HAPANA SCLR0 SCLR1

HAKUNA

Chii chinoiswa A chemupupuri chakabatana nacho?

gui_multiplier Multiplier input Multiplier

_a_input

Skena chain input

Tsanangudzo
Iwe unofanirwa kusarudza VARIABLE kukosha kweNdeipi iyo inomiririra fomati yeMultipliers B yekupinda? parameter kugonesa iyi sarudzo.
Sarudza Clock0, Clock1 kana Clock2 kugonesa uye kududzira chiratidzo chewachi yekupinda yerejista yesaini. Iwe unofanirwa kusarudza Nyoresa `signb' kuisa kuti uite iyi parameter.
Inotsanangura iyo asynchronous clear source ye signb register. Iwe unofanirwa kusarudza Nyoresa `signb' kuisa kuti uite iyi parameter.
Inotsanangura kunobva kwakajeka kwechinyorwa chechiratidzo. Iwe unofanirwa kusarudza Nyoresa `signb' kuisa kuti uite iyi parameter.
Sarudza iyi sarudzo kuti ugone kugonesa rejista yekuisa dataa bhazi rekuisa.
Sarudza Clock0, Clock1 kana Clock2 kugonesa uye kududzira rejista yekuisa wachi chiratidzo chedhata yekupinza bhazi. Iwe unofanirwa kusarudza Nyoresa yekuisa A yeakawanda kuti agonese iyi parameter.
Inotsanangura rejista asynchronous clear source yedataa rekuisa bhazi. Iwe unofanirwa kusarudza Nyoresa yekuisa A yeakawanda kuti agonese iyi parameter.
Inotsanangura regisitasi yakajeka kwakabva dataa rekuisa bhazi. Iwe unofanirwa kusarudza Nyoresa yekuisa A yeakawanda kuti agonese iyi parameter.
Sarudza iyi sarudzo yekugonesa rejista yekuisa yedatab bhazi rekuisa.
Sarudza Clock0, Clock1 kana Clock2 kugonesa uye kududzira rejista yekuisa wachi chiratidzo chebhasi rekuisa datab. Iwe unofanirwa kusarudza Nyoresa yekuisa B yeanowedzera kuti agonese iyi parameter.
Inotsanangura rejista asynchronous clear source yebhazi rekuisa datab. Iwe unofanirwa kusarudza Nyoresa yekuisa B yeakawanda kuti agone kuita iyi parameter.
Inotsanangura register yakajeka kwakabva bhazi rekuisa datab. Iwe unofanirwa kusarudza Nyoresa yekuisa B yeanowedzera kuti agonese iyi parameter.
Sarudza kwainopinza yekuisa A yekuwedzera.
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Parameter

IP Yakagadzirwa Parameter

Value

Scanout A Register Configuration

Nyoresa zvakabuda zve scan chain

gui_scanouta On

_rejista

Off

Chii chinobva pakuisa wachi?

gui_scanouta _register_clock k

Clock0 Clock1 Clock2

Ndekupi kunobva kune asynchronous clear kupinza?

gui_scanouta _register_aclr

HAPANA ACLR0 ACLR1

Ndekupi kunobva synchronous clear input?

gui_scanouta _register_sclr

HAPANA SCLR0 SCLR1

8.6.4. Preadder Tab

Tafura 33. Preadder Tab

Parameter

IP Yakagadzirwa Parameter

Value

Sarudza preadder mode

preadder_mo de

SIMPLE, COEF, INPUT, SQUARE, CONSTANT

Default Value

Tsanangudzo
Sarudza Multiplier kuisa kuti ushandise dataa yekupinza bhazi senzvimbo yekuwedzera. Sarudza Kupinza cheni yeScan kuti ushandise bhazi rekuisa scanin senzvimbo yekuwedzera uye wogonesa bhazi rekubuda. Iyi parameter inowanikwa paunosarudza 2, 3 kana 4 yeNhamba yezviwanziridzo ndeipi? parameter.

Off Clock0 HAPANA HAPANA

Sarudza iyi sarudzo kuti ugone kugonesa rejista yekubuda kwebhazi rescanouta rinobuda.
Iwe unofanirwa kusarudza Scan ketani yekupinza yeChii chinoiswa A chekuwedzera chakabatana nacho? parameter kugonesa iyi sarudzo.
Sarudza Clock0, Clock1 kana Clock2 kugonesa uye kududzira rejista yekuisa wachi chiratidzo che scanouta inobuda bhazi.
Iwe unofanirwa kubatidza Rejisa kubuda kweiyo scan chain parameter kuti uite iyi sarudzo.
Inotsanangura rejista asynchronous clear source yebhazi rekubuda kwe scanouta.
Iwe unofanirwa kubatidza Rejisa kubuda kweiyo scan chain parameter kuti uite iyi sarudzo.
Inotsanangura register yakajeka kunobva bhazi re scanouta.
Iwe unofanirwa kusarudza Rejisa kubuda kweiyo scan chain parameter kuti uite iyi sarudzo.

Default Value
SIMPLE

Tsanangudzo
Inotsanangura maitiro ekushanda kwepreadder module. SIMPLE: Iyi modhi inodarika preadder. Iyi ndiyo default mode. COEF: Iyi modhi inoshandisa kubuda kwe preadder uye coefsel bhazi rekuisa semapupu kune anowandisa. INPUT: Iyi modhi inoshandisa kuburitsa kwepreadder uye datac yekupinza bhazi semapupu kune anowandisa. SQUARE: Iyi modhi inoshandisa kuburitsa kwepreadder sezviviri zvinopinza kune yakawedzera.
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Parameter

IP Yakagadzirwa Parameter

Value

Sarudza nzira yepreadder

gui_preadder ADD,

_direction

SUB

Mabhazi ekupinza eC width_c anofanira kunge akapamhama zvakadii?

1-256

Data C Input Register Configuration

Bhalisa datac input

gui_datac_inp On

ut_register

Off

Chii chinobva pakuisa wachi?

gui_datac_inp ut_register_cl ock

Clock0 Clock1 Clock2

Ndekupi kunobva kune asynchronous clear kupinza?

gui_datac_inp ut_register_a clr

HAPANA ACLR0 ACLR1

Ndekupi kunobva synchronous clear input?

gui_datac_inp ut_register_sc lr

HAPANA SCLR0 SCLR1

Coefficients
Coef yakafara sei?

width_coef

1-27

Coef Register Configuration

Nyoresa coefsel input

gui_coef_regi On

ster

Off

Chii chinobva pakuisa wachi?

gui_coef_regi ster_clock

Clock0 Clock1 Clock2

Default Value
ADD
16

Tsanangudzo
CONSTANT: Iyi modhi inoshandisa dataa rekuisa bhazi rine preadder rakapfuura uye coefsel rekuisa bhazi semapupu kune anowandisa.
Inotsanangura kushanda kwepreadder. Kugonesa iyi parameter, sarudza zvinotevera zveSarudza preadder mode: · COEF · INPUT · SQUARE or · CONSTANT
Inotsanangura huwandu hwemabhiti eC bhazi rekuisa. Iwe unofanirwa kusarudza INPUT yeSarudza preadder modhi kuti ugone kuita iyi parameter.

Pa Clock0 HAPANA

Sarudza iyi sarudzo kuti ugone kugonesa rejista yekupinza yedatac bhazi rekuisa. Iwe unofanirwa kuseta INPUT kuSarudza preadder mode parameter kuti uite iyi sarudzo.
Sarudza Clock0, Clock1 kana Clock2 kuti utsanangure chiratidzo chewachi yekupinda yedatac yekuisa rejista. Iwe unofanirwa kusarudza Nyoresa datac yekuisa kuti ugone iyi parameter.
Inotsanangura iyo asynchronous yakajeka sosi yeiyo datac yekupinza rejista. Iwe unofanirwa kusarudza Nyoresa datac yekuisa kuti ugone iyi parameter.
Inotsanangura iyo synchronous clear source yedatac input register. Iwe unofanirwa kusarudza Nyoresa datac yekuisa kuti ugone iyi parameter.

Inotsanangura nhamba yemabhiti e

coefsel input bhazi.

Iwe unofanirwa kusarudza COEF kana CONSTANT yepreadder mode kuti igone kugonesa iyi parameter.

Pa Clock0

Sarudza iyi sarudzo yekugonesa rejista yekupinza yebhazi rekuisa coefsel. Iwe unofanirwa kusarudza COEF kana CONSTANT yepreadder mode kuti igone kugonesa iyi parameter.
Sarudza Clock0 , Clock1 kana Clock2 kuti utsanangure chiratidzo chewachi yekuisa yerejisita rekuisa coefsel. Iwe unofanirwa kusarudza Nyoresa iyo coefsel yekuisa kuti uite iyi parameter.
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Parameter
Ndekupi kunobva kune asynchronous clear kupinza?

IP Yakagadzirwa Parameter

Value

gui_coef_regi ster_aclr

HAPANA ACLR0 ACLR1

Ndekupi kunobva synchronous clear input

gui_coef_regi ster_sclr

HAPANA SCLR0 SCLR1

Coefficient_0 Configuration

coef0_0 kune coef0_7

0x00000 0xFFFFFF

Coefficient_1 Configuration

coef1_0 kune coef1_7

0x00000 0xFFFFFF

Coefficient_2 Configuration

coef2_0 kune coef2_7

0x00000 0xFFFFFF

Coefficient_3 Configuration

coef3_0 kune coef3_7

0x00000 0xFFFFFF

8.6.5. Accumulator Tab

Tafura 34. Accumulator Tab

Parameter

IP Yakagadzirwa Parameter

Value

Bvisa accumulator?

accumulator

EHE AIWA

Chii chinonzi accumulator operation type?

accum_directi ADD,

SUB

Default Value HAPANA
HAKUNA
0x0000000 0
0x0000000 0
0x0000000 0
0x0000000 0

Tsanangudzo
Inotsanangura asynchronous clear source yecoefsel register yekupinza. Iwe unofanirwa kusarudza Nyoresa iyo coefsel yekuisa kuti uite iyi parameter.
Inotsanangura iyo synchronous clear source yecoefsel register yekupinza. Iwe unofanirwa kusarudza Nyoresa iyo coefsel yekuisa kuti uite iyi parameter.
Inotsanangura kukosha kwekoefficient yeiyi yekutanga kuwedzera. Huwandu hwemabhiti hunofanira kufanana nehwakatsanangurwa muna Kufara kwecoef kunofanira kunge kwakakura zvakadii? parameter. Iwe unofanirwa kusarudza COEF kana CONSTANT yepreadder mode kuti igone kugonesa iyi parameter.
Inotsanangura kukosha kwekoefficient yeichi chiwedzere chechipiri. Huwandu hwemabhiti hunofanira kufanana nehwakatsanangurwa muna Kufara kwecoef kunofanira kunge kwakakura zvakadii? parameter. Iwe unofanirwa kusarudza COEF kana CONSTANT yepreadder mode kuti igone kugonesa iyi parameter.
Inotsanangura kukosha kwekoefficient yechitatu chekuwedzera. Huwandu hwemabhiti hunofanira kufanana nehwakatsanangurwa muna Kufara kwecoef kunofanira kunge kwakakura zvakadii? parameter. Iwe unofanirwa kusarudza COEF kana CONSTANT yepreadder mode kuti igone kugonesa iyi parameter.
Inotsanangura kukosha kwekoefficient yeiyi yechina yekuwedzeredza. Huwandu hwemabhiti hunofanira kufanana nehwakatsanangurwa muna Kufara kwecoef kunofanira kunge kwakakura zvakadii? parameter. Iwe unofanirwa kusarudza COEF kana CONSTANT yepreadder mode kuti igone kugonesa iyi parameter.

Default Value NO
ADD

Tsanangudzo
Sarudza YES kugonesa accumulator. Iwe unofanirwa kusarudza Rejisa kubuda kweadder unit paunenge uchishandisa accumulator chimiro.
Inotsanangura kushanda kweaccumulator: · ADD yekuwedzera kushanda · SUB yekubvisa. Iwe unofanirwa kusarudza YES yeKugonesa accumulator? parameter kugonesa iyi sarudzo.
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Parameter
Preload Constant Gonesa preload nguva dzose

IP Yakagadzirwa Parameter

Value

gui_ena_prelo On

ad_const

Off

Chii chinonzi accumulate port chakabatana nacho?

gui_accumula ACCUM_SLOAD, te_port_select SLOAD_ACCUM

Sarudza kukosha kwe preload loadconst_val 0 - 64

nguva dzose

Chii chinobva pakuisa wachi?

gui_accum_sl oad_register_ wachi

Clock0 Clock1 Clock2

Ndekupi kunobva kune asynchronous clear kupinza?

gui_accum_sl oad_register_ aclr

HAPANA ACLR0 ACLR1

Ndekupi kunobva synchronous clear input?

gui_accum_sl oad_register_ sclr

HAPANA SCLR0 SCLR1

Gonesa kaviri accumulator

gui_double_a On

ccum

Off

Default Value

Tsanangudzo

Off

Gonesa iyo accum_sload kana

sload_accum masaini uye kunyoresa kupinza

kuti usarudze zvine simba zvinopinza ku

kuunganidza.

Kana accum_sload yakadzikira kana sload_accum, iyo yekuwedzera inobuda inodyiswa mune accumulator.

Kana accum_sload yakakwira kana sload_accum, mushandisi anotsanangurwa preload yenguva dzose inodyiswa mune accumulator.

Iwe unofanirwa kusarudza YES yeKugonesa accumulator? parameter kugonesa iyi sarudzo.

ACCUM_SL OAD

Inotsanangura maitiro e accum_sload/ sload_accum chiratidzo.
ACCUM_SLOAD: Dhiraivha accum_sload yakaderera kuti uise iyo yakawedzera kubuda kune accumulator.
SLOAD_ACCUM: Dhiraivha sload_accum yakakwira kuti uise iyo yakawedzera kubuda kune accumulator.
Iwe unofanirwa kusarudza Bvumira preload nguva dzose sarudzo yekugonesa iyi parameter.

Taura preset inoramba ichikosha.

Ukoshi uhwu hunogona kuva 2N uko N iri preset inogara kukosha.

Kana N = 64, inomiririra zero inogara iripo.

Iwe unofanirwa kusarudza Bvumira preload nguva dzose sarudzo yekugonesa iyi parameter.

Wachi0

Sarudza Clock0, Clock1 kana Clock2 kuti utaure chiratidzo chewachi yekupinda yeaccum_sload/sload_accum rejista.
Iwe unofanirwa kusarudza Bvumira preload nguva dzose sarudzo yekugonesa iyi parameter.

HAKUNA

Inotsanangura iyo asynchronous yakajeka sosi yeiyo accum_sload/sload_accum rejista.
Iwe unofanirwa kusarudza Bvumira preload nguva dzose sarudzo yekugonesa iyi parameter.

HAKUNA

Inotsanangura iyo synchronous yakajeka sosi yeiyo accum_sload/sload_accum rejista.
Iwe unofanirwa kusarudza Bvumira preload nguva dzose sarudzo yekugonesa iyi parameter.

Off

Inogonesa iyo kaviri accumulator rejista.

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8.6.6. Systolic/Chainout Tab

Tafura 35. Systolic/Chainout Adder Tab

Parameter Inogonesa chainout adder

IP Yakagadzirwa Parameter

Value

chainout_add YES,

AIHWA

Chii chinonzi chainout adder operation type?

chainout_add ADD,

er_direction

SUB

Bvisa `negate' mapindiro echainout adder?

Port_negate

PORT_USED, PORT_UNUSED

Nyoresa `kuramba' kuisa? negate_regist er

ISINA KUREGWADZWA, CLOCK0, CLOCK1, CLOCK2, CLOCK3

Ndekupi kunobva kune asynchronous clear kupinza?

negate_aclr

HAPANA ACLR0 ACLR1

Ndekupi kunobva synchronous clear input?

negate_sclr

HAPANA SCLR0 SCLR1

Systolic Kunonoka
Gonesa systolic kunonoka marejista

gui_systolic_d On

elay

Off

Chii chinobva pakuisa wachi?

gui_systolic_d CLOCK0,

elay_clock

WACHI1,

Default Value
AIHWA

Tsanangudzo
Sarudza YES kuti ugone chainout adder module.

ADD

Inotsanangura chainout adder operation.
Pakubvisa, SIGNED inofanirwa kusarudzirwa Ndeipi iyo inomiririra fomati yeMultipliers A yekupinda? uye Ndeipi iyo inomiririra fomati yeMultipliers B yekupinda? muMultipliers Tab.

PORT_UN USED

Sarudza PORT_USED kuti ugone kusarudzika chiratidzo chekupinda.
Iyi parameter haina kushanda kana chainout adder yakadzimwa.

UNREGIST ERED

Kugonesa rejista yekuisa yekuramba chiratidzo chekuisa uye inotsanangura chiratidzo chewachi yekupinda yerejista yekuramba.
Sarudza UNREGISTERED kana regisita rekuisa regedhi risingade
Iyi parameter haina basa kana ukasarudza:
· HAPANA yekugonesa chainout adder kana
· PORT_UNUSED yeKugonesa 'negate' mapindiro echainout adder? parameter kana

HAKUNA

Inotsanangura iyo asynchronous yakajeka sosi yerejista yekuramba.
Iyi parameter haina basa kana ukasarudza:
· HAPANA yekugonesa chainout adder kana
· PORT_UNUSED yeKugonesa 'negate' mapindiro echainout adder? parameter kana

HAKUNA

Inotsanangura iyo synchronous clear source yerejista yekuramba.
Iyi parameter haina basa kana ukasarudza:
· HAPANA yekugonesa chainout adder kana
· PORT_UNUSED yeKugonesa 'negate' mapindiro echainout adder? parameter kana

Off CLOCK0

Sarudza iyi sarudzo yekugonesa systolic modhi. Iyi parameter inowanikwa kana ukasarudza 2, kana 4 yeNhamba yevawandisa ndeipi? parameter. Iwe unofanirwa kugonesa iyo Rejista kubuda kweiyo adder unit kushandisa systolic kunonoka marejista.
Inotsanangura chiratidzo chewachi yekupinda yesystolic kunonoka register.
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Parameter

IP Yakagadzirwa Parameter

Value

WACHI2,

Ndekupi kunobva kune asynchronous clear kupinza?

gui_systolic_d elay_aclr

HAPANA ACLR0 ACLR1

Ndekupi kunobva synchronous clear input?

gui_systolic_d elay_sclr

HAPANA SCLR0 SCLR1

Default Value
HAKUNA
HAKUNA

Tsanangudzo
Iwe unofanirwa kusarudza kugonesa systolic kunonoka marejista kuti uite iyi sarudzo.
Inotsanangura iyo asynchronous yakajeka sosi yeiyo systolic kunonoka rejista. Iwe unofanirwa kusarudza kugonesa systolic kunonoka marejista kuti uite iyi sarudzo.
Inotsanangura iyo synchronous yakajeka sosi yeiyo systolic kunonoka rejista. Iwe unofanirwa kusarudza kugonesa systolic kunonoka marejista kuti uite iyi sarudzo.

8.6.7. Pipelining Tab

Tafura 36. Pipelining Tab

Parameter Pipelining Configuration

IP Yakagadzirwa Parameter

Value

Iwe unoda kuwedzera pipeline regiji kune inopinza?

gui_pipelining Kwete, Hongu

Default Value
Aihwa

Ndapota tsanangura

latency

nhamba ye latency wachi

cycles

Chero kukosha kukuru 0 pane 0

Chii chinobva pakuisa wachi?

gui_input_late ncy_clock

Clock0, Clock1, Clock2

Ndekupi kunobva kune asynchronous clear kupinza?

gui_input_late ncy_aclr

HAPANA ACLR0 ACLR1

Ndekupi kunobva synchronous clear input?

gui_input_late ncy_sclr

HAPANA SCLR0 SCLR1

Clock0 HAPANA HAPANA

Tsanangudzo
Sarudza Hongu kugonesa imwe nhanho yerejista yepombi kune masaini ekuisa. Iwe unofanirwa kutsanangura kukosha kukuru kupfuura 0 kune Ndapota tsanangura nhamba yenguva yenguva yewachi parameter.
Inotsanangura yaunoda latency mumawachi. Imwe nhanho yerejista yepombi = 1 latency muwachi kutenderera. Iwe unofanirwa kusarudza YES yeUnoda kuwedzera pombi rejista kune yekuisa? kugonesa iyi sarudzo.
Sarudza Clock0, Clock1 kana Clock2 kugonesa uye kududzira pombi regiji yekuisa chiratidzo chewachi. Iwe unofanirwa kusarudza YES yeUnoda kuwedzera pombi rejista kune yekuisa? kugonesa iyi sarudzo.
Inotsanangura rejista asynchronous clear source yekuwedzera pombi regiji. Iwe unofanirwa kusarudza YES yeUnoda kuwedzera pombi rejista kune yekuisa? kugonesa iyi sarudzo.
Inotsanangura register yakajeka kwakabva kune yekuwedzera pombi regiji. Iwe unofanirwa kusarudza YES yeUnoda kuwedzera pombi rejista kune yekuisa? kugonesa iyi sarudzo.

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683490 | 2020.10.05 Tumira Mhinduro

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core

Chenjerera:

Intel yakabvisa rutsigiro rweiyi IP muIntel Quartus Prime Pro Edition vhezheni 20.3. Kana iyo IP musimboti mudhizaini yako yakanangana nemidziyo muIntel Quartus Prime Pro Edition, unogona kutsiva IP neLPM_MULT Intel FPGA IP kana kugadzirazve IP uye kuunganidza dhizaini yako uchishandisa Intel Quartus Prime Standard Edition software.

Iyo ALTMEMMULT IP musimboti inoshandiswa kugadzira memory-based multiplier uchishandisa onchip memory blocks inowanikwa muIntel FPGAs (ine M512, M4K, M9K, uye MLAB memory blocks). Iyi IP musimboti inobatsira kana iwe usina zviwanikwa zvakakwana zvekushandisa iyo inowandisa mune logic zvinhu (LEs) kana yakatsaurwa yekuwedzera zviwanikwa.
Iyo ALTMEMMULT IP musimboti ibasa rinoenderana rinoda wachi. Iyo ALTMEMMULT IP musimboti inoshandisa yekuwedzeredza ine diki yekupinda uye latency inogoneka kune yakapihwa seti yemaparamita uye zvakatemwa.
Iyi inotevera nhamba inoratidza madoko eiyo ALTMEMMULT IP musimboti.

Mufananidzo 21. ALTMEMMULT Ports

ALTMEMMULT

data_in[] sload_data coeff_in[]

mhedzisiro[] mhedzisiro_valid load_done

sload_coeff

scl wachi
inst

Ruzivo Rwunofambidzana Mamiriro ezvinhu ari papeji 71

9.1. Zvimiro
Iyo ALTMEMMULT IP musimboti inopa zvinotevera maficha: · Inogadzira chete ndangariro-based multiplier uchishandisa on-chip memory blocks inowanikwa mu.
Intel FPGAs · Inotsigira hupamhi hwedata hwe1 bits · Inotsigira yakasainwa uye isina kusaina data inomiririra fomati · Inotsigira pipelining ine yakagadziriswa inobuda latency

ISO 9001:2015 Yakanyoreswa

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05
* Inochengeta maawandiro enguva dzose mundangariro-yekuwana ndangariro (RAM)
· Inopa sarudzo yekusarudza iyo RAM block mhando
· Inotsigira inosarudzika synchronous yakajeka uye inotakura-yekudzora yekupinza madoko
9.2. Verilog HDL Prototype
Iyi inotevera Verilog HDL prototype iri muVerilog Dhizaini File (.v) altera_mf.v mune eda synthesis directory.
module altmemmult #( parameter coeff_representation = “SIGNED”, parameter coefficient0 = “UNUSED”, parameter data_representation = “SIGNED”, parameter yaida_device_family = “isina kushandiswa”, parameter max_clock_cycles_per_result = 1, parameter nhamba_ye_block = 1, paramita nhamba_ye_chivharo total_latency = 1, parameter width_c = 1, parameter width_d = 1, parameter width_r = 1, parameter width_s = 1, parameter lpm_type = "altmemmult", parameter lpm_hint = "isina kushandiswa") (waya yekupinda, waya yekupinda [width_c-1: 0]coeff_in, waya yekupinda [width_d-1:0] data_in, waya yakabuda load_done, yakabuda waya [width_r-1:0] zvabuda, waya yekubuda_valid, input wire sclr, input wire [width_s-1:0] sel, input waya sload_coeff, kupinza waya sload_data)/* synthesis syn_black_box=1 */; endmodule
9.3. VHDL Chikamu Chiziviso
Iyo VHDL chikamu chiziviso chiri muVHDL Dhizaini File (.vhd) altera_mf_components.vhd in the librariesvhdlaltera_mf directory.
chikamu altmemmult generic (coeff_representation: tambo := "SIGNED"; coefficient0: string := "USUSED"; data_representation: tambo := "SIGNED"; chinangwa_chishandiso_mhuri: tambo := "isina kushandiswa"; max_clock_cycles_per_tural number:= := 1; ram_block_type:string := “AUTO”; total_latency:natural; width_c:natural; width_d:natural; width_r:natural; width_s:natural := 1; lpm_hint:string := "UNUSED"; lpm_type: tambo := "altmemmult"); port( wachi: in std_logic; coeff_in:in std_logic_vector(width_c-1 downto 1) := (vamwe => '0'); data_in:in std_logic_vector(width_d-0 downto 1);

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load_done:out std_logic; mhedzisiro: kunze std_logic_vector(width_r-1 downto 0); result_valid:out std_logic; sclr:in std_logic := '0'; sel:mu std_logic_vector(width_s-1 downto 0) := (vamwe => '0'); sload_coeff:in std_logic := '0'; sload_data:mu std_logic := '0'); end component;

9.4. Zviteshi

Aya matafura anotevera anonyora ekuisa uye kubuda madoko eiyo ALTMEMMULT IP musimboti.

Tafura 37. ALTMEMMULT Input Ports

Port Name

Zvinodiwa

Tsanangudzo

wachi

Ehe

Kupinza kwewachi kumupupuri.

coeff_in[]

Aihwa

Coefficient input port yekuwandisa. Saizi yenzvimbo yekupinza inotsamira pane WIDTH_C parameter kukosha.

data_in[]

Ehe

Data yekupinza port kune yawandisa. Saizi yenzvimbo yekupinza inotsamira pane WIDTH_D parameter kukosha.

sclr

Aihwa

Synchronous yakajeka kuisa. Kana isina kushandiswa, iyo yakasarudzika kukosha inoshanda yakakwira.

sel[]

Aihwa

Yakagadziriswa coefficient kusarudzwa. Saizi yenzvimbo yekupinza inotsamira paWIDTH_S

parameter value.

sload_coeff

Aihwa

Synchronous load coefficient input port. Inotsiva iyo ikozvino yakasarudzwa coefficient kukosha neukoshi hunotsanangurwa mune coeff_in yekuisa.

sload_data

Aihwa

Synchronous load data input port. Chiratidzo chinodonongodza kushanda kutsva kwekuwanza uye kukanzura chero kushanda kwekuwandisa kuriko. Kana iyo MAX_CLOCK_CYCLES_PER_RESULT parameter ine kukosha kwe1, sload_data yekuisa podhi inofuratirwa.

Tafura 38. ALTMEMMULT Output Ports

Port Name

Zvinodiwa

Tsanangudzo

mhedzisiro[]

Ehe

Multiplier output port. Saizi yenzvimbo yekupinza inotsamira pane WIDTH_R parameter kukosha.

result_valid

Ehe

Inotaridza kana chinobuda chiri mubairo unoshanda wekuwandisa kwakazara. Kana iyo MAX_CLOCK_CYCLES_PER_RESULT parameter ine kukosha kwe1, mhedzisiro_valid yekubuda pachiteshi haisi kushandiswa.

load_done

Aihwa

Inoratidza kana coefficient itsva yapedza kurodha. Iyo load_done signal inotaura kana coefficient itsva yapedza kurodha. Kunze kwekunge iyo load_done sign yakakwira, hapana imwe coefficient value inogona kutakurwa mundangariro.

9.5. Paramita

Tafura inotevera inonyora maparamendi eiyo ALTMEMMULT IP musimboti.

Tafura 39.
WIDTH_D WIDTH_C

ATMEMMULT Parameters
Parameter Zita

Type Inodiwa

Tsanangudzo

Integer Hongu

Inotsanangura hupamhi hwechiteshi che data_in[].

Integer Hongu

Inotsanangura hupamhi hwecoeff_in[] chiteshi. akaenderera…

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Intel FPGA Integer Arithmetic IP Cores Mushandisi Gwaro 59

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

Parameter Zita WIDTH_R WIDTH

Zvinyorwa / Zvishandiso

Intel FPGA Integer Arithmetic IP Cores [pdf] Bhuku reMushandisi
FPGA Integer Arithmetic IP Cores, Integer Arithmetic IP Cores, Arithmetic IP Cores, IP Cores

References

User Manual

FPGA Integer Arithmetic IP Cores

Zvinyorwa / Zvishandiso

References

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Kanzura mhinduro