F Tile Serial Lite IV Intel FPGA IP User Guide

Zamkatimu kubisa

1 F Tile seri Lite IV Intel FPGA IP

2 Zolemba / Zothandizira

2.1 Maumboni

3 Zolemba Zogwirizana

F Tile seri Lite IV Intel FPGA IP

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F-Tile Serial Lite IV Intel® FPGA IP User Guide
Zasinthidwa ku Intel® Quartus® Prime Design Suite: 22.1 IP Version: 5.0.0

Paintaneti Tumizani Ndemanga

UG-20324

ID: 683074 Mtundu: 2022.04.28

Zamkatimu
Zamkatimu
1. Za F-Tile Serial Lite IV Intel® FPGA IP User Guide……………………………………….. 4
2. F-Tile seri Lite IV Intel FPGA IP Overview…………………………………………………………………. 6 2.1. Zotulutsidwa……………………………………………………………………………………..7 2.2. Zothandizira……………………………………………………………………………………….. 7 2.3. IP Version Support Level……………………………………………………………………………..8 2.4. Device Speed Grade Support…………………………………………………………………………..8 2.5. Kugwiritsa Ntchito Zida ndi Kuchedwa…………………………………………………………………………… Bandwidth Efficiency…………………………………………………………………………………………. 9
3. Chiyambi……………………………………………………………………………………………………. 11 3.1. Kuyika ndi Kupereka Ziphatso za Intel FPGA IP Cores………………………………………………………… 11 3.1.1. Intel FPGA IP Evaluation Mode………………………………………………………………. 11 3.2. Kufotokoza za IP Parameters ndi Zosankha……………………………………………………………… Zapangidwa File Kapangidwe……………………………………………………………………………………… 14 3.4. Simulating Intel FPGA IP Cores……………………………………………………………………………… 16 3.4.1. Kuyerekeza ndi Kutsimikizira Mapangidwe…………………………………………………….. 17 3.5. Kuphatikizira IP Cores mu Zida Zina za EDA…………………………………………………………. 17 3.6. Kupanga Mapangidwe Athunthu……………………………………………………………………………..18
4. Kufotokozera Kachitidwe……………………………………………………………………………………….. 19 4.1. TX Datapath………………………………………………………………………………………..20 4.1.1. Adapter ya TX MAC…………………………………………………………………………….. 21 4.1.2. Kulowetsa kwa Mawu a Control (CW) ……………………………………………………………………………… TX CRC……………………………………………………………………………………………23 4.1.3. TX MII Encoder……………………………………………………………………………….28 4.1.4. TX PCS ndi PMA………………………………………………………………………….. 29 4.1.5. RX Datapath…………………………………………………………………………………………. 30 4.2. RX PCS ndi PMA…………………………………………………………………………….. 30 4.2.1. RX MII Decoder…………………………………………………………………………………… 31 4.2.2. RX CRC……………………………………………………………………………………….. 31 4.2.3. RX Deskew………………………………………………………………………………….31 4.2.4. Kuchotsa kwa RX CW…………………………………………………………………………………32 4.2.5. F-Tile seri Lite IV Intel FPGA IP Clock Architecture……………………………………………. 35 4.3. Reset and Link Initialization…………………………………………………………………………..36 4.4. TX Kukhazikitsanso ndi Kuyambitsa Njira………………………………………………………. 37 4.4.1. RX Reset and Initialization Sequence………………………………………………………. 38 4.4.2. Kuwerengetsera kwa Link Rate ndi Bandwidth Efficiency ……………………………………………….. 39
5. Parameters…………………………………………………………………………………………………………. 42
6. F-Tile Serial Lite IV Intel FPGA IP Interface Signals…………………………………………….. 44 6.1. Zizindikiro za Wotchi………………………………………………………………………………………….44 6.2. Bwezeretsani Zizindikiro………………………………………………………………………………………………………… Zizindikiro za MAC………………………………………………………………………………………….. 44 6.3. Ma Transceiver Reconfiguration Signals……………………………………………………………………… 45 6.4. Zizindikiro za PMA………………………………………………………………………………………….. 48

F-Tile Serial Lite IV Intel® FPGA IP User Guide 2

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Zamkatimu
7. Kupanga ndi F-Tile Serial Lite IV Intel FPGA IP…………………………………………………… 51 7.1. Bwezerani Malangizo……………………………………………………………………………………….. 51 7.2. Malangizo Oyendetsera Zolakwa……………………………………………………………………………..51
8. F-Tile seri Lite IV Intel FPGA IP User Guide Archives ……………………………………………. 52 9. Document Revision History for the F-Tile Serial Lite IV Intel FPGA IP User Guide ………53

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F-Tile Serial Lite IV Intel® FPGA IP User Guide 3

683074 | 2022.04.28 Tumizani Ndemanga

1. Za F-Tile Serial Lite IV Intel® FPGA IP User Guide

Chikalatachi chikufotokoza za IP, mafotokozedwe a zomangamanga, njira zopangira, ndi malangizo opangira F-Tile Serial Lite IV Intel® FPGA IP pogwiritsa ntchito ma transceivers a F-tile mu zipangizo za Intel Agilex TM.

Omvera Ofuna

Chikalatachi ndi cha anthu otsatirawa:
· Opanga mapulani kuti apange chisankho cha IP panthawi yokonzekera mapangidwe adongosolo
· Opanga zida zopangira zida akaphatikiza IP pamapangidwe awo adongosolo
· Mainjiniya otsimikizira panthawi yofananira ndi magawo otsimikizira ma hardware

Zolemba Zogwirizana

Gome lotsatirali likulemba zolemba zina zomwe zikugwirizana ndi F-Tile Serial Lite IV Intel FPGA IP.

Table 1.

Zolemba Zogwirizana

Buku

F-Tile seri Lite IV Intel FPGA IP Design Exampndi User Guide

Intel Agilex Device Data Sheet

Kufotokozera
Chikalatachi chimapereka m'badwo, malangizo ogwiritsira ntchito, komanso kufotokozera kwa F-Tile Serial Lite IV Intel FPGA IP design ex.ampLero mu zida za Intel Agilex.
Chikalatachi chikufotokozera mawonekedwe amagetsi, mawonekedwe osinthira, mafotokozedwe a kasinthidwe, ndi nthawi ya zida za Intel Agilex.

Table 2.
CW RS-FEC PMA TX RX PAM4 NRZ

Acronyms ndi Glossary Acronym List
Mwachidule

Kukula Kuwongolera Mawu Reed-Solomon Forward Error Correction Physical Medium Attachment Transmitter Receiver Pulse-Amplitude Modulation 4-Level Kusabwerera-to-zero

anapitiriza…

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa cha kugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito. *Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.

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1. Za F-Tile Serial Lite IV Intel® FPGA IP User Guide 683074 | 2022.04.28

PCS MII XGMII

Mwachidule

Kukula kwa Thupi Coding Sublayer Media Independent Interface 10 Gigabit Media Independent Interface

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2. F-Tile seri Lite IV Intel FPGA IP Overview

Chithunzi 1.

F-Tile seri Lite IV Intel FPGA IP ndiyoyenera kulumikizana ndi data ya bandwidth yayikulu pa chip-to-chip, board-to-board, ndi ma backplane application.

F-Tile Serial Lite IV Intel FPGA IP imaphatikizira zowongolera zofikira pa media (MAC), zotchingira zakuthupi (PCS), ndi midadada yapa media media (PMA). IP imathandizira kuthamanga kwa data mpaka 56 Gbps pamseu uliwonse wokhala ndi misewu inayi ya PAM4 kapena 28 Gbps panjira yokhala ndi misewu yayikulu ya 16 NRZ. IP iyi imapereka ma bandwidth apamwamba, mafelemu otsika pamwamba, kuwerengera kwa I/O, ndipo imathandizira kuchulukira kwakukulu mumayendedwe onse ndi liwiro. IP iyi imasinthidwanso mosavuta mothandizidwa ndi mitundu yambiri yamitengo ya data ndi Ethernet PCS mode ya F-tile transceiver.

IP iyi imathandizira njira ziwiri zotumizira:
· Basic mode-Iyi ndi njira yosakira pomwe deta imatumizidwa popanda paketi yoyambira, kuzungulira kopanda kanthu, komanso kumapeto kwa paketi kuti muwonjezere bandwidth. IP imatenga deta yoyamba yovomerezeka ngati chiyambi cha kuphulika.
· Full mode-Izi ndi paketi kusamutsa mode. Munjira iyi, IP imatumiza kuphulika ndi kulunzanitsa kozungulira koyambira ndi kumapeto kwa paketi ngati delimiters.

Chithunzi cha F-Tile seri Lite IV High Level Block block

Avalon Streaming Interface TX

F-Tile seri Lite IV Intel FPGA IP
MAC TX
TX USRIF_CTRL

64 * n misewu yaying'ono (NRZ mode) / 2 * n misewu bits (PAM4 mode)

TX MAC

Adapter INSERT

MII ENCODE

Ma PC Okhazikika

TX PCS

TX MII

EMIB ENCODE SCRAMBLER FEC

TX PMA

n Lanes Bits (PAM4 mode)/ n Lanes Bits (NRZ mode)
TX Serial Interface

Avalon Streaming Interface RX
64 * n misewu yaying'ono (NRZ mode) / 2 * n misewu bits (PAM4 mode)

RX PCS

CW RMV

DESKEW

MII

& ALIGN DECODE

RX MII

EMIB

DECODE BLOCK SYNC & FEC DESCRAMBLER

Mtengo RX PMA

Mtengo CSR

2n Lanes Bits (PAM4 mode)/ n Lanes Bits (NRZ mode) RX Serial Interface
Avalon Memory-Mapped Interface Register Config

Nthano

Mfundo zofewa

Mfundo zolimba

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2. F-Tile seri Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Mutha kupanga F-Tile seri Lite IV Intel FPGA IP kapangidwe examples kuti mudziwe zambiri za IP. Onani F-Tile seri Lite IV Intel FPGA IP Design Exampndi User Guide.
Zambiri Zofananira · Kufotokozera Kwamagwiritsidwe patsamba 19 · F-Tile Serial Lite IV Intel FPGA IP Design Exampndi User Guide

2.1. Zambiri Zotulutsidwa

Mitundu ya Intel FPGA IP imafanana ndi mitundu ya Intel Quartus® Prime Design Suite mpaka v19.1. Kuyambira mu Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP ili ndi ndondomeko yatsopano yomasulira.

Nambala ya Intel FPGA IP (XYZ) imatha kusintha ndi mtundu uliwonse wa pulogalamu ya Intel Quartus Prime. Kusintha kwa:

X ikuwonetsa kukonzanso kwakukulu kwa IP. Mukasintha pulogalamu ya Intel Quartus Prime, muyenera kukonzanso IP.
· Y akuwonetsa kuti IP ili ndi zatsopano. Panganinso IP yanu kuti muphatikizepo zatsopanozi.
Z ikuwonetsa kuti IP ili ndi zosintha zazing'ono. Panganinso IP yanu kuti ikhale ndi zosinthazi.

Table 3.

F-Tile Serial Lite IV Intel FPGA IP Release Information

Nambala ya IP ya Intel Quartus Prime Version Yotulutsa Date Code Code

5.0.0 22.1 2022.04.28 IP-SLITE4F

Kufotokozera

2.2. Zothandizira
Gome lotsatirali likuwonetsa zomwe zikupezeka mu F-Tile Serial Lite IV Intel FPGA IP:

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Table 4.

F-Tile seri Lite IV Intel FPGA IP Features

Mbali

Kufotokozera

Kusamutsa Data

Pa PAM4 mode:
- FHT imathandizira 56.1, 58, ndi 116 Gbps panjira yokhala ndi misewu yayikulu ya 4.
- FGT imathandizira mpaka 58 Gbps pamseu uliwonse wokhala ndi mikwingwirima 12.
Onani Table 18 patsamba 42 kuti mumve zambiri pamitengo ya data ya transceiver yothandizidwa ya PAM4 mode.
· Kwa mawonekedwe a NRZ:
- FHT imathandizira 28.05 ndi 58 Gbps panjira iliyonse yokhala ndi misewu yambiri ya 4.
- FGT ikuthandizira mpaka 28.05 Gbps pamseu uliwonse wokhala ndi misewu yopitilira 16.
Onani Table 18 patsamba 42 kuti mumve zambiri za mitengo ya data ya transceiver yothandizidwa pamtundu wa NRZ.
· Imathandizira kukhamukira kosalekeza (Basic) kapena paketi (Yathunthu) mitundu.
· Imathandizira mapaketi azithunzi otsika.
· Imathandizira kusamutsa kwa byte granularity pakukula kulikonse.
· Imathandizira kulumikizana ndi ogwiritsa ntchito kapena kungolumikizana.
· Imathandizira nthawi yokhazikika yokhazikika.

PCS

· Imagwiritsa ntchito malingaliro olimba a IP omwe amalumikizana ndi ma transceivers a Intel Agilex F-tile kuti achepetse zida zofewa.
· Imathandizira PAM4 modulation mode pamayendedwe a 100GBASE-KP4. RS-FEC imayatsidwa nthawi zonse mumayendedwe awa.
· Imathandizira NRZ ndi njira yosinthira ya RS-FEC.
· Imathandizira 64b/66b encoding decoding.

Kuzindikira Kolakwika ndi Kusamalira

· Imathandizira kuwunika kwa zolakwika za CRC panjira za data za TX ndi RX. · Imathandizira kuyang'ana zolakwika za ulalo wa RX. · Imathandizira kuzindikira zolakwika za RX PCS.

Zolumikizirana

· Imathandizira kusamutsidwa kwathunthu kwa paketi ya duplex yokhala ndi maulalo odziyimira pawokha.
· Imagwiritsa ntchito kulumikizana kwa point-to-point ku zida zingapo za FPGA zokhala ndi latency yotsika.
· Imathandizira malamulo ofotokozedwa ndi ogwiritsa ntchito.

2.3. IP Version Support Level

Pulogalamu ya Intel Quartus Prime ndi Intel FPGA yothandizira chipangizo cha F-Tile Serial Lite IV Intel FPGA IP ndi motere:

Table 5.

Mtundu wa IP ndi Mulingo Wothandizira

Intel Quartus Prime 22.1

Chipangizo ma transceivers a Intel Agilex F-tile

IP Version Simulation Compilation Hardware Design

5.0.0

2.4. Chipangizo Speed Grade Thandizo
F-Tile Serial Lite IV Intel FPGA IP imathandizira magiredi othamanga awa a Intel Agilex F-tile zida: · Transceiver liwiro giredi: -1, -2, ndi -3 · Core speed grade: -1, -2, ndi - 3

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Zambiri Zogwirizana
Intel Agilex Device Data Sheet Zambiri zokhudzana ndi kuchuluka kwa data zomwe zimathandizidwa mu Intel Agilex F-tile transceivers.

2.5. Kugwiritsa Ntchito Zida ndi Kuchedwa

Zida ndi kuchedwa kwa F-Tile Serial Lite IV Intel FPGA IP zidapezedwa kuchokera ku Intel Quartus Prime Pro Edition software version 22.1.

Table 6.

Intel Agilex F-Tile seri Lite IV Intel FPGA IP Resource Utilization
Muyeso wa latency umachokera paulendo wozungulira latency kuchokera ku TX core input mpaka RX core output.

Mtundu wa Transceiver

Zosiyana

Nambala ya Njira Yamayendedwe a Data RS-FEC ALM

Latency (TX core clock cycle)

Mtengo wa FGT

28.05 Gbps NRZ 16

Olemala Oyambira 21,691 65

Olumala kwathunthu 22,135 65

Zoyambira Zathandizira 21,915 189

Zathunthu 22,452 189

58 Gbps PAM4 12

Zoyambira Zathandizira 28,206 146

Zathunthu 30,360 146

Mtengo wa FHT

58 Gbps NRZ

Zoyambira Zathandizira 15,793 146

Zathunthu 16,624 146

58 Gbps PAM4 4

Zoyambira Zathandizira 15,771 154

Zathunthu 16,611 154

116 Gbps PAM4 4

Zoyambira Zathandizira 21,605 128

Zathunthu 23,148 128

2.6. Bandwidth Mwachangu

Table 7.

Bandwidth Mwachangu

Zosintha za Transceiver mode

PAM4

Kukhamukira mode RS-FEC

Zonse Zayatsidwa

Basic Yathandizidwa

Seri interface bit rate mu Gbps (RAW_RATE)
Kuphulika kwa kukula kwa kusintha kwa mawu (BURST_SIZE) (1)
Nthawi yoyankhulirana ndi wotchi (SRL4_ALIGN_PERIOD)

56.0 2,048 4,096

56.0 4,194,304 4,096

Zokonda

Mtengo wa NRZ

Zodzaza

Wolumala

Yayatsidwa

28.0

2,048

4,096

Basic Disabled 28.0

Yathandizira 28.0

4,194,304

4,096

4,096 adapitilira…

(1) BURST_SIZE for Basic mode imayandikira mopanda malire, chifukwa chake kuchuluka kumagwiritsidwa ntchito.

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Zosintha

Zokonda

64/66b kodi

0.96969697 0.96969697 0.96969697 0.96969697 0.96969697 0.96969697

Pamwamba pa kukula kwa mawu ambiri (BURST_SIZE_OVHD)

2 (2)

0 (3)

2 (2)

0 (3)

Nthawi yoyatsira chikhomo 81,915 mumayendedwe a wotchi (ALIGN_MARKER_PERIOD)

81,915

81,916

Kuyanjanitsa chikhomo mu 5

wotchi yozungulira

(ALIGN_MARKER_WIDTH)

Bandwidth bwino (4)

0.96821788 0.96916433 0.96827698 0.96822967 0.96922348 0.96917616

Mtengo wabwino (Gbps) (5)

54.2202012 54.27320236 27.11175544 27.11043076 27.13825744 27.13693248

Kuchuluka kwa wotchi (MHz) (6)

423.59532225 424.00939437 423.62117875 423.6004806 424.0352725 424.01457

Zambiri Zogwirizana ndi Mulingo wa Ulalo ndi Bandwidth Mwachangu Kuwerengera patsamba 40

(2) Mumode yonse, kukula kwa BURST_SIZE_OVHD kumaphatikizapo START/END Mau owongolera omwe ali pawiri mumkokomo wa data.
(3) Pamawonekedwe Oyamba, BURST_SIZE_OVHD ndi 0 chifukwa palibe START/END panthawi yotsegulira.
(4) Onani Kuwerengera Kwa Ulalo ndi Bandwidth Kuwerengera Mwachangu kwa bandwidth yowerengera.
(5) Onani Kuwerengetsera kwa Link Rate ndi Bandwidth Efficiency kuti muwerengere bwino mtengo.
6

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3. Chiyambi

3.1. Kukhazikitsa ndi Kupereka Chilolezo cha Intel FPGA IP Cores

Kukhazikitsa kwa Intel Quartus Prime software kumaphatikizapo laibulale ya Intel FPGA IP. Laibulale iyi imapereka ma cores ambiri a IP kuti mugwiritse ntchito popanga popanda kufunikira kwa chilolezo chowonjezera. Zina za Intel FPGA IP cores zimafuna kugula laisensi yosiyana kuti igwiritsidwe ntchito popanga. Intel FPGA IP Evaluation Mode imakupatsani mwayi kuti muwunikire ma Intel FPGA IP omwe ali ndi zilolezo poyerekezera ndi zida, musanaganize zogula laisensi yayikulu ya IP. Mukungofunika kugula chiphaso chathunthu cha ma Intel IP cores omwe ali ndi chilolezo mukamaliza kuyesa kwa hardware ndipo mwakonzeka kugwiritsa ntchito IP popanga.

Pulogalamu ya Intel Quartus Prime imayika ma cores a IP m'malo otsatirawa mwachisawawa:

Chithunzi 2.

IP Core Installation Njira
intelFPGA(_pro) quartus - Muli Intel Quartus Prime software ip - Muli Intel FPGA IP laibulale ndi wachitatu IP cores altera - Muli Intel FPGA IP laibulale code code - Muli gwero la IP la Intel FPGA files

Table 8.

Malo oyika IP Core

Malo

Mapulogalamu

:intelFPGA_proquartusipaltera

Intel Quartus Prime Pro Edition

:/intelFPGA_pro/quartus/ip/altera Intel Quartus Prime Pro Edition

Platform Windows* Linux*

Zindikirani:

Pulogalamu ya Intel Quartus Prime sichithandizira mipata munjira yoyika.

3.1.1. Intel FPGA IP Evaluation Mode
Njira yaulere ya Intel FPGA IP Evaluation Mode imakupatsani mwayi woyesa ma Cores a Intel FPGA IP omwe ali ndi chilolezo poyerekezera ndi hardware musanagule. Intel FPGA IP Evaluation Mode imathandizira kuwunika kotsatiraku popanda chilolezo chowonjezera:
+ Tsanzirani zomwe zili ndi chilolezo cha Intel FPGA IP pakompyuta yanu. * Tsimikizirani magwiridwe antchito, kukula, komanso kuthamanga kwa IP core mwachangu komanso mosavuta. · Pangani mapulogalamu anthawi yochepa files pamapangidwe omwe ali ndi ma IP cores. + Konzani chipangizo chokhala ndi IP core yanu ndikutsimikizira kapangidwe kanu mu hardware.

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3. Chiyambi
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Intel FPGA IP Evaluation Mode imathandizira njira zotsatirazi:
· Tethered-Imalola kuyendetsa mapangidwe omwe ali ndi chilolezo cha Intel FPGA IP kwamuyaya ndi kulumikizana pakati pa bolodi lanu ndi kompyuta yanu. Njira yolumikizira imafuna gulu loyeserera loyeserera (JTAG) chingwe cholumikizidwa pakati pa JTAG doko pa bolodi lanu ndi kompyuta yolandirayo, yomwe ikuyendetsa Intel Quartus Prime Programmer kwa nthawi yonse yowunikira zida. Pulogalamuyi imangofunika kukhazikitsa pulogalamu ya Intel Quartus Prime, ndipo safuna chilolezo cha Intel Quartus Prime. Kompyutayi imayendetsa nthawi yowunika potumiza chizindikiro cha nthawi ndi nthawi ku chipangizocho kudzera pa JTAG doko. Ngati ma cores onse a IP omwe ali ndi zilolezo pamapangidwe amathandizira, nthawi yowunikira imatha mpaka kuwunika kulikonse kwa IP kutha. Ngati ma cores onse a IP amathandizira nthawi yowunika mopanda malire, chipangizocho sichimatha.
· Untethered-Amalola kuyendetsa mapangidwe omwe ali ndi IP yovomerezeka kwakanthawi kochepa. IP core imabwerera kumayendedwe osatsekeredwa ngati chipangizocho chitha kulumikizidwa ndi kompyuta yomwe ikuyendetsa pulogalamu ya Intel Quartus Prime. IP core imabwereranso kumayendedwe osalumikizidwa ngati china chilichonse chovomerezeka cha IP pamapangidwe sichigwirizana ndi njira yolumikizira.
Nthawi yowunikira ikatha kwa Intel FPGA IP yomwe ili ndi chilolezo pamapangidwe, mapangidwewo amasiya kugwira ntchito. Ma IP cores onse omwe amagwiritsa ntchito Intel FPGA IP Evaluation Mode amathera nthawi imodzi pomwe IP core pakupanga nthawi yatha. Nthawi yowunikira ikatha, muyenera kukonzanso chipangizo cha FPGA musanapitirize kutsimikizira za hardware. Kuti muwonjezere kugwiritsa ntchito IP pachimake pakupanga, gulani chiphaso chokwanira cha IP core.
Muyenera kugula laisensi ndikupanga kiyi yalayisensi yopangira zonse musanapange pulogalamu yopanda malire file. Panthawi ya Intel FPGA IP Evaluation Mode, Compiler imangopanga pulogalamu yokhala ndi nthawi yochepa file ( _time_limited.sof) yomwe imatha nthawi yake.

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Chithunzi 3.

Intel FPGA IP Evaluation Mode Flow
Ikani Intel Quartus Prime Software ndi Intel FPGA IP Library

Parameterize ndikukhazikitsa Chilolezo cha Intel FPGA IP Core

Tsimikizirani IP mu Simulator Yothandizidwa

Lembani Mapangidwewo mu Intel Quartus Prime Software

Pangani Pulogalamu Yazida Zanthawi Yochepa File

Konzani Chipangizo cha Intel FPGA ndikutsimikizira Ntchito pa Board
Palibe IP Yokonzeka Kugwiritsa Ntchito?
Inde Gulani Kupanga Kwathunthu
IP License

Zindikirani:

Phatikizani IP Yovomerezeka mu Zogulitsa Zamalonda
Onani chiwongolero cha ogwiritsa ntchito pa IP iliyonse kuti mupeze magawo ndi tsatanetsatane wa momwe mungagwiritsire ntchito.
Intel imalola ma IP cores pampando uliwonse, nthawi zonse. Malipiro a layisensi amaphatikizapo kukonza ndi chithandizo chaka choyamba. Muyenera kukonzanso mgwirizano wokonza kuti mulandire zosintha, kukonza zolakwika, ndi chithandizo chaukadaulo kupitilira chaka choyamba. Muyenera kugula chiphaso chokwanira cha Intel FPGA IP cores chomwe chimafuna chilolezo chopanga, musanapange mapulogalamu files kuti mutha kugwiritsa ntchito nthawi yopanda malire. Panthawi ya Intel FPGA IP Evaluation Mode, Compiler imangopanga pulogalamu yokhala ndi nthawi yochepa file ( _time_limited.sof) yomwe imatha nthawi yake. Kuti mupeze makiyi anu alayisensi opanga, pitani ku Intel FPGA Self-Service Licensing Center.
Migwirizano ya License ya Intel FPGA imayendetsa kuyika ndi kugwiritsa ntchito ma IP cores omwe ali ndi zilolezo, pulogalamu ya Intel Quartus Prime design, ndi ma IP cores onse opanda chilolezo.

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Zowonjezera Zina · Intel FPGA Licensing Support Center · Mau oyamba a Intel FPGA Software Installation and Licensing
3.2. Kufotokozera za IP Parameters ndi Zosankha
IP parameter editor imakupatsani mwayi wosintha kusintha kwanu kwa IP. Gwiritsani ntchito njira zotsatirazi kuti mutchule zosankha za IP ndi magawo mu pulogalamu ya Intel Quartus Prime Pro Edition.
1. Ngati mulibe kale pulojekiti ya Intel Quartus Prime Pro Edition yomwe mungaphatikizepo F-Tile Serial Lite IV Intel FPGA IP yanu, muyenera kupanga imodzi. a. Mu Intel Quartus Prime Pro Edition, dinani File New Project Wizard kuti apange pulojekiti yatsopano ya Quartus Prime, kapena File Open Project kuti mutsegule pulojekiti yomwe ilipo ya Quartus Prime. Wizard imakulimbikitsani kuti mutchule chipangizo. b. Tchulani chipangizo cha banja la Intel Agilex ndikusankha chipangizo cha F-tile chomwe chimakwaniritsa zofunikira za grade grade pa IP. c. Dinani Malizani.
2. Mu Gulu la IP, pezani ndikusankha F-Tile seri Lite IV Intel FPGA IP. Zenera la New IP Variation likuwonekera.
3. Tchulani dzina lapamwamba la IP yanu yatsopano. Mkonzi wa parameter amasunga zosintha za IP mu a file dzina .ip.
4. Dinani Chabwino. The parameter editor ikuwonekera. 5. Tchulani magawo a IP yanu. Onani gawo la Parameter
Zambiri za F-Tile seri Lite IV Intel FPGA IP magawo. 6. Optionally, kupanga kayeseleledwe testbench kapena compilation ndi hardware kapangidwe
example, tsatirani malangizo omwe ali mu Design Exampndi User Guide. 7. Dinani Pangani HDL. The Generation dialog box ikuwonekera. 8. Tchulani zotsatira file kupanga zosankha, ndiyeno dinani Pangani. Kusintha kwa IP
files kupanga molingana ndi zomwe mukufuna. 9. Dinani kumaliza. Mkonzi wa parameter amawonjezera pamwamba .ip file ku panopa
polojekiti basi. Ngati mwapemphedwa kuti muwonjezere pamanja .ip file ku polojekitiyo, dinani Project Add/Chotsani Files mu Project kuwonjezera ma file. 10. Mutatha kupanga ndi kuyambitsa kusintha kwanu kwa IP, pangani ma pini oyenerera kuti mulumikize madoko ndikukhazikitsa magawo oyenera a RTL pazochitika zilizonse.
Zambiri Zofananira patsamba 42
3.3. Zapangidwa File Kapangidwe
Pulogalamu ya Intel Quartus Prime Pro Edition imapanga zotsatirazi za IP file kapangidwe.
Kuti mudziwe zambiri za file kapangidwe ka kapangidwe example, tchulani F-Tile Serial Lite IV Intel FPGA IP Design Exampndi User Guide.

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Chithunzi 4. F-Tile Serial Lite IV Intel FPGA IP Yopangidwa Files
.ip - Kuphatikiza kwa IP file

Kusintha kwa IP files

_ Kusintha kwa IP files

example_design

.cmp - Chidziwitso cha gawo la VHDL file _bb.v - Verilog HDL yakuda bokosi EDA kaphatikizidwe file _inst.v ndi .vhd – Sampndi ma instantiation templates .xml- lipoti la XML file

Exampndi malo a IP core design example files. Malo osakhazikika ndi akaleample_design, koma mumalimbikitsidwa kufotokoza njira ina.

.qgsimc - Imalemba magawo oyerekeza kuti athandizire kusinthika kowonjezereka .qgsynthc - Imalemba magawo a kaphatikizidwe kuti athandizire kusinthika kowonjezereka

.qip - Mndandanda wa IP synthesis files

Lipoti la _generation.rpt- IP

.sopcinfo- Kuphatikizika kwa zida zamapulogalamu file .html- Data yolumikizira ndi kukumbukira mapu

.csv - Pin ntchito file

.spd - Zimaphatikiza zolemba zofananira

sim Kuyerekeza files

synth IP synthesis files

.v Kuyerekeza kwapamwamba file

.v Kaphatikizidwe kapamwamba ka IP file

Zolemba za simulator

Ma library a subcore

synth
Subcore synthesis files

sim
Subcore Simulation files

Table 9.

F-Tile seri Lite IV Intel FPGA IP Yopangidwa Files

File Dzina

Kufotokozera

.ip

Dongosolo la Platform Designer kapena kusiyanasiyana kwapamwamba kwa IP file. ndi dzina lomwe mumapereka kusintha kwa IP yanu.

.cmp

The VHDL Component Declaration (.cmp) file ndi malemba file yomwe ili ndi matanthauzidwe am'deralo ndi madoko omwe mungagwiritse ntchito popanga VHDL files.

html

Lipoti lomwe lili ndi chidziwitso cholumikizira, mapu okumbukira omwe akuwonetsa adilesi ya kapolo aliyense polemekeza mbuye aliyense komwe amalumikizidwa, ndi magawo omwe amaperekedwa.

_generation.rpt

Pulogalamu ya IP kapena Platform Designer file. Chidule cha mauthenga pa nthawi ya IP.

.qgsimc

Imatchula magawo oyerekeza kuti athandizire kusinthika kowonjezereka.

.qgsynthc

Imatchula magawo a kaphatikizidwe kuti athandizire kusinthika kowonjezereka.

.qip

Lili ndi zonse zofunika za gawo la IP kuti muphatikize ndikuphatikiza gawo la IP mu pulogalamu ya Intel Quartus Prime.
anapitiriza…

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File Dzina .sopcinfo
.csv .spd _bb.v _inst.v kapena _inst.vhd .regmap
.svd
.v kapena .vhd mentor/ synopsy/vcs/ synopsy/vcsmx/ xcelium/ submodules/ /

Kufotokozera
Imafotokoza zolumikizirana ndi magawo a IP mu dongosolo lanu la Platform Designer. Mutha kusanthula zomwe zili mkati mwake kuti mupeze zofunika mukapanga ma driver a mapulogalamu a zigawo za IP. Zida zotsika monga chida cha Nios® II zimagwiritsa ntchito izi file. The .sopcinfo file ndi dongosolo.h file zopangira zida za Nios II zimaphatikizapo zambiri zamaadiresi za kapolo aliyense wachibale kwa mbuye aliyense yemwe amapeza kapolo. Mabwana osiyanasiyana amatha kukhala ndi mapu aadiresi osiyanasiyana kuti athe kupeza gawo linalake la akapolo.
Lili ndi zambiri zakukweza kwa gawo la IP.
Zofunikira file kwa ip-make-simscript kuti apange zolemba zofananira za oyeserera othandizira. The .spd file lili ndi mndandanda wa files amapangidwa kuti ayesedwe, komanso zambiri zamakumbukiro zomwe mutha kuyambitsa.
Mutha kugwiritsa ntchito Verilog black-box (_bb.v) file monga chilengezo chopanda kanthu cha module kuti chigwiritsidwe ntchito ngati bokosi lakuda.
Zithunzi za HDLampndi instantiation template. Mutha kukopera ndi kumata zomwe zili mu izi file mu HDL yanu file yambitsani kusintha kwa IP.
Ngati IP ili ndi zambiri zolembetsa, .regmap file amapanga. The .regmap file limafotokoza zambiri zamapu olembetsa a masters ndi akapolo interfaces. Izi file limakwaniritsa .sopcinfo file popereka zambiri mwatsatanetsatane za kaundula za dongosolo. Izi zimathandizira kuwonetsa mawonekedwe views ndi ziwerengero zomwe mungagwiritse ntchito mu System Console.
Imalola zida za hard processor system (HPS) System Debug kuti view mamapu olembetsa a zotumphukira zolumikizidwa ndi HPS mu dongosolo la Platform Designer. Panthawi ya kaphatikizidwe, .svd files za mawonekedwe a akapolo owonekera kwa System Console masters amasungidwa mu .sof file mu gawo la debug. System Console imawerenga gawoli, lomwe Platform Designer angafunse kuti mudziwe zambiri zamapu. Kwa akapolo a dongosolo, Platform Designer atha kupeza zolembera ndi mayina.
HDL files omwe amakhazikitsa submodule iliyonse kapena IP ya mwana kuti ipangidwe kapena kuyerekezera.
Muli ModelSim*/QuestaSim* script msim_setup.tcl kuti mukhazikitse ndikuyendetsa kayeseleledwe.
Muli ndi chipolopolo vcs_setup.sh kuti mukhazikitse ndikuyendetsa kayesedwe ka VCS*. Muli ndi chipolopolo vcsmx_setup.sh ndi synopsy_sim.setup file kukhazikitsa ndi kuyendetsa kayeseleledwe ka VCS MX.
Muli ndi chipolopolo xcelium_setup.sh ndi khwekhwe lina files kukhazikitsa ndikuyendetsa kayeseleledwe ka Xcelium*.
Muli HDL files kwa ma submodule a IP.
Pa chikwatu chilichonse chopangidwa ndi ana a IP, Platform Designer amapanga masinthidwe a synth/ ndi sim/ sub-directories.

3.4. Kutengera Intel FPGA IP Cores
Pulogalamu ya Intel Quartus Prime imathandizira kuyerekezera kwa IP core RTL muzinthu zina za EDA. Kupanga kwa IP kumapanga zoyerekeza files, kuphatikiza mawonekedwe oyeserera, testbench iliyonse (kapena example design), ndi zolembera zofananira ndi ogulitsa zamtundu uliwonse wa IP. Mukhoza kugwiritsa ntchito kayeseleledwe kachitsanzo ndi testbench iliyonse kapena wakaleampkamangidwe ka kayeseleledwe. Kutulutsa kwa IP kungaphatikizeponso zolemba kuti mupange ndikuyendetsa testbench iliyonse. Zolemba zimalemba mitundu yonse kapena malaibulale omwe mukufuna kuti muyese IP core yanu.

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Pulogalamu ya Intel Quartus Prime imapereka kuphatikiza ndi zoyeserera zambiri ndipo imathandizira kuyenda koyerekeza kangapo, kuphatikiza mayendedwe anu olembedwa komanso oyeserera. Mulimonse momwe mungayendere, kuyezetsa koyambira kwa IP kumaphatikizapo izi:
1. Pangani IP HDL, testbench (kapena example design), ndi script yokhazikitsira simulator files.
2. Konzani malo oyeserera anu ndi zolemba zilizonse zoyeserera.
3. Sungani malaibulale achitsanzo.
4. Yendetsani simulator yanu.

3.4.1. Kuyesa ndi Kutsimikizira Mapangidwe

Mwachikhazikitso, mkonzi wa parameter amapanga zolemba za simulator zokhala ndi malamulo oti asonkhanitse, kulongosola, ndi kutsanzira mitundu ya Intel FPGA IP ndi laibulale yachitsanzo. files. Mutha kukopera malamulowa muzolemba zanu zoyeserera za testbench, kapena kusintha izi files kuti muwonjezere malamulo ophatikizira, kufotokozera, ndikufanizira kapangidwe kanu ndi testbench.

Table 10. Intel FPGA IP Core Simulation Scripts

Woyeserera

File Directory

ModelSim

_sim/mentor

KochiLaka

Zithunzi za VCS

_sim/synopsy/vcs

Chithunzi cha VCS MX

_sim/synopsy/vcsmx

Xcelium

_sim/xcelium

Script msim_setup.tcl (7)
vcs_setup.sh vcsmx_setup.sh synopsy_sim.setup xcelium_setup.sh

3.5. Kuphatikizira IP Cores mu Zida Zina za EDA
Mwachidziwitso, gwiritsani ntchito chida china chothandizira cha EDA kuti mupange mapangidwe omwe amaphatikizapo Intel FPGA IP cores. Mukapanga IP core synthesis files kuti mugwiritse ntchito ndi zida za kaphatikizidwe za EDA za chipani chachitatu, mutha kupanga malo ndi mndandanda wanthawi yoyerekeza. Kuti muthe kupanga, yatsani Kupanga nthawi ndi kuyerekezera kwazinthu za zida zophatikizira za EDA za gulu lina mukamasintha ma IP anu.
Dera ndi kuyerekezera nthawi net limafotokoza kulumikizidwa kwa IP ndi kamangidwe kake, koma sikuphatikiza tsatanetsatane wa magwiridwe antchito enieni. Chidziwitsochi chimathandizira zida zina zophatikizira gulu lachitatu kuti lifotokoze bwino malo ndi kuyerekezera nthawi. Kuphatikiza apo, zida zophatikizira zimatha kugwiritsa ntchito zidziwitso zanthawi kuti zikwaniritse zomwe zimayendetsedwa ndi nthawi ndikuwongolera zotsatira.
Pulogalamu ya Intel Quartus Prime imapanga ma _syn.v mndandanda file mu mtundu wa Verilog HDL, mosasamala kanthu za zomwe zatuluka file mtundu womwe mwafotokoza. Ngati mugwiritsa ntchito netlist pakuphatikiza, muyenera kuphatikiza IP core wrapper file .v kapena .vhd mu Intel Quartus Prime project yanu.

(7) Ngati simunakhazikitse njira ya chida cha EDA- yomwe imakuthandizani kuyambitsa zoyeserera za EDA za chipani chachitatu kuchokera ku Intel Quartus Prime software - yendetsani izi mu ModelSim kapena QuestaSim simulator Tcl console (osati mu pulogalamu ya Intel Quartus Prime. Tcl console) kuti mupewe zolakwika zilizonse.

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3.6. Kupanga Mapangidwe Athunthu
Mutha kugwiritsa ntchito lamulo la Start Compilation pa menyu Processing mu pulogalamu ya Intel Quartus Prime Pro Edition kuti mupange kapangidwe kanu.

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4. Kufotokozera Kwantchito

Chithunzi 5.

F-Tile seri Lite IV Intel FPGA IP imakhala ndi MAC ndi Ethernet PCS. MAC imalumikizana ndi ma PCS achizolowezi kudzera pa MII.

IP imathandizira mitundu iwiri yosinthira:
PAM4–Imapereka mayendedwe 1 mpaka 12 kuti musankhe. IP nthawi zonse imakhazikitsa njira ziwiri za PCS panjira iliyonse mu PAM4 modulation mode.
· NRZ–Imapereka mayendedwe 1 mpaka 16 kuti musankhe.

Njira iliyonse yosinthira imathandizira mitundu iwiri ya data:
· Basic mode-Iyi ndi njira yosakira pomwe deta imatumizidwa popanda paketi yoyambira, kuzungulira kopanda kanthu, komanso kumapeto kwa paketi kuti muwonjezere bandwidth. IP imatenga deta yoyamba yovomerezeka ngati chiyambi cha kuphulika.

Kusamutsa Kwa Data Yoyambira tx_core_clkout tx_avs_ready

tx_avs_valid tx_avs_data rx_core_clkout rx_avs_ready

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_valid rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

ISO 9001:2015 Adalembetsedwa

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Chithunzi 6.

· Full mode-Uku ndiye kusamutsa deta pa paketi. Munjira iyi, IP imatumiza kuphulika ndi kulunzanitsa kozungulira koyambira komanso kumapeto kwa paketi ngati delimiters.

Kutumiza Kwamadongosolo Athunthu tx_core_clkout

tx_avs_ready tx_avs_valid tx_avs_startofpacket tx_avs_endofpacket
tx_avs_data rx_core_clkout rx_avs_ready rx_avs_valid rx_avs_startofpacket rx_avs_endofpacket

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

Zambiri Zofananira · F-Tile seri Lite IV Intel FPGA IP Overview patsamba 6 · F-Tile seri Lite IV Intel FPGA IP Design Exampndi User Guide

4.1. TX Datapath
Dongosolo la TX lili ndi zigawo izi: · Adapter ya MAC · Chotchinga choyika mawu · CRC · MII encoder · PCS block · PMA block

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Chithunzi 7. TX Datapath

Kuchokera kwa ogwiritsa logic

TX MAC

Avalon Streaming Interface

Adapter ya MAC

Sinthani Kuyika kwa Mawu

Mtengo CRC

MII Encoder

MII Interface Custom PCS
PCS ndi PMA

TX Serial Interface Kuzida Zina za FPGA

4.1.1. Adapter ya TX MAC
Adapter ya TX MAC imayang'anira kutumiza kwa data kumalingaliro a wogwiritsa ntchito pogwiritsa ntchito mawonekedwe a Avalon® akukhamukira. Chida ichi chimathandizira kufalitsa chidziwitso chofotokozedwa ndi ogwiritsa ntchito komanso kuwongolera koyenda.

Kusamutsa Zambiri Zofotokozedwa ndi Wogwiritsa

Mumsewu wathunthu, IP imapereka chizindikiro cha tx_is_usr_cmd chomwe mungagwiritse ntchito kuyambitsa kuzungulira kwa chidziwitso cha ogwiritsa ntchito monga kutumiza kwa XOFF/XON kumalingaliro a ogwiritsa ntchito. Mutha kuyambitsa njira yotumizira uthenga wofotokozedwa ndi ogwiritsa ntchito potsimikizira chizindikirochi ndikusamutsa zambiri pogwiritsa ntchito tx_avs_data limodzi ndi zonena za tx_avs_startofpacket ndi tx_avs_valid sign. Chotchingacho chimachotsa tx_avs_ready kwa mikombero iwiri.

Zindikirani:

Zomwe zimatanthauzidwa ndi ogwiritsa ntchito zimapezeka mu Full mode.

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Chithunzi 8.

Kuwongolera Kuyenda

Pali zikhalidwe zomwe TX MAC siili yokonzeka kulandira deta kuchokera kumalingaliro a ogwiritsa ntchito monga nthawi yolumikiziranso ulalo kapena ngati palibe deta yomwe ingatumizidwe kuchokera kwa ogwiritsa ntchito. Pofuna kupewa kutayika kwa data chifukwa cha izi, IP imagwiritsa ntchito siginecha ya tx_avs_ready kuwongolera kayendedwe ka data kuchokera kumalingaliro a ogwiritsa ntchito. IP imachotsa chizindikiro pakachitika zotsatirazi:
· Pamene tx_avs_startofpacket inenedwa, tx_avs_ready imachotsedwa kwa wotchi imodzi.
· Pamene tx_avs_endofpacket inenedwa, tx_avs_ready imachotsedwa kwa wotchi imodzi.
· Pamene ma CW onse awiriawiri atsimikiziridwa kuti tx_avs_ready amadetsedwa kwa mawotchi awiri.
· Pamene RS-FEC mayikidwe chikhomo kuyika kumachitika pa mwambo PCS mawonekedwe, tx_avs_ready ndi deasserted kwa anayi wotchi m'zinthu.
* Mawotchi 17 aliwonse amtundu wa Ethernet mumayendedwe osinthira a PAM4 ndi mawotchi 33 aliwonse amtundu wa Ethernet pamayendedwe a NRZ. The tx_avs_ready imachotsedwa kwa wotchi imodzi.
· Pamene wosuta logic dessserts tx_avs_valid popanda kufala deta.

Zithunzi zotsatirazi zanthawi ndi zakaleamples wa TX MAC adaputala ntchito tx_avs_ready kwa deta kayendedwe.

Flow Control ndi tx_avs_valid Deassertion ndi START/END Ma CW Ophatikizana

tx_core_clkout

tx_avs_valid tx_avs_data

D1 D2 D3

Zovomerezeka zotsekemera zotsekemera

Zamgululi

tx_avs_ready tx_avs_startofpacket

Zosakaniza zokonzeka zopangira mikombero iwiri kuti muyike END-STRT CW

tx_avs_endofpacket

usrif_data

D1 D2 D3

CW_data

DN MAPETO STRT D0 D1 D2 D3 ZOSAVUTA D4

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Chithunzi 9.

Kuwongolera kwa Flow ndi Kuyika kwa Chizindikiro cha Alignment
tx_core_clkout tx_avs_valid

tx_avs_data tx_avs_ready

DN-5 DN-4 DN-3 DN-2 DN-1

DN+1

01234

tx_avs_startofpacket tx_avs_endofpacket

usrif_data CW_data CRC_data MII_data

DN-1 DN DN DN DN DN DN DN DN +1 DN-1 DN DN DN DN DN +1 DN-1 DN DN

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

Zamgululi

DN+1

i_sl_tx_mii_c[7:0]

0x0 pa

ine_sl_tx_mii_am

01234

i_sl_tx_mii_am_pre3

01234

Chithunzi 10.

Kuwongolera kwa Flow ndi START/END Ma CW Ophatikizana Amagwirizana Ndi Kuyika kwa Chizindikiro cha Alignment

tx_core_clkout tx_avs_valid

tx_avs_data

DN-5 DN-4 DN-3 DN-2 DN-1

tx_avs_ready

012 345 6

tx_avs_startofpacket

tx_avs_endofpacket

usrif_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

CW_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

CRC_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

MII_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

Zamgululi

MAPETO STRT D0

i_sl_tx_mii_c[7:0]

0x0 pa

i_sl_tx_mii_am i_sl_tx_mii_am_pre3

01234

4.1.2. Kuyika kwa Control Word (CW).
F-Tile Serial Lite IV Intel FPGA IP imapanga ma CW kutengera ma siginoloji ochokera kwa ogwiritsa ntchito. Ma CW amawonetsa zodulira mapaketi, zidziwitso zamapaketi kapena deta ya ogwiritsa ntchito ku block ya PCS ndipo amachokera ku ma code owongolera a XGMII.
Gome lotsatirali likuwonetsa kufotokozera kwa ma CW othandizidwa:

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Table 11.
YAMBIRITSANI KUGWIRITSA NTCHITO

Kufotokozera kwa Ma CW Othandizidwa

Chiwerengero cha Mawu (1 mawu

= 64 pang'ono)

Inde

EMPTY_CYC

Inde

IDLE

Ayi

DATA

Inde

Mu gulu

Kufotokozera
Chiyambi cha data delimiter. Kutha kwa data delimiter. Liwu lowongolera (CW) la kulumikizana kwa RX. Mzunguliro wopanda kanthu pakusamutsa deta. IDLE (yopanda gulu). Malipiro.

Table 12. CW Field Description
Munda wa RSVD num_valid_bytes_eob
EMPTY eop sop seop align CRC32 usr

Kufotokozera
Malo osungidwa. Itha kugwiritsidwa ntchito kuwonjezera mtsogolo. Zogwirizana ndi 0.
Chiwerengero cha ma byte ovomerezeka mu liwu lomaliza (64-bit). Ichi ndi mtengo wa 3bit. · 3'b000: 8 byte · 3'b001: 1 byte · 3'b010: 2 byte · 3'b011: 3 byte · 3'b100: 4 byte · 3'b101: 5 byte · 3'b110: 6 byte · 3'b111: 7 bati
Chiwerengero cha mawu osavomerezeka kumapeto kwa kuphulika.
Imawonetsa mawonekedwe osinthira a RX Avalon kuti atsimikizire chizindikiro chomaliza.
Imawonetsa mawonekedwe osinthira a RX Avalon kuti awonetse chizindikiro choyambira paketi.
Imawonetsa mawonekedwe a RX Avalon akukhamukira kuti atsimikizire poyambira paketi komanso kumapeto kwa paketi munthawi yomweyo.
Onani kusanja kwa RX.
Mtengo wapatali wa magawo CRC.
Zikuwonetsa kuti mawu owongolera (CW) ali ndi chidziwitso chofotokozedwa ndi ogwiritsa ntchito.

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4.1.2.1. Chiyambi cha kuphulika kwa CW

Chithunzi 11. Kuyamba kwa kuphulika kwa CW Format

YAMBA

63:56

Mtengo RSVD

55:48

Mtengo RSVD

47:40

Mtengo RSVD

deta

39:32 31:24

Chithunzi cha RSVD

23:16

sop usr align=0 seop

15:8

njira

7:0

'hFB(START)

ulamuliro 7:0

Table 13.

Mumode yonse, mutha kuyika START CW potsimikizira tx_avs_startofpacket siginecha. Mukangonena chizindikiro cha tx_avs_startofpacket, sop bit imayikidwa. Mukatsimikizira zonse tx_avs_startofpacket ndi tx_avs_endofpacket siginecha, seop bit imayikidwa.

ANTHU CW Field Makhalidwe
Munda sop/seop
usr (8)
gwirizanitsa

Mtengo

Kutengera tx_is_usr_cmd chizindikiro:

1: Pamene tx_is_usr_cmd = 1

0: Pamene tx_is_usr_cmd = 0

Mu Basic mode, MAC imatumiza START CW pambuyo poti kubwezeretsedwako kuthetsedwa. Ngati palibe deta yomwe ilipo, MAC imatumiza EMPTY_CYC yophatikizika ndi END ndi START CWs mpaka mutayamba kutumiza.

4.1.2.2. Kutha kwa kuphulika kwa CW

Chithunzi 12. Mapeto a kuphulika kwa CW Format

TSIRIZA

63:56

'hFD

55:48

CRC32[31:24]

47:40

CRC32[23:16]

deta 39:32 31:24

CRC32[15:8] CRC32[7:0]

23:16 eop=1 RSVD RSVD RSVD

Mtengo RSVD

15:8

Mtengo RSVD

ZOSAVUTA

7:0

Mtengo RSVD

nambala_valid_bytes_eob

kulamulira

7:0

(8) Izi zimathandizidwa mu Full mode.
Tumizani Ndemanga

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Table 14.

MAC imayika END CW pomwe tx_avs_endofpacket imanenedwa. The END CW ili ndi chiwerengero cha ma byte ovomerezeka pamawu omaliza a data ndi zambiri za CRC.

Mtengo wa CRC ndi zotsatira za 32-bit CRC za data yomwe ili pakati pa START CW ndi mawu a data isanafike END CW.

Gome lotsatirali likuwonetsa kufunikira kwa magawo mu END CW.

END CW Minda Yamtengo
Field eop CRC32 num_valid_bytes_eob

Mtengo 1
Mtengo wa CRC32 Chiwerengero cha ma byte ovomerezeka pamawu omaliza a data.

4.1.2.3. Kuyanjanitsa Pawiri CW

Chithunzi 13. Kuyanjanitsa Paired CW Format

ALIGN CW Penyani ndi START/END

64 + 8bits XGMII Interface

YAMBA

63:56

Mtengo RSVD

55:48

Mtengo RSVD

47:40

Mtengo RSVD

deta

39:32 31:24

Chithunzi cha RSVD

23:16 eop=0 sop=0 usr=0 align=1 seop=0

15:8

Mtengo RSVD

7:0

'hFB

ulamuliro 7:0

64 + 8bits XGMII Interface

TSIRIZA

63:56

'hFD

55:48

Mtengo RSVD

47:40

Mtengo RSVD

deta

39:32 31:24

Chithunzi cha RSVD

23:16 eop=0 RSVD RSVD RSVD

Mtengo RSVD

15:8

Mtengo RSVD

7:0

Mtengo RSVD

ulamuliro 7:0

ALIGN CW ndi CW yolumikizidwa ndi START/END kapena END/START CWs. Mutha kuyika ALIGN paired CW potsimikizira tx_link_reinit siginecha, kukhazikitsa kauntala ya Alignment Period, kapena kuyambitsanso kukonzanso. Pamene ALIGN paired CW yayikidwa, gawo loyanjanitsa limayikidwa ku 1 kuti ayambitse chotchinga cholandirira kuti ayang'ane masanjidwe a data panjira zonse.

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Table 15.

Malingaliro a kampani ALIGN CW Field
Kulinganiza munda
eop sop usr seop

Mtengo 1 0 0 0 0

4.1.2.4. CW yopanda kanthu

Chithunzi 14. Mtundu wa CW wopanda kanthu

EMPTY_CYC Gwirizanitsani ndi END/START

64 + 8bits XGMII Interface

TSIRIZA

63:56

'hFD

55:48

Mtengo RSVD

47:40

Mtengo RSVD

deta

39:32 31:24

Chithunzi cha RSVD

23:16 eop=0 RSVD RSVD RSVD

Mtengo RSVD

15:8

Mtengo RSVD

7:0

Mtengo RSVD

ulamuliro 7:0

64 + 8bits XGMII Interface

YAMBA

63:56

Mtengo RSVD

55:48

Mtengo RSVD

47:40

Mtengo RSVD

deta

39:32 31:24

Chithunzi cha RSVD

23:16

sop=0 usr=0 align=0 seop=0

15:8

Mtengo RSVD

7:0

'hFB

ulamuliro 7:0

Table 16.

Mukathira tx_avs_valid kwa mawotchi awiri pakaphulika, MAC imayika EMPTY_CYC CW yolumikizidwa ndi END/START CWs. Mutha kugwiritsa ntchito CW iyi ngati palibe deta yomwe mungatumizire kwakanthawi.

Mukatsuka tx_avs_valid kwa kuzungulira kumodzi, IP deasssertion tx_avs_valid kuwirikiza kawiri tx_avs_valid deassertion kuti ipange awiri END/START CWs.

EMPTY_CYC CW Field Values
Kulinganiza munda
eop

Mtengo 0 0

anapitiriza…

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Field sop usr seop

Mtengo 0 0 0

4.1.2.5. CW wopanda

Chithunzi 15. Idle CW Format

IDLE CW

63:56

'h07

55:48

'h07

47:40

'h07

deta

39:32 31:24

'h07'h07

23:16

'h07

15:8

'h07

7:0

'h07

ulamuliro 7:0

MAC imayika IDLE CW pamene palibe kutumiza. Panthawi imeneyi, chizindikiro cha tx_avs_valid ndichotsika.
Mutha kugwiritsa ntchito IDLE CW mukamaliza kutumiza kapena kutumiza kuli kopanda ntchito.

4.1.2.6. Mawu a Data

Mawu a data ndi malipiro a paketi. Zowongolera za XGMII zonse zakhazikitsidwa ku 0 mumtundu wa mawu a data.

Chithunzi 16. Data Mawu Format

64 + 8 bits XGMII Interface

DATA MAWU

63:56

data ya ogwiritsa 7

55:48

data ya ogwiritsa 6

47:40

data ya ogwiritsa 5

deta

39:32 31:24

Zogwiritsa ntchito 4 data ya ogwiritsa 3

23:16

data ya ogwiritsa 2

15:8

data ya ogwiritsa 1

7:0

data ya ogwiritsa 0

ulamuliro 7:0

4.1.3. TX CRC
Mutha kuloleza block ya TX CRC pogwiritsa ntchito Yambitsani CRC parameter mu IP Parameter Editor. Izi zimathandizidwa mumitundu yonse ya Basic ndi Full.

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MAC imawonjezera mtengo wa CRC ku END CW potsimikizira chizindikiro cha tx_avs_endofpacket. Munjira ya BASIC, ALIGN CW yokha yolumikizidwa ndi END CW ili ndi gawo lovomerezeka la CRC.
Chotchinga cha TX CRC chimalumikizana ndi block ya TX Control Word Insertion ndi block ya TX MII Encode. Chotchinga cha TX CRC chimawerengera mtengo wa CRC pamtengo wa 64-bit pamtundu uliwonse kuyambira pa START CW mpaka END CW.
Mutha kunena kuti crc_error_inject siginecha kuti muwononge mwadala deta munjira inayake kuti mupange zolakwika za CRC.

4.1.4. TX MII Encoder

TX MII encoder imagwira ntchito yotumiza paketi kuchokera ku MAC kupita ku TX PCS.

Chithunzi chotsatira chikuwonetsa mawonekedwe a data pa basi ya 8-bit MII mu PAM4 modulation mode. The START ndi END CW amawonekera kamodzi munjira ziwiri zilizonse za MII.

Chithunzi 17. PAM4 Modulation Mode MII Data Pattern

CYCLE 1

CYCLE 2

CYCLE 3

CYCLE 4

CYCLE 5

SOP_CW

DATA_1

DATA_9 DATA_17

IDLE

DATA_DUMMY SOP_CW
DATA_DUMMY

DATA_2 DATA_3 DATA_4

DATA_10 DATA_11 DATA_12

DATA_18 DATA_19 DATA_20

EOP_CW IDLE
EOP_CW

SOP_CW

DATA_5 DATA_13 DATA_21

IDLE

DATA_DUMMY DATA_6 DATA_14 DATA_22 EOP_CW

SOP_CW DATA_DUMMY

DATA_7 DATA_8

DATA_15 DATA_16

DATA_23 DATA_24

IDLE EOP_CW

Chithunzi chotsatira chikuwonetsa mawonekedwe a data pa basi ya 8-bit MII mumayendedwe a NRZ. The START ndi END CW amawonekera m'njira zonse za MII.

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Chithunzi 18. NRZ Modulation Mode MII Data Pattern

CYCLE 1

CYCLE 2

CYCLE 3

SOP_CW

DATA_1

DATA_9

SOP_CW

DATA_2 DATA_10

SOP_CW SOP_CW

DATA_3 DATA_4

DATA_11 DATA_12

SOP_CW

DATA_5 DATA_13

SOP_CW

DATA_6 DATA_14

SOP_CW

DATA_7 DATA_15

SOP_CW

DATA_8 DATA_16

CYCLE 4 DATA_17 DATA_18 DATA_19 DATA_20 DATA_21 DATA_22 DATA_23 DATA_24

CYCLE 5 EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW

4.1.5. TX PCS ndi PMA
F-Tile Serial Lite IV Intel FPGA IP imakonza transceiver ya F-tile kukhala Ethernet PCS mode.

4.2. Chithunzi cha RX
RX datapath ili ndi zigawo izi: · PMA block · PCS block · MII decoder · CRC · Deskew block · Control Word kuchotsa block

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Chithunzi 19. RX Datapath

Kwa ogwiritsa logic Avalon Streaming Interface
Chithunzi cha RX MAC
Control Mawu Kuchotsa
Deskew

Mtengo CRC

MII Decoder

MII Interface Custom PCS
PCS ndi PMA

RX Serial Interface Kuchokera ku Chipangizo china cha FPGA
4.2.1. RX PCS ndi PMA
F-Tile Serial Lite IV Intel FPGA IP imakonza transceiver ya F-tile kukhala Ethernet PCS mode.
4.2.2. RX MII Decoder
Chida ichi chikuwonetsa ngati zomwe zikubwera zili ndi mawu owongolera ndi zolembera. The RX MII decoder imatulutsa deta mu mawonekedwe a 1-bit yovomerezeka, chizindikiro cha 1-bit, chizindikiro cha 1bit control, ndi data ya 64-bit pamzere uliwonse.
4.2.3. Mtengo wa RX CRC
Mutha kuloleza block ya TX CRC pogwiritsa ntchito Yambitsani CRC parameter mu IP Parameter Editor. Izi zimathandizidwa mumitundu yonse ya Basic ndi Full. Ma block a RX CRC amalumikizana ndi RX Control Word Removal ndi RX MII Decoder block. IP imanena kuti rx_crc_error chizindikiro pakachitika cholakwika cha CRC.

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IP imachotsa rx_crc_error pakuphulika kulikonse. Ndizotuluka ku malingaliro a ogwiritsa ntchito pakuwongolera zolakwika za ogwiritsa.
4.2.4. Chithunzi cha RX
RX deskew block imazindikira zolembera za njira iliyonse ndikugwirizanitsanso deta isanatumize ku chipika chochotsa cha RX CW.
Mutha kusankha kulola maziko a IP kuti agwirizanitse deta panjira iliyonse pokhapokha ngati cholakwika chayanjanitsa chikachitika pokhazikitsa Yambitsani Auto Alignment parameter mu IP parameter Editor. Mukayimitsa mawonekedwe owongolera okha, IP core imatsimikizira rx_error siginecha kuwonetsa cholakwika cha kusanja. Muyenera kunena rx_link_reinit kuti muyambitse njira yoyanjanitsa pamene cholakwika cha njirayo chichitika.
Deskew ya RX imazindikira zolembera zotengera makina a boma. Chithunzi chotsatira chikuwonetsa mayiko omwe ali mu RX deskew block.

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Chithunzi 20.

RX Deskew Lane Alignment State Machine yokhala ndi Auto Alignment Enabled Flow Chart
Yambani

IDLE

Bwezerani = 1 inde ayi

Ma PC onse

ayi

njira zakonzeka?

inde

DIKIRANI

Zolemba zonse zolumikizirana ayi
wapezeka?
inde
KUGWIRITSA NTCHITO

ayi
inde Timeout?

inde
Wataya masanjidwe?
palibe Mapeto

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Chithunzi 21.

RX Deskew Lane Alignment State Machine yokhala ndi Auto Alignment Disabled Flow Chart
Yambani

IDLE

Bwezerani = 1 inde ayi

Ma PC onse

ayi

njira zakonzeka?

inde

inde
rx_link_reinit =1
palibe ERROR

ayi inde Timeout?

DIKIRANI
ayi Zolemba zonse zolunzanitsa
wapezeka?
inde ALIGN

inde
Wataya masanjidwe?
ayi
TSIRIZA
1. Njira yolumikizira imayamba ndi dziko la IDLE. Chidacho chimasunthira ku WAIT state njira zonse za PCS zikakonzeka ndipo rx_link_reinit yatsitsidwa.
2. M'chigawo cha WAIT, chipikacho chimayang'ana zolembera zonse zomwe zapezeka zimatsimikiziridwa mkati mwa kuzungulira komweko. Ngati izi ndi zoona, chipikacho chimapita ku ALIGNED state.
3. Pamene chipikacho chili mu ALIGNED state, zimasonyeza kuti misewu ikugwirizana. M'chigawochi, chipikacho chikupitiriza kuyang'anitsitsa kayendetsedwe kake kanjira ndikuwona ngati zolembera zonse zilipo mkati mwa njira yomweyo. Ngati chizindikiro chimodzi sichipezeka mumayendedwe omwewo ndipo yambitsani Auto Alignment parameter yakhazikitsidwa, chipikacho chimapita ku

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IDLE boma kuti ayambitsenso njira yolumikizirana. Ngati Yambitsani Kuyanjanitsa Magalimoto sikunakhazikitsidwe ndipo cholembera chimodzi sichipezeka munthawi yomweyo, chipikacho chimapita ku ERROR state ndikudikirira kuti malingaliro a wogwiritsa anene rx_link_reinit chizindikiro kuti ayambitse njira yoyanjanitsa.

Chithunzi 22. Kuyanjanitsanso Njira ndi Yambitsani Kuyanjanitsa Magalimoto Kuyatsa rx_core_clk

rx_link_up

rx_link_reinit

ndi_zolemba_zonse

Deskew State

ALGNED

IDLE

DIKIRANI

ALGNED

AUTO_ALIGN = 1

Chithunzi 23. Kuyanjanitsanso Njira ndi Yambitsani Kuyanjanitsa Kwagalimoto Kuyimitsidwa rx_core_clk

rx_link_up

rx_link_reinit

ndi_zolemba_zonse

Deskew State

ALGNED

ZOLAKWA

IDLE

DIKIRANI

ALGNED

AUTO_ALIGN = 0
4.2.5. Kuchotsedwa kwa RX CW
Chotchinga ichi chimasankha ma CW ndikutumiza deta kumalingaliro a ogwiritsa ntchito pogwiritsa ntchito mawonekedwe a Avalon akukhamukira pambuyo pochotsa ma CW.
Ngati palibe deta yolondola yomwe ilipo, chotchinga chochotsa cha RX CW chimatsitsa chizindikiro cha rx_avs_valid.
Mu FULL mode, ngati wogwiritsa ntchito akhazikitsidwa, chipikachi chimatsimikizira chizindikiro cha rx_is_usr_cmd ndipo deta mu nthawi yoyamba ya wotchi imagwiritsidwa ntchito ngati chidziwitso kapena lamulo.
Pamene rx_avs_ready dessserts ndi rx_avs_valid akunena, chotchinga chochotsa cha RX CW chimapanga cholakwika pamalingaliro a wosuta.
Ma sigino a Avalon okhudzana ndi chipikachi ndi motere: · rx_avs_startofpacket · rx_avs_endofpacket · rx_avs_channel · rx_avs_empty · rx_avs_data

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· rx_avs_valid
· rx_num_valid_bytes_eob
rx_is_usr_cmd (ikupezeka mu Full mode)
4.3. F-Tile seri Lite IV Intel FPGA IP Clock Architecture
F-Tile Serial Lite IV Intel FPGA IP ili ndi zolowetsa mawotchi anayi omwe amapanga mawotchi kupita ku midadada yosiyanasiyana: · Transceiver reference clock (xcvr_ref_clk)–Wotchi yolowetsa kuchokera ku wotchi yakunja
tchipisi kapena ma oscillator omwe amapanga mawotchi a TX MAC, RX MAC, ndi TX ndi RX midadada ya PCS. Onani ku Parameters kuti muthandizire pafupipafupi. · TX core clock (tx_core_clk)–Wotchiyi idachokera ku transceiver PLL imagwiritsidwa ntchito pa TX MAC. Wotchi iyi ndi wotchi yotulutsa kuchokera ku transceiver ya F-tile kuti ilumikizane ndi malingaliro a ogwiritsa ntchito a TX. · RX core clock (rx_core_clk)-Wotchi iyi imachokera ku transceiver PLL imagwiritsidwa ntchito pa RX deskew FIFO ndi RX MAC. Wotchi iyi ndi wotchi yotulutsa kuchokera ku transceiver ya F-tile kuti ilumikizane ndi malingaliro a ogwiritsa ntchito a RX. · Wotchi ya transceiver reconfiguration interface (reconfig_clk) -wotchi yolowetsa kuchokera ku mawotchi akunja kapena ma oscillator omwe amapanga mawotchi a mawonekedwe a F-tile transceiver reconfiguration mu TX ndi RX datapaths. Mafupipafupi a wotchi ndi 100 mpaka 162 MHz.
Chithunzi chotsatirachi chikuwonetsa madera a F-Tile Serial Lite IV Intel FPGA IP wotchi ndi zolumikizira mkati mwa IP.

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Chithunzi 24.

F-Tile seri Lite IV Intel FPGA IP Clock Architecture

Oscillator

FPGA1
F-Tile Serial Lite IV Intel FPGA IP Transceiver Reconfiguration Interface Clock
(reconfig_clk)

tx_core_clkout (kulumikizana ndi malingaliro a ogwiritsa ntchito)

tx_core_clk= clk_pll_div64[mid_ch]

FPGA2

F-Tile seri Lite IV Intel FPGA IP

Transceiver Reconfiguration Interface Clock

(reconfig_clk)

Oscillator

rx_core_clk= clk_pll_div64[mid_ch]

rx_core_clkout (kulumikizana ndi malingaliro a ogwiritsa ntchito)

clk_pll_div64[mid_ch] clk_pll_div64[n-1:0]

Avalon Streaming Interface TX Data
TX MAC

serial_link[n-1:0]

Deskew

FIFO

Avalon Streaming Interface RX Data RX MAC

Avalon Streaming Interface RX Data
Chithunzi cha RX MAC

Zolemba za FIFO

rx_core_clkout (kulumikizana ndi malingaliro a ogwiritsa ntchito)

rx_core_clk= clk_pll_div64[mid_ch]

Ma PC Okhazikika

serial_link[n-1:0]

TX MAC

Avalon Streaming Interface TX Data

tx_core_clk= clk_pll_div64[mid_ch]

tx_core_clkout (kulumikizana ndi malingaliro a ogwiritsa ntchito)

Transceiver Ref Clock (xcvr_ref_clk)
Transceiver Ref Clock (xcvr_ref_clk)

Oscillator*

Nthano

Chithunzi cha FPGA
TX core clock domain
RX core clock domain
Transceiver reference wotchi domain Zizindikilo za data

4.4. Bwezeretsani ndi Kuyambitsa Link
Ma MAC, F-tile Hard IP, ndi midadada yosinthiranso ali ndi ma siginecha osiyana siyana: · midadada ya TX ndi RX MAC imagwiritsa ntchito tx_core_rst_n ndi rx_core_rst_n siginecha yokhazikitsanso. · tx_pcs_fec_phy_reset_n ndi rx_pcs_fec_phy_reset_n yambitsaninso ma siginali
chowongolera chotsitsimutsa kuti mukhazikitsenso F-tile Hard IP. · Chida chosinthiranso chimagwiritsa ntchito reconfig_reset reset siginali.

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Chithunzi 25. Bwezeretsani Zomangamanga
Avalon Streaming Interface TX Data
MAC
Avalon Streaming SYNC Interface RX Data

FPGA F-tile seri Lite IV Intel FPGA IP

tx_mii rx_mii
phy_ehip_ready phy_rx_pcs_ready

F-tile Hard IP

TX Serial Data RX Serial Data

tx_core_rstn rx_core_rstn tx_pcs_fec_phy_reset_n rx_pcs_fec_phy_reset_n reconfig_reset

Bwezeretsani Zomveka
Zina Zofananira · Bwezeretsani Maupangiri patsamba 51 · F-Tile Serial Lite IV Intel FPGA IP Design Exampndi User Guide
4.4.1. Kukhazikitsanso kwa TX ndi Kuyambitsa Njira
Kukhazikitsanso kwa TX kwa F-Tile Serial Lite IV Intel FPGA IP kuli motere: 1. Assert tx_pcs_fec_phy_reset_n, tx_core_rst_n, ndi reconfig_reset
munthawi yomweyo kukhazikitsanso F-tile yolimba IP, MAC, ndi midadada yokonzanso. Tulutsani tx_pcs_fec_phy_reset_n ndikukonzanso kukonzanso mukadikirira tx_reset_ack kuti muwonetsetse kuti midadada yakhazikitsidwa bwino. 2. IP ndiye imatsimikizira phy_tx_lanes_stable, tx_pll_locked, ndi phy_ehip_ready zizindikiro pambuyo tx_pcs_fec_phy_reset_n reset kumasulidwa, kusonyeza TX PHY yakonzeka kufalitsa. 3. tx_core_rst_n siginecha desserts pambuyo phy_ehip_ready chizindikiro chikukwera. 4. IP imayamba kutumiza zilembo za IDLE pa mawonekedwe a MII pamene MAC yatha. Palibe chofunikira pakuwongolera njira ya TX ndi skewing chifukwa misewu yonse imagwiritsa ntchito wotchi yomweyo. 5. Potumiza zilembo za IDLE, MAC imatsimikizira tx_link_up chizindikiro. 6. Kenako MAC imayamba kutumiza ALIGN yophatikizika ndi START/END kapena END/START CW pakanthawi kokhazikika kuti ayambitse njira yolumikizira wolandila wolumikizidwa.

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Chithunzi 26.

TX Bwezerani ndi Kuyambitsa Nthawi Yoyambira
reconfig_sl_clk

reconfig_clk

tx_core_rst_n

tx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

tx_reset_ack

tx_pll _locked

phy_tx_lanes_stable

phy_ehip_ready

tx_li nk_up

7
5 6 8

4.4.2. Kukhazikitsanso kwa RX ndi Kuyambitsa Kutsata
Kukhazikitsanso RX kwa F-Tile Serial Lite IV Intel FPGA IP ndi motere:
1. Assert rx_pcs_fec_phy_reset_n, rx_core_rst_n, ndi reconfig_reset nthawi imodzi kuti mukonzenso F-tile hard IP, MAC, ndi midadada yokonzanso. Tulutsani rx_pcs_fec_phy_reset_n ndikukonzanso kukonzanso mukadikirira rx_reset_ack kuti muwonetsetse kuti midadada yakhazikitsidwa bwino.
2. IP ndiye imatsimikizira chizindikiro cha phy_rx_pcs_ready pambuyo poti kubwezeretsanso kwa PCS kumasulidwa, kusonyeza kuti RX PHY yakonzeka kufalitsa.
3. rx_core_rst_n siginecha desserts pambuyo phy_rx_pcs_ready chizindikiro chikukwera.
4. IP imayambitsa ndondomeko yoyanjanitsa kanjira ikatha kukhazikitsidwanso kwa RX MAC ndikulandira ALIGN yophatikizidwa ndi START/END kapena END/START CW.
5. Chida cha RX deskew chimatsimikizira kuti rx_link_up siginecha ikatha kutsata njira zonse.
6. IP ndiye imatsimikizira chizindikiro cha rx_link_up ku malingaliro a wogwiritsa ntchito kuti asonyeze kuti ulalo wa RX uli wokonzeka kuyamba kulandira deta.

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Chithunzi 27. Kubwezeretsanso kwa RX ndi Kuyambitsa Nthawi Yoyambira
reconfig_sl_clk

reconfig_clk

rx_core_rst_n

rx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

rx_reset_ack

rx_cdr_lock

rx_block_lock

rx_pcs_ready

rx_link_up

3 3 3 2

4 5 5

6 7

4.5. Mawerengedwe Ogwirizana ndi Bandwidth Efficiency

Kuwerengera kwa F-Tile Serial Lite IV Intel FPGA IP bandwidth kuli motere:

Bandwidth mphamvu = raw_rate * 64/66 * (burst_size - burst_size_ovhd)/burst_size * [align_marker_period / (align_marker_period + align_marker_width)] * [(srl4_align_period – 2) / srl4_align_period

Table 17. Bandwidth Efficiency Zosiyanasiyana Kufotokozera

Zosintha

Kufotokozera

raw_rate burst_size

Uwu ndiye mulingo wocheperako womwe umatheka ndi mawonekedwe a serial. raw_rate = SERDES m'lifupi * transceiver wotchi pafupipafupi Example: raw_rate = 64 * 402.812500 Gbps = 25.78 Gbps
Mtengo wa kukula kophulika. Kuti muwerenge kuchuluka kwamphamvu kwa bandwidth, gwiritsani ntchito mtengo wamba wophulika. Kuti muwongolere kwambiri, gwiritsani ntchito kuchuluka kwa kukula kophulika.

burst_size_ovhd

Kuphulika kwa mtengo wapamwamba.
Mumode yonse, mtengo wa burst_size_ovhd ukulozera ku START ndi END ma CW ophatikizidwa.
Mumawonekedwe Oyambira, mulibe burst_size_ovhd chifukwa mulibe START ndi END ma CW ophatikizana.

align_marker_period

Mtengo wa nthawi yomwe cholembera cholozera chayikidwa. Mtengo wake ndi 81920 wotchi yozungulira yophatikizira ndi 1280 pakuyerekeza mwachangu. Mtengo uwu umachokera ku PCS hard logic.

align_marker_width srl4_align_period

Kuchuluka kwa mawotchi omwe chizindikiro cholozera chovomerezeka chimakwezedwa.
Chiwerengero cha mawotchi ozungulira pakati pa zolembera ziwiri. Mutha kukhazikitsa mtengo uwu pogwiritsa ntchito gawo la Alignment Period mu IP Parameter Editor.

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Mawerengedwe a ulalo wa ulalo ali pansipa: Mlingo wothandiza = bandwidth magwiridwe antchito * raw_rate Mutha kupeza kuchuluka kwa wotchi ya ogwiritsa ntchito ndi equation yotsatirayi. Kuwerengera pafupipafupi kwa wotchi ya wogwiritsa ntchito kumatengera kusanja kwa data kosalekeza ndipo palibe kuzungulira kwa IDLE komwe kumachitika pamalingaliro a ogwiritsa ntchito. Mlingo uwu ndiwofunikira popanga malingaliro a wogwiritsa ntchito FIFO kupewa kusefukira kwa FIFO. Kuchuluka kwa wotchi pafupipafupi = mlingo wogwira mtima / 64

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5. Magawo

Table 18. F-Tile Serial Lite IV Intel FPGA IP Parameter Kufotokozera

Parameter

Mtengo

Zosasintha

Kufotokozera

General Design Zosankha

Mtundu wa PMA modulation

PAM4 · NRZ

PAM4

Sankhani PCS modulation mode.

Mtengo wa PMA

· FHT · FGT

Mtengo wa FGT

Imasankha mtundu wa transceiver.

Mtengo wapatali wa magawo PMA

Pa PAM4 mode:
- Mtundu wa transceiver wa FGT: 20 Gbps 58 Gbps
- Mtundu wa transceiver wa FHT: 56.1 Gbps, 58 Gbps, 116 Gbps
· Kwa mawonekedwe a NRZ:
- Mtundu wa transceiver wa FGT: 10 Gbps 28.05 Gbps
- Mtundu wa transceiver wa FHT: 28.05 Gbps, 58 Gbps

56.1 (FGT/FHT PAM4)
28.05 Gbps (FGT/FHT NRZ)

Imatanthawuza kuchuluka kwa data komwe kumatulutsidwa ndi transceiver kuphatikiza kutumiza ndi mitu ina. Mtengo wake umawerengeredwa ndi IP pozungulira mpaka 1 decimal malo mu Gbps unit.

PMA mode

· Duplex · Tx · Rx

Duplex

Kwa mtundu wa transceiver wa FHT, mayendedwe othandizidwa ndi duplex okha. Pamtundu wa transceiver wa FGT, njira yothandizidwa ndi Duplex, Tx, ndi Rx.

Mtengo wa PMA

Pa PAM4 mode:

njira

- 1 mpaka 12

· Kwa mawonekedwe a NRZ:

- 1 mpaka 16

Sankhani nambala ya mayendedwe. Pamapangidwe a simplex, nambala yothandizidwa ndi mayendedwe ndi 1.

Mafupipafupi a wotchi ya PLL

· Kwa mtundu wa transceiver wa FHT: 156.25 MHz
· Pamtundu wa transceiver wa FGT: 27.5 MHz 379.84375 MHz, kutengera kuchuluka kwa data ya transceiver yosankhidwa.

· Kwa mtundu wa transceiver wa FHT: 156.25 MHz
· Pamtundu wa transceiver wa FGT: 165 MHz

Imatchula mafupipafupi a wotchi ya transceiver.

System PLL

—

wotchi yolozera

pafupipafupi

170 MHz

Zikupezeka pamtundu wa transceiver wa FHT. Imatchula wotchi ya System PLL ndipo idzagwiritsidwa ntchito ngati F-Tile Reference ndi System PLL Clocks Intel FPGA IP kuti ipange wotchi ya System PLL.

Ma frequency a System PLL
Nthawi Yogwirizanitsa

- 128 65536

Yambitsani RS-FEC

Yambitsani

876.5625 MHz 128 Yambitsani

Imatchula pafupipafupi mawotchi a System PLL.
Imatchula nthawi yolowera. Mtengo uyenera kukhala x2. Yatsani kuti mutsegule mawonekedwe a RS-FEC.
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Parameter

Mtengo

Zosasintha

Kufotokozera

Letsani

Pa PAM4 PCS modulation mode, RS-FEC imayatsidwa nthawi zonse.

User Interface

Njira yotsatsira

· ZOKHUDZA · BASIC

Zodzaza

Sankhani kukhamukira deta kwa IP.

Zokwanira: Njira iyi imatumiza kuzungulira kwa paketi ndi kumapeto kwa paketi mkati mwa chimango.

Zofunika: Iyi ndi njira yoyeretsera yomwe deta imatumizidwa popanda paketi yoyambira, yopanda kanthu, ndi mapeto a paketi kuti muwonjezere bandwidth.

Yambitsani CRC

Thandizani Letsani

Letsani

Yatsani kuti muzitha kuzindikira ndi kukonza zolakwika za CRC.

Yambitsani kuyanjanitsa kwadzidzidzi

Thandizani Letsani

Letsani

Yatsani kuti muzitha kuyanjanitsa njira yokhayokha.

Yambitsani debug endpoint

Thandizani Letsani

Letsani

Ikakhala ON, F-Tile Serial Lite IV Intel FPGA IP imaphatikizapo Debug Endpoint yomwe imalumikizana mkati ndi mawonekedwe a Avalon memory. IP imatha kuchita mayeso ena ndikuchotsa zolakwika kudzera mwa JTAG pogwiritsa ntchito System Console. Mtengo wofikira ndi Wozimitsa.

Kuphatikizika kwa Simplex (Zosintha izi zimangopezeka mukasankha FGT dual simplex design.)

RSFEC idayatsidwa pa seri Lite IV Simplex IP yoyikidwa panjira yomweyo ya FGT.

Thandizani Letsani

Letsani

Yatsani njirayi ngati mukufuna kusakanikirana kosinthika ndi RS-FEC kuyatsa ndikuyimitsa F-Tile Serial Lite IV Intel FPGA IP munjira ziwiri zosavuta zamtundu wa transceiver wa NRZ, pomwe TX ndi RX zonse zimayikidwa pa FGT yomweyo. njira (ma).

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6. F-Tile seri Lite IV Intel FPGA IP Interface Signals

6.1. Zizindikiro za Clock

Table 19. Zizindikiro za Clock

Dzina

M'lifupi Direction

Kufotokozera

tx_core_clkout

Wotchi yayikulu ya TX ya mawonekedwe a TX PCS, TX MAC ndi malingaliro a ogwiritsa ntchito

TX datapath.

Wotchi iyi imapangidwa kuchokera ku block ya PCS.

rx_core_clkout

Wotchi yoyambira ya RX ya mawonekedwe a PCS a RX, RX deskew FIFO, RX MAC

ndi malingaliro ogwiritsa ntchito mu RX datapath.

Wotchi iyi imapangidwa kuchokera ku block ya PCS.

xcvr_ref_clk
reconfig_clk reconfig_sl_clk

Wotchi yolozera ya Transceiver.

Mtundu wa transceiver ukakhazikitsidwa ku FGT, lumikizani wotchi iyi ndi chizindikiro chotuluka (out_refclk_fgt_0) cha F-Tile Reference ndi System PLL Clocks Intel FPGA IP. Pamene mtundu wa transceiver wakhazikitsidwa ku FHT, gwirizanitsani

wotchiyi ku chizindikiro chotuluka (out_fht_cmmpll_clk_0) cha F-Tile Reference ndi System PLL Clocks Intel FPGA IP.

Onani ku Parameters kuti muthandizire pafupipafupi.

Wotchi yolowetsa yosinthira mawonekedwe a transceiver.

Mafupipafupi a wotchi ndi 100 mpaka 162 MHz.

Lumikizani siginecha ya wotchiyi ku mawotchi akunja kapena ma oscillator.

Wotchi yolowetsa yosinthira mawonekedwe a transceiver.

Mafupipafupi a wotchi ndi 100 mpaka 162 MHz.

Lumikizani siginecha ya wotchiyi ku mawotchi akunja kapena ma oscillator.

out_systempll_clk_ 1

Zolowetsa

Wotchi ya System PLL.
Lumikizani wotchi iyi ndi chizindikiro chotuluka (out_systempll_clk_0) cha F-Tile Reference ndi System PLL Clocks Intel FPGA IP.

Zambiri Zofananira patsamba 42

6.2. Bwezerani Zizindikiro

Table 20. Bwezeraninso Zizindikiro

Dzina

M'lifupi Direction

tx_core_rst_n

Zolowetsa

Clock Domain Asynchronous

rx_core_rst_n

Zolowetsa

Asynchronous

tx_pcs_fec_phy_reset_n 1

Zolowetsa

Asynchronous

Kufotokozera

Chizindikiro chokhazikika chotsika. Kukhazikitsanso F-Tile seri Lite IV TX MAC.

Chizindikiro chokhazikika chotsika. Kukhazikitsanso F-Tile Serial Lite IV RX MAC.

Chizindikiro chokhazikika chotsika.

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Dzina

Width Direction Clock Domain

Kufotokozera

Kukonzanso ma PC amtundu wa F-Tile seri Lite IV TX.

rx_pcs_fec_phy_reset_n 1

Zolowetsa

Asynchronous

Chizindikiro chokhazikika chotsika. Kukonzanso ma PC a F-Tile Serial Lite IV RX.

reconfig_reset

Zolowetsa

reconfig_clk Chizindikiro chokhazikitsanso kwambiri.

Imakhazikitsanso chipika chokonzanso mawonekedwe a Avalon memory-mapped interface.

reconfig_sl_reset

Lowetsani chizindikiro cha reconfig_sl_clk Active-high reset.

Imakhazikitsanso chipika chokonzanso mawonekedwe a Avalon memory-mapped interface.

6.3. Zizindikiro za MAC

Table 21.

Zizindikiro za TX MAC
Pa tebulo ili, N ikuyimira chiwerengero cha misewu yokhazikitsidwa mu IP parameter editor.

Dzina

M'lifupi

Direction Clock Domain

Kufotokozera

tx_avs_ready

Output tx_core_clkout Chizindikiro cha Avalon.

Zikanenedwa, zikuwonetsa kuti TX MAC ndiyokonzeka kuvomereza deta.

tx_avs_data

· (64*N)*2 (PAM4 mode)
64*N (NRZ mode)

Zolowetsa

tx_core_clkout chizindikiro cha Avalon. TX data.

tx_avs_channel

Lowetsani tx_core_clkout chizindikiro cha Avalon.

Nambala ya tchanelo ya data yomwe imasamutsidwa panthawiyi.

Chizindikirochi sichipezeka mu Basic mode.

tx_avs_valid

Lowetsani tx_core_clkout chizindikiro cha Avalon.

Zikanenedwa, zikuwonetsa kuti chizindikiro cha data cha TX ndichovomerezeka.

tx_avs_startofpacket

Lowetsani tx_core_clkout chizindikiro cha Avalon.

Zikanenedwa, zikuwonetsa kuyambika kwa paketi ya data ya TX.

Onetsani kuzungulira koloko kumodzi pa paketi iliyonse.

Chizindikirochi sichipezeka mu Basic mode.

tx_avs_endofpacket

Lowetsani tx_core_clkout chizindikiro cha Avalon.

Zikanenedwa, zikuwonetsa kutha kwa paketi ya data ya TX.

Onetsani kuzungulira koloko kumodzi pa paketi iliyonse.

Chizindikirochi sichipezeka mu Basic mode.

tx_avs_zopanda

Lowetsani tx_core_clkout chizindikiro cha Avalon.

Imawonetsa kuchuluka kwa mawu osavomerezeka pakuphulika komaliza kwa data ya TX.

Chizindikirochi sichipezeka mu Basic mode.

tx_num_valid_bytes_eob

Zolowetsa

tx_core_clkout

Imawonetsa kuchuluka kwa ma byte ovomerezeka mu liwu lomaliza la kuphulika komaliza. Chizindikirochi sichipezeka mu Basic mode.
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Dzina tx_is_usr_cmd
tx_link_up tx_link_reinit
crc_error_inject tx_error

M'lifupi 1
1 1
ndi 5

Direction Clock Domain

Kufotokozera

Zolowetsa

tx_core_clkout

Zikanenedwa, chizindikirochi chimayambitsa kuzungulira kwa chidziwitso cha ogwiritsa ntchito.
Nenani chizindikirochi pa wotchi yofanana ndi tx_startofpacket kunena.
Chizindikirochi sichipezeka mu Basic mode.

Output tx_core_clkout Zikanenedwa, zimasonyeza kuti ulalo wa data wa TX wakonzeka kutumiza deta.

Zotulutsa

tx_core_clkout

Pamene atsimikiziridwa, chizindikiro ichi chimayambitsa kukonzanso njira.
Nenani chizindikirochi kuti muzungulira koloko imodzi kuti muyambitse MAC kutumiza ALIGN CW.

Zolowetsa

tx_core_clkout Ikanenedwa, MAC imalowetsa cholakwika cha CRC32 kumayendedwe osankhidwa.

Output tx_core_clkout Osagwiritsidwa ntchito.

Chithunzi chotsatirachi chikuwonetsa zakaleample ya TX kutumiza kwa data kwa mawu 10 kuchokera kumalingaliro a ogwiritsa ntchito kudutsa misewu 10 ya TX.

Chithunzi 28.

Chithunzi cha TX Data Transmission Timing
tx_core_clkout

tx_avs_valid

tx_avs_ready

tx_avs_startofpackets

tx_avs_endofpackets

tx_avs_data

0,1..,19 10,11…19 …… N-10..

0,1,2, ,9

… N-10..

Njira ya 0

……………

Mtengo wa 0

N-10 MAPETO STT 0

Njira ya 1

……………

Mtengo wa 1

N-9 MAPETO STT 1

N-10 END IDLE IDLE N-9 END IDLE IDLE

Njira ya 9

……………

Mtengo wa 9

N-1 MAPETO STT 9

N-1 MAPETO IDLE IDLE

Table 22.

Zizindikiro za RX MAC
Pa tebulo ili, N ikuyimira chiwerengero cha misewu yokhazikitsidwa mu IP parameter editor.

Dzina

M'lifupi

Direction Clock Domain

Kufotokozera

rx_avs_ready

Lowetsani rx_core_clkout chizindikiro cha Avalon.

Zikanenedwa, zimasonyeza kuti malingaliro a wogwiritsa ntchito ali okonzeka kuvomereza deta.

rx_avs_data

(64*N)*2 (PAM4 mode)
64*N (NRZ mode)

Zotulutsa

rx_core_clkout chizindikiro cha Avalon. Zithunzi za RX.

rx_avs_channel

Kutulutsa rx_core_clkout Chizindikiro cha Avalon.

Nambala ya tchanelo ya data

adalandira pamayendedwe apano.

Chizindikirochi sichipezeka mu Basic mode.

rx_avs_valid

Kutulutsa rx_core_clkout Chizindikiro cha Avalon.

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Dzina

M'lifupi

Direction Clock Domain

Kufotokozera

Zikanenedwa, zikuwonetsa kuti chizindikiro cha data cha RX ndichovomerezeka.

rx_avs_startofpacket

Kutulutsa rx_core_clkout Chizindikiro cha Avalon.

Zikanenedwa, zikuwonetsa kuyambika kwa paketi ya data ya RX.

Onetsani kuzungulira koloko kumodzi pa paketi iliyonse.

Chizindikirochi sichipezeka mu Basic mode.

rx_avs_endofpacket

Kutulutsa rx_core_clkout Chizindikiro cha Avalon.

Zikanenedwa, zikuwonetsa kutha kwa paketi ya data ya RX.

Onetsani kuzungulira koloko kumodzi pa paketi iliyonse.

Chizindikirochi sichipezeka mu Basic mode.

rx_avs_zopanda

Kutulutsa rx_core_clkout Chizindikiro cha Avalon.

Imawonetsa kuchuluka kwa mawu osavomerezeka pakuphulika komaliza kwa data ya RX.

Chizindikirochi sichipezeka mu Basic mode.

rx_num_valid_bytes_eob

Zotulutsa

rx_core_clkout Ikuwonetsa kuchuluka kwa ma byte ovomerezeka mu liwu lomaliza la kuphulika komaliza.
Chizindikirochi sichipezeka mu Basic mode.

rx_is_usr_cmd

Output rx_core_clkout Ikanenedwa, chizindikirochi chimayambitsa wosuta-

kutanthauzira kwa chidziwitso.

Nenani chizindikirochi pa wotchi yofanana ndi tx_startofpacket kunena.

Chizindikirochi sichipezeka mu Basic mode.

rx_link_up

Kutulutsa rx_core_clkout Kukanenedwa, kumawonetsa ulalo wa data wa RX

yakonzeka kulandira deta.

rx_link_reinit

Lowetsani rx_core_clkout Akanenedweratu, chizindikirochi chimayamba mayendedwe

kukonzanso.

Mukayimitsa Yambitsani Kuyimitsa Magalimoto, perekani chizindikiro ichi kuti muyendetse koloko imodzi kuti muyambitse MAC kuti igwirizanenso mayendedwe. Ngati Yambitsani Auto Alignment yakhazikitsidwa, MAC ilumikizaninso misewu yokha.

Osatchula chizindikiro ichi pamene Yambitsani Kuyanjanitsa Magalimoto kwakhazikitsidwa.

rx_error

(N*2*2)+3 (PAM4 mode)
(N*2)*3 (NRZ mode)

Zotulutsa

rx_core_clkout

Zikanenedwa, zikuwonetsa zolakwika zomwe zimachitika mu RX datapath.
· [(N*2+2):N+3] = Imawonetsa zolakwika za PCS panjira inayake.
· [N+2] = Ikuwonetsa cholakwika pamalumikizidwe. Yambitsaninso kuyan'anila kwa kanjira ngati pang'onopang'ono uku kutsimikiziridwa.
· [N+1]= Imawonetsa kuti deta imatumizidwa kumalingaliro a ogwiritsa ntchito pomwe malingaliro a ogwiritsa ntchito sanakonzekere.
· [N] = Imawonetsa kutayika kwa masinthidwe.
· [(N-1):0] = Zimasonyeza kuti deta ili ndi zolakwika za CRC.

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6.4. Transceiver Reconfiguration Signals

Table 23.

PCS Reconfiguration Signals
Pa tebulo ili, N ikuyimira chiwerengero cha misewu yokhazikitsidwa mu IP parameter editor.

Dzina

M'lifupi

Direction Clock Domain

Kufotokozera

reconfig_sl_read

Lowetsani reconfig_sl_ PCS reconfiguration kuwerenga lamulo

clk

zizindikiro.

reconfig_sl_write

Lowetsani reconfig_sl_ PCS reconfiguration kulemba

clk

kulamula zizindikiro.

reconfig_sl_address

14 bits + clogb2N

Zolowetsa

reconfig_sl_ clk

Imatchulanso adilesi ya mawonekedwe a PCS a Avalon munjira yosankhidwa.
Msewu uliwonse uli ndi ma bits 14 ndipo chapamwamba chimayimira njira yolowera.
Example, pamapangidwe a 4-lane NRZ/PAM4, yokhala ndi reconfig_sl_address[13:0] ponena za mtengo wa adilesi:
· reconfig_sl_address[15:1 4] yakhazikitsidwa ku 00 = adilesi ya msewu 0.
· reconfig_sl_address[15:1 4] yakhazikitsidwa ku 01 = adilesi ya msewu 1.
· reconfig_sl_address[15:1 4] yakhazikitsidwa ku 10 = adilesi ya msewu 2.
· reconfig_sl_address[15:1 4] yakhazikitsidwa ku 11 = adilesi ya msewu 3.

reconfig_sl_readdata

Output reconfig_sl_ Imatchulanso zosintha za PCS

clk

kuwerengedwa ndi kuzungulira kokonzeka mu a

njira yosankhidwa.

reconfig_sl_waitrequest

Output reconfig_sl_ Ikuyimira kukonzanso kwa PCS

clk

Avalon kukumbukira-mapu mawonekedwe

chizindikiro choyimitsa mumsewu wosankhidwa.

reconfig_sl_writedata

Input reconfig_sl_ Imafotokoza za kukonzanso kwa PCS

clk

kulembedwa mozungulira mu a

njira yosankhidwa.

reconfig_sl_readdata_vali

Zotulutsa

reconfig_sl_ Imatchulanso kukonzanso kwa PCS

clk

zomwe zalandilidwa ndizovomerezeka muzosankhidwa

msewu.

Table 24.

F-Tile Hard IP Reconfiguration Signals
Pa tebulo ili, N ikuyimira chiwerengero cha misewu yokhazikitsidwa mu IP parameter editor.

Dzina

M'lifupi

Direction Clock Domain

Kufotokozera

reconfig_read

Lowetsani reconfig_clk PMA reconfiguration werengani

kulamula zizindikiro.

reconfig_write

Lowetsani reconfig_clk PMA reconfiguration kulemba

kulamula zizindikiro.

reconfig_address

18 bits + clog2bN

Zolowetsa

reconfig_clk

Imatchula adilesi ya PMA Avalon yojambulidwa mumsewu wosankhidwa.
anapitiriza…

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Dzina
reconfig_readdata reconfig_waitrequest reconfig_writedata reconfig_readdatavalid

M'lifupi
32 1 32 1

Direction Clock Domain

Kufotokozera

M'njira zonse ziwiri za PAM4 ad NRZ, msewu uliwonse uli ndi ma bits 18 ndipo zotsalira zam'mwamba zimatanthawuza njira yodutsamo.
Example, pamapangidwe anjira 4:
· reconfig_address[19:18] khalani ku 00 = adilesi ya msewu 0.
· reconfig_address[19:18] khalani ku 01 = adilesi ya msewu 1.
· reconfig_address[19:18] khalani ku 10 = adilesi ya msewu 2.
· reconfig_address[19:18] khalani ku 11 = adilesi ya msewu 3.

Zotulutsa

reconfig_clk Imafotokoza za PMA kuti iwerengedwe ndi kuzungulira kokonzeka mumsewu wosankhidwa.

Zotulutsa

reconfig_clk Imayimira PMA Avalon yokumbukira mawonekedwe oyimitsa mawonekedwe munjira yosankhidwa.

Zolowetsa

reconfig_clk Imatanthawuza deta ya PMA kuti ilembedwe pamayendedwe olembera mumsewu wosankhidwa.

Zotulutsa

reconfig_clk Imatanthawuza kukonzanso kwa PMA zomwe zalandilidwa ndizovomerezeka munjira yosankhidwa.

6.5. Zizindikiro za PMA

Table 25.

Zizindikiro za PMA
Pa tebulo ili, N ikuyimira chiwerengero cha misewu yokhazikitsidwa mu IP parameter editor.

Dzina

M'lifupi

Direction Clock Domain

Kufotokozera

phy_tx_lanes_stable

N*2 (PAM4 mode)
N (NRZ mode)

Zotulutsa

Asynchronous Zikanenedwa, zimasonyeza kuti TX datapath yakonzeka kutumiza deta.

tx_pll_locked

N*2 (PAM4 mode)
N (NRZ mode)

Zotulutsa

Asynchronous Ikanenedwa, imasonyeza kuti TX PLL yapeza malo otsekera.

phy_ehip_ready

N*2 (PAM4 mode)
N (NRZ mode)

Zotulutsa

Asynchronous

Zikanenedwa, zikuwonetsa kuti PCS yokhazikika yamaliza kukhazikitsidwa kwamkati ndikukonzekera kutumizidwa.
Chizindikirochi chimatsimikizira pambuyo tx_pcs_fec_phy_reset_n ndi tx_pcs_fec_phy_reset_nare kuchotsedwa.

tx_serial_data

Zikhomo za TX serial clock TX zikhomo.

rx_serial_data

Lowetsani RX siriyo wotchi RX siriyo zikhomo.

phy_rx_block_lock

N*2 (PAM4 mode)
N (NRZ mode)

Zotulutsa

Asynchronous Ikanenedwa, ikuwonetsa kuti mayendedwe a 66b block amaliza panjira.

rx_cdr_lock

N*2 (PAM4 mode)

Zotulutsa

Asynchronous

Pamene ananena, limasonyeza kuti anachira mawotchi zokhoma deta.
anapitiriza…

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Dzina phy_rx_pcs_ready phy_rx_hi_ber

M'lifupi

Direction Clock Domain

Kufotokozera

N (NRZ mode)

N*2 (PAM4 mode)
N (NRZ mode)

Zotulutsa

Asynchronous

Zikanenedwa, zikuwonetsa kuti njira za RX za njira yofananira ya Efaneti ndizogwirizana kwathunthu ndikukonzekera kulandira deta.

N*2 (PAM4 mode)
N (NRZ mode)

Zotulutsa

Asynchronous

Zikanenedwa, zikuwonetsa kuti RX PCS ya njira yofananira ya Ethernet ili mu HI BER state.

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7. Kupanga ndi F-Tile seri Lite IV Intel FPGA IP

7.1. Bwezerani Malangizo
Tsatirani malangizowa kuti mukhazikitsenso kukonzanso dongosolo lanu.
Mangani tx_pcs_fec_phy_reset_n ndi rx_pcs_fec_phy_reset_n siginecha palimodzi pamlingo wadongosolo kuti mukhazikitsenso TX ndi RX PCS nthawi imodzi.
· Assert tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, tx_core_rst_n, rx_core_rst_n, ndi reconfig_reset zizindikiro nthawi yomweyo. Onani ku Reset and Link Initialization kuti mumve zambiri zakusinthanso kwa IP ndikutsatizana koyambira.
Gwirani tx_pcs_fec_phy_reset_n, ndi rx_pcs_fec_phy_reset_n siginecha yotsika, ndi reconfig_reset siginecha yokwera ndikudikirira tx_reset_ack ndi rx_reset_ack kuti mukonzenso F-tile molimba IP ndi midadada yokonzanso.
· Kuti mukwaniritse kulumikizana mwachangu pakati pa zida za FPGA, yambitsaninso ma IP olumikizidwa a F-Tile seri Lite IV Intel FPGA nthawi imodzi. Onani F-Tile seri Lite IV Intel FPGA IP Design Example User Guide kuti mudziwe zambiri zowunika ulalo wa IP TX ndi RX pogwiritsa ntchito zida.
Zambiri Zogwirizana
· Bwezeraninso ndikuyambitsanso kulumikizana patsamba 37
F-Tile seri Lite IV Intel FPGA IP Design Exampndi User Guide

7.2. Malangizo Oyendetsera Zolakwa

Gome lotsatirali likulemba malangizo oyendetsera zolakwika pazolakwika zomwe zitha kuchitika ndi kapangidwe ka F-Tile Serial Lite IV Intel FPGA IP.

Table 26. Mkhalidwe Wolakwika ndi Malangizo Oyendetsera

Zolakwika
Njira imodzi kapena zingapo sizingakhazikitse kulumikizana pambuyo pa nthawi yoperekedwa.

Malangizo
Gwiritsani ntchito nthawi yoti mukhazikitsenso ulalo pamlingo wofunsira.

Njira imataya kulankhulana pambuyo pokhazikika.
Njira imataya kulankhulana panthawi ya deskew.

Izi zikhoza kuchitika pambuyo kapena panthawi ya kusamutsa deta. Limbikitsani kuzindikira kutayika kwa ulalo pamlingo wofunsira ndikukhazikitsanso ulalo.
Tsatirani njira yolumikiziranso ulalo panjira yolakwika. Muyenera kuwonetsetsa kuti mayendedwe a board sadutsa 320 UI.

Kuwongolera njira zotayika pambuyo poti njira zonse zalumikizidwa.

Izi zikhoza kuchitika pambuyo kapena panthawi yotumizira deta. Limbikitsani kuzindikira kutayika kwa kanjira pamlingo wofunsira kuti muyambitsenso njira yoyanjanitsa.

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8. F-Tile Serial Lite IV Intel FPGA IP User Guide Archives

Mitundu ya IP ndi yofanana ndi mitundu ya Intel Quartus Prime Design Suite mpaka v19.1. Kuchokera ku Intel Quartus Prime Design Suite software version 19.2 kapena mtsogolo, ma IP cores ali ndi dongosolo latsopano la IP.

Ngati mtundu wa IP core sunatchulidwe, chiwongolero cha ogwiritsa ntchito pamtundu wakale wa IP akugwira ntchito.

Intel Quartus Prime Version
21.3

Mtundu wa IP Core 3.0.0

Wogwiritsa Ntchito F-Tile seri Lite IV Intel® FPGA IP User Guide

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9. Document Revision History for the F-Tile Serial Lite IV Intel FPGA IP User Guide

Mtundu Wolemba 2022.04.28
2021.11.16 2021.10.22 2021.08.18

Intel Quartus Prime Version
22.1
21.3 21.3 21.2

Mtundu wa IP 5.0.0
3.0.0 3.0.0 2.0.0

Zosintha
Tebulo Losinthidwa: F-Tile Serial Lite IV Intel FPGA IP Features - Malongosoledwe Osinthidwa Kasamutsa Data ndi thandizo la FHT transceiver rate: 58G NRZ, 58G PAM4, ndi 116G PAM4
· Table Yosinthidwa: F-Tile Serial Lite IV Intel FPGA IP Parameter Description - Yowonjezedwa magawo atsopano · System PLL reference wotchi pafupipafupi · Yambitsani debug endpoint - Sinthani Makhalidwe a PMA data rate - Kusinthidwa kwa parameter kuti ifanane ndi GUI
· Kusinthidwa kufotokozera kwa kusamutsa deta mu Table: F-Tile Serial Lite IV Intel FPGA IP Features.
· Kusinthidwa dzina la tebulo IP kukhala F-Tile Serial Lite IV Intel FPGA IP Parameter Kufotokozera mu gawo la Parameters kuti zimveke bwino.
· Table Yosinthidwa: Magawo a IP: - Anawonjezera gawo latsopano-RSFEC yoyatsidwa pa seri Lite IV Simplex IP yoyikidwa panjira (ma FGT). - Sinthani zosintha zanthawi zonse za Transceiver reference wotchi pafupipafupi.
Kutulutsidwa koyamba.

ISO 9001:2015 Adalembetsedwa

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	Intel F Tile seri Lite IV Intel FPGA IP [pdf] Buku Logwiritsa Ntchito F Tile seri Lite IV Intel FPGA IP, F Tile seri Lite IV, Intel FPGA IP
	Intel F-Tile seri Lite IV Intel FPGA IP [pdf] Buku Logwiritsa Ntchito F-Tile Serial Lite IV Intel FPGA IP, Serial Lite IV Intel FPGA IP, Lite IV Intel FPGA IP, IV Intel FPGA IP, FPGA IP, IP

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F Tile seri Lite IV Intel FPGA IP

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