NXP S32K39/S32K37 Electrification Mcus

 Introduction

This document compares the features of the S32K344 to the S32K396 family of devices and identifies differences that affect the migration of an application. The S32K3 MCUs of 32/bit AEC-Q100 qualified MCUs combine a scalable family of Arm® Cortex- M7® cores-based microcontrollers in single, dual, and lockstep core configurations, supporting up to ASIL D function safety automotive and industrial applications.

Context

Figure 1 shows the compatibility of the new S32K39/7 device with its predecessor S32K34x and the new S32K35x device being developed in parallel. All the S32K3xx shares the same architecture. S32K39/7 offers higher performances and extended analog/timers modules. Software written for S32K344 can be effortlessly ported to S32K39/7. In the 289 MapBGA package, the certain pin compatibility is kept between the S32K344 and S32K396 devices. Additional new pin functions are assigned to new peripherals.

 Comparison with S32K344

The following table compares some of the prominent features between S32K344 and S32K396.

Table 1. S32Kxx family feature comparison

1.  Cortex-M7 DMIPS/MHz 2.14-3.23.
2. Final DMIPS is in a range based on compiler setting. The low number uses the “ground rules” laid out in the Dhrystone documentation. The high number uses the in lining of functions of a simultaneous (“multifile”) compilation.

Color wheel description:

In summary: S32K344 vs S32K396

• In addition to the new modules in S32K396, the other main difference is the number of modules. Some modules have also been slightly changed.
• Increase the number of cores to 4, one pair of cores is in permanent lock-step. The other pair of cores can be either lock-step or split-lock, so up to 3 cores could be used in total. The system clock frequency has been increased from 160MHz to 320MHz.
• Except for some changes in the number and content of EIM, ERM, and FCCU channels, the safety, and security solutions on S32K344 are same as S32K396.
• S32K396 176 LQFP is not compatible with the S32K344 172 MaxQFP package. They are two different packages.

 Platform architecture

Figure 2 shows the block diagram for S32K396.
Figure 3 shows the block diagram for S32K344. The main differences are shown in Table 2.

The platform architectures of both are basically the same. S32k396 add some new peripherals, for example, SDADC, Zipwire, eTPU, eFlexPWM, SWG, and CoolFlux DSP.

Table 2. Platform differences

 Module features difference

Core and systems

 OMU
The S32K396 devices support calibration by the use of the Overlay Management Unit, it has 4x OMU instance.

• Two are added in permanent lockstep mode for two cores in permanent lockstep mode
• Two in slit-lock mode, for the other 2 cores in split-lock mode There is no OMU on the S32K344.

MSCM
MSCM provides information of the system cores and can identify the core that is running currently. As compared with S32K344, since three cores are on S32K396, the number of registers that define the configuration information for the core increases to three. Register interrupt router CPn interrupt generation (IRCP0IGR0 -IRCP1IGR3) and interrupts router CPn interrupt status (IRCP0ISR0 – IRCP1ISR3), where n increased to three. In addition, this module provides more AHB gasket configuration (IAHBCFGREG) features.

 TSPC
No TSPC on S32K396.

 AXBS_lite
The crossbar switch connects bus masters and bus slaves using a crossbar switch structure. S32K396 has seven AXBS, as compared to S32K344, two more AXBS are added for DMA1 and Zipwire.

 eDMA
S32K396 has two eDMA instances, each having 32 channels. Whereas eDMA_1 is in lockstep for self-check . S32K344 supports 1x DMA, not in lock-step.

 DMAMUX
The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called the slot, to any of the 16 DMA channels. S32K396 has four DMAMUX instances, DMA channel configuration registers 0-3 support a periodic trigger function. S32K344 has two DMAMUX, all DMA channel configuration registers support periodic trigger functions. DMAMUX_0 and DMAMUX_1 channels are mapped to eDMA_0 channels and DMAMUX_2 and DMAMUX_3 channels are mapped to eDMA_1 channels.

 XBIC
Table 3 shows the differences of XBIC for S32K344 and S32K396.

Table 3. XBIC differences

Memories and memory overview
The following table shows the differences of memories for S32K344 and S32K396. Table

4. Memory general differences

The memory configuration for S32K396 is the same as the configuration of S32K344, including Embedded Flash Memory (c40asf), Flash Memory Controller (PFLASH) and RAM Controller (PRAMC).
There is a few new Master ID added for new modules, such as EMAC, Zipwire, eDMA1 and Cortex-M7_2 on the S32K396.

 Clocking

Clock sources
There are four clock sources available on S32K396 as compared to S32K344, differing in that S32K396 does not have support for a slow external oscillator (SXOSC). Parameters of the other clock sources remain the same as on the S32K344 device.

 System clocks
Main system clocks are generated using MC_CGM MUX_0. Compared to S32K344, there is one more divider to support the generation of CM7_CORE_CLK as the main clock for cores. CORE_CLK is used as a crossbar, peripheral bridge, SRAM, flash memory, QSPI, and fast-speed peripheral clock. In contrast to S32K344 where this clock is also used as a source for CM7 cores. QSPI_MEM_CLK is double the frequency compared to S32K344 since the core clock is also doubled. See the summary in the table below.

Table 5. System clock comparison between s32k39 and s32k344

 Clock generation MC_CGM
S32K396 supports additional multiplexers MUX_13_DC_0[DIV] for STM2 clock, MUX_15_DC_0 for LFAST, and MUX_16_DC_0 for SWG clock. There is an additional CMU_FC_6 implemented on S32K396 to monitor CM7_CORE_CLK over and under frequency with FXOSC as a reference clock.

 Security and device GPRs

• The security configurations for HSE_B, DCF records, DCM_GPR, DCM, and MU on S32K396 are almost the same as the configuration on S32K344. No huge difference between them.
• There is an extension for QuadSPI SFP at the Configuration_GPR memory map, which responds to the configuration for QuadSPI SFP access.
• There is an extension in the DCM_GPR register, which is extended for Cortex-M7_2 and other new IP or instances, like eTPU and eDMA1. An additional MU_2 is added on S32K396, which is used for communication between application cores.

Modes and power management

 PMC
Table 6 shows the differences between power management controllers for S32K344 and S32K396.

Table 6. PMC differences

Figure 5 shows the power management system block diagram for S32K396. Figure 6 shows the power management system block diagram for S32K344.

The key difference here is that for generating the V11 (generated by the PMC module internally by the linear regulator), there is essential to have an external NMOS with low-threshold voltage, having a connected NMOS_CTRL output pin to its gate on S32K396 to regulate a 1.5 V supply (V15 either provided externally or generated by internal SMPS) down to core voltage (V11). The V15 pin is not a high current input (used for voltage sensing) as compared to S32K344 devices where V11 is generated internally with no external NMOS required and V15 is a high current input.

The following are the additional supply domains as compared to S32K344:

•  VDD_SD_ADC0, VDD_SDADC1: Power supply domain for sigma-delta ADCs. Those power supply inputs must be shorted to the VDD_HV_A domain at the PCB level.
• VDD_SWG: Power supply domain for the sine wave generators. This power supply input must be shorted to the VDD_HV_A domain at the PCB level.
• VDD_LVDS: Power supply domain for the 3.3V LVDS interface used by the Zipwire communication module.

 Safety
Table 7 shows the differences between the safety module for S32K344 and S32K396. In addition to the different number of channels, the content of some channels has also changed. See the S32K396 reference manual for more information.

Table 7. Safety module differences

Real-time control

eFlexPWM
The S32K396 devices support eFlexPWM with 2 instances. eFlexPWM uses the digital Nano-edge module to provide high-resolution PWM outputs. There is no eFlexPWM on the S32K344.

 SAR ADC
Table 8 shows the differences of SAR ADC for S32K344 and S32K396.

Table 8. SARADC differences

 SDADC
The S32K396 devices support SDADC with 4 instances. It can be triggered by different motor control IP. There is no SDADC on the S32K344.

 ADCBIST
The S32K396 devices support ADCBIST. It can create a sine wave for SDADC test measures. There is no ADCBIST on the S32K344.

 LPCMP
Table 9 shows the differences of LPCMP for S32K344 and S32K396.

Table 9. LPCMP differences

eMIOS
Table 10 shows the differences of eMIOS for S32K344 and S32K396.

Table 10. eMIOS differences

Compared to S32K344 only 1 instance of eMIOS is implemented on S32K396. The difference is also in the channel types, on S32K396 all the channels (type Z) support the same set of features. For more details of the features supported by, the eMIOS channels see the S32K396 reference manual. Below are the eMIOS channel type diagrams for S32K344 and S32K396.

 BCTU
There is one more BCTU instance implemented on S32K396 as compared to S32K344 to support an additional four SAR ADC. Table 11 shows the differences of BCTU implementation on S32K344 and S32K396.

Table 11. BCTU differences

TRGMUX
There is one additional TRGMUX_MSC added to support the MSC interface and eTPU channels on S32K396.

CoolFlux DSP
S32K396 supports one instance of CoolFlux DSP with four thread hardware multithreading. There is no CoolFlux DSP on S32K344. It is intended to postprocess raw data from the SDADCs and provide the final samples according to the configured sampling rate. Each thread is to process data from one instance of SDADC. If SDADCs are not used in the application, CoolFlux DSP could be used to perform other operations.

 eTPU
S32K396 supports two Enhanced Time Processing Units (eTPU) with a total of 64 channels. The main frequency reaches 320 MHz. There is no eTPU on S32k344.

 SGEN
The S32K396 devices support Sine Wave Generator (SGEN) modules with two instances. The SGEN generates a high-quality sinusoidal voltage signal. It can be programmed with the desired oscillation frequency and amplitude voltage.

Communication

FlexCAN
The FlexCAN module on S32K396 is similar to the one on S32K344. The configuration for this module is the same as that on S32K344. Only a few differences between them must be known, which have been given in the following tables.
Table 12 shows the differences of the FlexCAN module between S32K396 and S32K344.

Table 12. Differences of FlexCAN between S32K396 and S32K344

Table 13 shows the differences of error injection address mapping between S32K396 and S34K344.

Table 13. Difference of Error injection address mapping between S32K396 and S32K344

All FlexCAN memory must be initialized before operation. Some of these locations are different between S32K396 and S32K344, which is shown in the following table.

Table 14. Differences of the offset address range to be initialized

 Zipwire
Serial Inter-Processor Interface (SIPI) and LVDS Fast Asynchronous Serial Transmission Interface (LFAST) modules work together as a single unit called Zipwire. There is no Zipwire implemented on S32K344.

LPUART
Four instances of LPUART are implemented on S32K396 as compared to sixteen instances implemented on S32K344. The configuration of all the LPUART modules on the S32K396 modules is the same as LPUART_0 to LPUART_3 on S32K344. In addition, there are LPUART_4 to LPUART_15 modules on S32K344. Apart from standard LPUART units there is one additional LPUART_MSC that supports only receiving of the data, and not the transmitting. This module works with the MSC channel communication interface as its upstream part.

 SAI
There is no SAI implemented on S32k396.

 QSPI flash interface
QuadSPI on S32K396 is similar to the module on S32K344, which added some new features including up to eight bidirectional data lines, support for Hyper-RAM, and secure flash protection. The configuration for QuadSPI on S32K344 can be used for the IP on S32K396.

Note: The secure flash protection must be configured properly, which can cause an error when accessing the flash.

Table 15. Differences in QuadSPI between S32K396 and S32K344

 MSC
S32K396 supports a microsecond channel interface (MSC), which is a serial interface designed to provide I/O expansion by reducing the number of MCU pins required to drive output signals. MSC is composed of DSPI and LPUART_MSC modules. There is no MSC implemented on S32K344.

Debug
Additional HSE (MTB) interface is supported in S32K396.

Hardware migration

 Power requirement
S32K396 has two main and flexible power domains VDD_HV_A and VDD_HV_B that must be supplied externally. VDD_HV_A is the main I/O and primary supply for analog modules. VDD_HV_B is secondary I/O. Those are the same as on S32K344. The third domain is V15 in which the on-chip SMPS or an external source generates 1.5 V input. The PMC module of the MCU uses this pin to measure the voltage level of V15. V11 is the domain to supply core and internal logic with 1.1 V. It is driven by an external NFET, which is controlled by a linear regulator inside the PMC. Apart from that there are additional supply sources to power sigma-delta ADCs, Sine wave generators, and LVDS drivers for Zipwire communication.

Table 16. Power domains differences

Note: In the case of 1.5 V generated by on chip SMPS one external ballast generates V15 supply on S32K344. In the case of S32K396 two external transistors are needed: One PMOS for the DCDC block that generates V15 and one NMOS to generate V11. NMOS is mandatory for S32K396 to generate V11 compared to S32K344 where this supply domain does not require external NMOS.

FS26 handshake
If FS26 PMIC provides power supply for S32K396 and Standby mode entry is required for both S32K396 and FS26 certain requirements on hardware connection between MCU and PMIC were added to support Standby mode exit:

• EXTWAKE output of S32K396 (available on PTA8, PTA25, or PTE21) must be routed to WAKE1 of FS26 (pin 47) and that must be configured to detect rising edge on the PMIC side.
• RESET_b from S32K396 (PTA5) must be routed to WAKE2 of FS26 (pin 2) and that must be configured to detect the falling edge on the PMIC side.
• RESET_b from S32K396 must be also routed to RSTB of FS26 (pin 16).
• PGOOD input of S32K396 (available on PTA9, PTA20, or PTA26) must be routed to GPIO2 of FS26 (pin 6).
• SPI connection is requested between S32K396 and FS26 for Standby mode entry request.

Figure 9 illustrates the required connections between S32K396 and FS26 for low-power handshake. LDO1 and LDO2 outputs of FS26 are required to be ON during Standby mode. Not all the connections of the power domains are illustrated for the simplification here.

• 32 balls are new pins that are not present on S32K344 (forming a ring at the center of the package).
• 18 other pins see their functionality change from S32K344 to S32K39x. These pins concern the inclusion of zip wire, sinewave generator, and microsecond bus modules that have dedicated pins on the device.
• 16 pins are now dedicated to ADC channels.

Zipwire, SWG, ADC channels, and microsecond functionalities are implemented as dedicated functions on the pin. There are no other functions on these pins other than these. On a pin that has GPIO capabilities, the goal is to keep the same muxed functions in S32K396 as in S32K344. In average, the number of functions multiplexed on one pin is bigger in S32K396 vs S32K344 to compensate for the use of dedicated pins.

Software migration

1. Summary
   The primary application cores on the S32K396 devices differ from the cores on S32K344 in data cache sizes and split-lock capability and these differences may affect software functionality and performance when porting. Interrupts use a similar routing approach but the interrupt details and table are different between the S32K396 and the S32K344 devices. Except for the newly added peripherals, the addresses of other peripherals are almost the same. For the memory map the start address for the blocks that are kept are the same, the end address is different. So, the SW developed on S32K344 can be ported with not so much effort to S32K396.
2.  Cortex-M7 code
   Code, in general, can be compiled and run on the Cortex-M7 cores without modification. Consider the following guidelines when porting code. The Data cache on the S32K344 devices is half the size of the 16 kB on the S32K396.
3.  Interrupt routing
   The general operation of the interrupts on the S32K396 family is the same as on the S32K344. The sources of interrupts that are common for both devices have the same numbering. Newly added sources replace those which are no longer present in S32K344 (like SAI, eMIOS1-2, LPUART_5-15) and fills the reserved spaces. For details see S32K39_and_S32K37_interrupt_map.xlsx attached to the S32K396 reference manual.
4.  Peripheral use
   There is a high degree of compatibility between peripherals in the two families but the placement in memory is different as is the routing of interrupts and DMA triggers. There are more copies of the peripherals on the S32K396 as compared to the S32K344 and the features of each is higher than that on the S32K344.

 Revision history

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• Date of release: 25 March 2025
• Document identifier: AN14301

Frequently Asked Questions

• Q: Can software written for S32K344 be used on S32K396?
  A: Yes, software written for S32K344 can be effortlessly ported to S32K396.
• Q: Are there any pin compatibility issues between S32K344 and S32K396?
  A: The devices maintain certain pin compatibility, facilitating a seamless transition.
• Q: What are the key differences in performance between S32K344 and S32K396?
  A: S32K396 offers higher performances and extended analog/timers modules compared to S32K344.

Documents / Resources

NXP S32K39/S32K37 Electrification Mcus [pdf] User Guide S32K396, S32K344, S32K39 S32K37 Electrification Mcus, S32K39 S32K37, Electrification Mcus, Mcus

References

• User Manual