NXP S32K39/S32K37 Electrification Mcus User Guide

User Guide for NXP models including: S32K396, S32K344, S32K39 S32K37 Electrification Mcus, S32K39 S32K37, Electrification Mcus, Mcus

S32K344 to S32K39/S32K37 Migration Guide

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S32K396, S32K344, Migration, Features comparison

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S32K344 to S32K39/S32K37 Migration Guide

25 Mar 2025 — This document compares the features of the S32K344 to the S32K396 family of devices and identifies differences that affect the migration of an application.

[PDF] S32K344 to S32K39/S32K37 Migration Guide

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S32K344 to S32K39/S32K37 Migration Guide
Rev. 1.0 -- 25 March 2025

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Document information

Information

Content

Keywords

S32K396, S32K344, Migration, Features comparison

Abstract

The document describes main differences between S32K344 and S32K396 family devices. It helps customers quickly migrate from S32K344 to S32K396.

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S32K344 to S32K39/S32K37 Migration Guide

1 Introduction
This document compares the features of the S32K344 to the S32K396 family of devices and identifies differences that affect the migration of an application. The S32K3 MCUs of 32/bit AEC-Q100 qualified MCUs combine a scalable family of Arm® Cortex- M7® cores-based microcontrollers in single, dual, and lockstep core configurations, supporting up to ASIL D function safety automotive and industrial applications.
2 Context
Figure 1 shows the compatibility of the new S32K39/7 device with its predecessor S32K34x and the new S32K35x device being developed in parallel. All the S32K3xx shares the same architecture. S32K39/7 offers higher performances and extended analog/timers modules. Software written for S32K344 can be effortlessly ported to S32K39/7. In the 289 MapBGA package, the certain pin compatibility is kept between the S32K344 and S32K396 devices. Additional new pin functions are assigned to new peripherals.

Figure 1.Intersection content of S32K3xx family

3 Comparison with S32K344

The following table compares some of the prominent features between S32K344 and S32K396.

Table 1.S32Kxx family feature comparison

feature

S32K344

Safety/ASIL

Number of CPU cores 2 x Arm Cortex M7 @ 160 MHz

Core configuration

1x LS Cortex-M7

Program flash

memory (MB)

OTA (A/B swap)

Data flash memory (KB)

S32K396/394

S32K376/374

ASIL D

4 x Arm Cortex M7 @ 320 MHz

2x M7 Lockstep or 1x M7 LS + 2 M7 split lock

6/4

Yes (hardware) limited to 2M 128

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Table 1.S32Kxx family feature comparison...continued

feature

S32K344

S32K396/394

S32K376/374

Total RAM (KB)

512 KB (incl 192 kB TCM)

800 KB (including 64 KB Standby RAM and 288 KB TCM)

Standby RAM (KB)

Security

HSE_B

DMA Max performance
ASILD DMIPS

1x32 Channels N/A
3425162

2 x 32 channels (1x 32 channels Lock step) 20541 Mixed ASIL
1 Core in Lockstep (ASIL D) and 2 cores in split lock (ASIL-B)
1369

eTPU

N/A

2x engines @ 320MHz (2x32 ch)

N/A

Coolflux DSP

N/A

160 MHz

eFlexPWM

N/A

2 x eFlexPWM/Nanoedge (8 channels each)

FlexCAN (FD)

Ethernet MAC

1 x 10/100 Mbit/s

LPUART (LIN)

Zipwire

N/A

QSPI

LPSPI

MSC (LVDS-

N/A

DSPI + LPUART)

I2C

FlexIO

32 channels

8 channels, 32 pins (Emulating UART, I2C, SPI, I2S, SENT, PWM, Camera I/F)

SAR ADC

SDADC

N/A

SWG

N/A

2x 10 bit

ACMP/LCMP

PIT

SWT

STM

LCU

BCTU

TRIGMUX

eMIOS

3x24 channels

1x 24 channels

RTC

289 MapBGA

257 MapBGA

176 LQFP

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Table 1.S32Kxx family feature comparison...continued

feature

S32K344

S32K396/394

172 MaxQFP

S32K376/374

1. Cortex-M7 DMIPS/MHz 2.14-3.23. 2. Final DMIPS is in a range based on compiler setting. The low number uses the "ground rules" laid out in
the Dhrystone documentation. The high number uses the inlining of functions of a simultaneous ("multifile") compilation.
Color wheel description:

Common for all the devices
S32K344 specific / don't care for K39x and k37x design
S32K37x + S32K39x specific (new compared to S32K344)
S32K39x specific
In summary: S32K344 vs S32K396
· In addition to the new modules in S32K396, the other main difference is the number of modules. Some modules have also been slightly changed.
· Increase the number of cores to 4, one pair of cores is in permanent lock-step. The other pair of cores can be either lock-step or split-lock, so up to 3 cores could be used in total. The system clock frequency has been increased from 160MHz to 320MHz.
· Except for some changes in the number and content of EIM, ERM, and FCCU channels, the safety, and security solutions on S32K344 are same as S32K396.
· S32K396 176 LQFP is not compatible with the S32K344 172 MaxQFP package. They are two different packages.

4 Platform architecture

Figure 2 shows the block diagram for S32K396. Figure 3 shows the block diagram for S32K344. The main differences are shown in Table 2.

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Figure 2.S32K396 block diagram

Figure 3.S32K344 block diagram
The platform architectures of both are basically the same. S32k396 add some new peripherals, for example, SDADC, Zipwire, eTPU, eFlexPWM, SWG, and CoolFlux DSP.

Table 2.Platform differences Feature
Cores

S32K344 ARM Cortex M7_0/1

S32K396 ARM Cortex M7_0/1/2/3

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Table 2.Platform differences...continued

Feature

S32K344

System clock

160 MHz

XBAR

System and peripheral

AIPS3

S32K396 320 MHz System and peripheral
Yes

5 Module features difference

5.1 Core and systems
5.1.1 OMU
The S32K396 devices support calibration by the use of the Overlay Management Unit, it has 4x OMU instance. · Two are added in permanent lockstep mode for two cores in permanent lockstep mode · Two in slit-lock mode, for the other 2 cores in split-lock mode There is no OMU on the S32K344.
5.1.2 MSCM
MSCM provides information of the system cores and can identify the core that is running currently. As compared with S32K344, since three cores are on S32K396, the number of registers that define the configuration information for the core increases to three. Register interrupt router CPn interrupt generation (IRCP0IGR0 IRCP1IGR3) and interrupts router CPn interrupt status (IRCP0ISR0 - IRCP1ISR3), where n increased to three. In addition, this module provides more AHB gasket configuration (IAHBCFGREG) features.
5.1.3 TSPC
No TSPC on S32K396.
5.1.4 AXBS_lite
The crossbar switch connects bus masters and bus slaves using a crossbar switch structure. S32K396 has seven AXBS, as compared to S32K344, two more AXBS are added for DMA1 and Zipwire.
5.1.5 eDMA
S32K396 has two eDMA instances, each having 32 channels. Whereas eDMA_1 is in lockstep for self-check . S32K344 supports 1x DMA, not in lock-step.
5.1.6 DMAMUX
The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called the slot, to any of the 16 DMA channels. S32K396 has four DMAMUX instances, DMA channel configuration registers 0-3 support a periodic trigger function. S32K344 has two DMAMUX, all DMA channel configuration registers support periodic trigger functions. DMAMUX_0 and DMAMUX_1 channels are mapped to eDMA_0 channels and DMAMUX_2 and DMAMUX_3 channels are mapped to eDMA_1 channels.

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Figure 4.DMAMUX block diagram

5.1.7 XBIC

Table 3 shows the differences of XBIC for S32K344 and S32K396.

Table 3.XBIC differences Feature
Instances

S32K344 4 instances

S32K396
6 instances Added 2 instances for eDMA and Zipwire

5.2 Memories and memory overview

The following table shows the differences of memories for S32K344 and S32K396.

Table 4.Memory general differences Feature

S32K344

S32K396

Program flash memory

4 MB

Up to 6 MB

Data Flash

128 KB

Flash memory controller cache

Up to four pages of data (256-bit page size) may be buffered in each prefetch buffer for AHP Port 0, Port 1, and Port 2

Up to four pages of data (256bit page size) may be buffered in each prefetch buffer for AHP Port 0, Port 1, Port 2 and Port 3

RAM

512 KB SRAM (including 384 KB TCM) 800 KB SRAM(including 288 KB TCM)

Standby RAM

32 KB

64 KB

QuadSPI (External Memory interface)

1 instance with up to 4bit bidirectional data lines.

1 instance with up to 8-bit bidirectional data lines. Hyper RAM feature supported. For more details, see the QuadSPI section.

Error Correcting code

YES

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Table 4.Memory general differences...continued Feature

S32K344

Cache

8 KB data and 8 KB instruction cache for each CM7 Core

EEPROM

By Software

S32K396
16 KB data and 16 KB instruction cache for each CM7 Core
By Software

The memory configuration for S32K396 is the same as the configuration of S32K344, including Embedded Flash Memory (c40asf), Flash Memory Controller (PFLASH) and RAM Controller (PRAMC).
There is a few new Master ID added for new modules, such as EMAC, Zipwire, eDMA1 and Cortex-M7_2 on the S32K396.

5.3 Clocking

5.3.1 Clock sources
There are four clock sources available on S32K396 as compared to S32K344, differing in that S32K396 does not have support for a slow external oscillator (SXOSC). Parameters of the other clock sources remain the same as on the S32K344 device.

5.3.2 System clocks

Main system clocks are generated using MC_CGM MUX_0. Compared to S32K344, there is one more divider to support the generation of CM7_CORE_CLK as the main clock for cores. CORE_CLK is used as a crossbar, peripheral bridge, SRAM, flash memory, QSPI, and fast-speed peripheral clock. In contrast to S32K344 where this clock is also used as a source for CM7 cores. QSPI_MEM_CLK is double the frequency compared to S32K344 since the core clock is also doubled. See the summary in the table below.

Table 5.System clock comparison between s32k39 and s32k344

System clock node

System Clock divider

CORE_CLK AIPS_PLAT_CLK AIPS_SLOW_CLK
HSE_CLK DCM_CLK LBIST_CLK QSPI_MEM_CLK CM7_CORE_CLK

MC_CGM.MUX_0_DC_0[DIV] MC_CGM.MUX_0_DC_1[DIV] MC_CGM.MUX_0_DC_2[DIV] MC_CGM.MUX_0_DC_3[DIV] MC_CGM.MUX_0_DC_4[DIV] MC_CGM.MUX_0_DC_5[DIV] MC_CGM.MUX_0_DC_6[DIV] MC_CGM.MUX_0_DC_7[DIV]

Maximum frequency

S32K344

S32K396

160 MHz

80 MHz

40 MHz

120 MHz

48 MHz

160 MHz

320 MHz

5.3.3 Clock generation MC_CGM
S32K396 supports additional multiplexers MUX_13_DC_0[DIV] for STM2 clock, MUX_15_DC_0 for LFAST, and MUX_16_DC_0 for SWG clock.
There is an additional CMU_FC_6 implemented on S32K396 to monitor CM7_CORE_CLK over and under frequency with FXOSC as a reference clock.

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5.4 Security and device GPRs
The security configurations for HSE_B, DCF records, DCM_GPR, DCM, and MU on S32K396 are almost the same as the configuration on S32K344. No huge difference between them.
There is an extension for QuadSPI SFP at the Configuration_GPR memory map, which responds to the configuration for QuadSPI SFP access.
There is an extension in the DCM_GPR register, which is extended for Cortex-M7_2 and other new IP or instances, like eTPU and eDMA1. An additional MU_2 is added on S32K396, which is used for communication between application cores.

5.5 Modes and power management

5.5.1 PMC

Table 6 shows the differences between power management controllers for S32K344 and S32K396.

Table 6.PMC differences Feature Bandgaps
LVR monitors

S32K344 No
No

S32K396
Two bandgaps to enable independent supply generation and monitoring
Two independent LVR monitors for each safety relevant power supply domain

Figure 5 shows the power management system block diagram for S32K396. Figure 6 shows the power management system block diagram for S32K344.
The key difference here is that for generating the V11 (generated by the PMC module internally by the linear regulator), there is essential to have an external NMOS with low-threshold voltage, having a connected NMOS_CTRL output pin to its gate on S32K396 to regulate a 1.5 V supply (V15 either provided externally or generated by internal SMPS) down to core voltage (V11). The V15 pin is not a high current input (used for voltage sensing) as compared to S32K344 devices where V11 is generated internally with no external NMOS required and V15 is a high current input.
The following are the additional supply domains as compared to S32K344:
· VDD_SD_ADC0, VDD_SDADC1: Power supply domain for sigma-delta ADCs. Those power supply inputs must be shorted to the VDD_HV_A domain at the PCB level.
· VDD_SWG: Power supply domain for the sine wave generators. This power supply input must be shorted to the VDD_HV_A domain at the PCB level.
· VDD_LVDS: Power supply domain for the 3.3V LVDS interface used by the Zipwire communication module.

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Figure 5.S32K396 Power management system block diagram

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Figure 6.S32K344 Power management system block diagram

5.6 Safety

Table 7 shows the differences between the safety module for S32K344 and S32K396. In addition to the different number of channels, the content of some channels has also changed. See the S32K396 reference manual for more information.

Table 7.Safety module differences Feature
EIM channel number ERM channel number FCCU NCF channel number

S32K344 31 31 8

S32K396 19 19 15

5.7 Real-time control

5.7.1 eFlexPWM
The S32K396 devices support eFlexPWM with 2 instances. eFlexPWM uses the digital Nano-edge module to provide high-resolution PWM outputs. There is no eFlexPWM on the S32K344.

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5.7.2 SAR ADC

Table 8 shows the differences of SAR ADC for S32K344 and S32K396.

Table 8.SARADC differences

Feature

S32K344

Instance

ADC_0 ADC_1

Resolution 15 bits 15 bits

Number of

precision

channels

Number of

standard

channels

Number of

external

channels

DMA support

Yes

included

Number of

watchdogs

ADC_2 15 bits
8
16
0
Yes 4

ADC_0 15 bits
8
16
32
Yes 4

ADC_1 15 bits
8

S32K396

ADC_2 ADC_3

15 bits 15 bits

ADC_4 15 bits
8

ADC_5 15 bits
8

ADC_6 15 bits
8

Yes

5.7.3 SDADC
The S32K396 devices support SDADC with 4 instances. It can be triggered by different motor control IP. There is no SDADC on the S32K344.

5.7.4 ADCBIST
The S32K396 devices support ADCBIST. It can create a sine wave for SDADC test measures. There is no ADCBIST on the S32K344.

5.7.5 LPCMP

Table 9 shows the differences of LPCMP for S32K344 and S32K396.

Table 9.LPCMP differences

Feature

S32K344

Instances

S32K396 2

5.7.6 eMIOS

Table 10 shows the differences of eMIOS for S32K344 and S32K396.

Table 10.eMIOS differences

Feature

S32K344

Instances

3 (3 x 24 channels)

Channel types

X, Y, G, H

S32K396 1 (1 x 24 channels)
Z

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Compared to S32K344 only 1 instance of eMIOS is implemented on S32K396. The difference is also in the channel types, on S32K396 all the channels (type Z) support the same set of features. For more details of the features supported by, the eMIOS channels see the S32K396 reference manual. Below are the eMIOS channel type diagrams for S32K344 and S32K396.

Figure 7.eMIOS channel layout on S32K34

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Figure 8.eMIOS channel layout on S32K396

5.7.7 BCTU

There is one more BCTU instance implemented on S32K396 as compared to S32K344 to support an additional four SAR ADC. Table 11 shows the differences of BCTU implementation on S32K344 and S32K396.

Table 11.BCTU differences

BCTU instance

Feature

BCTU_0

Number of ADCs

Number of data FIFO
Data FIFO depth

BCTU_1

Number of ADCs
Number of data FIFO

S32K344 3
(ADC0, ADC1, and ADC2) 2
16 (FIFO1) 8 (FIFO2)
-
-

S32K396 3
(ADC0, ADC1, and ADC2) 3
16 (FIFO1) 8 (FIFO2) 8 (FIFO3)
4 (ADC3, ADC4, ADC5, and ADC6)
3

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Table 11.BCTU differences...continued

BCTU instance

Feature

Data FIFO depth

S32K344 -

S32K396
16 (FIFO1) 8 (FIFO2) 8 (FIFO3)

5.7.8 TRGMUX There is one additional TRGMUX_MSC added to support the MSC interface and eTPU channels on S32K396.

5.7.9 CoolFlux DSP
S32K396 supports one instance of CoolFlux DSP with four thread hardware multithreading. There is no CoolFlux DSP on S32K344. It is intended to postprocess raw data from the SDADCs and provide the final samples according to the configured sampling rate. Each thread is to process data from one instance of SDADC.
If SDADCs are not used in the application, CoolFlux DSP could be used to perform other operations.

5.7.10 eTPU
S32K396 supports two Enhanced Time Processing Units (eTPU) with a total of 64 channels. The main frequency reaches 320 MHz. There is no eTPU on S32k344.

5.7.11 SGEN
The S32K396 devices support Sine Wave Generator (SGEN) modules with two instances. The SGEN generates a high-quality sinusoidal voltage signal. It can be programmed with the desired oscillation frequency and amplitude voltage.

5.8 Communication

5.8.1 FlexCAN

The FlexCAN module on S32K396 is similar to the one on S32K344. The configuration for this module is the same as that on S32K344. Only a few differences between them must be known, which have been given in the following tables.
Table 12 shows the differences of the FlexCAN module between S32K396 and S32K344.

Table 12.Differences of FlexCAN between S32K396 and S32K344

Feature instances

CAN0*

CAN1

S32K344 CAN2 CAN3 CAN4 CAN5

CAN0

CAN1

Number of

message

buffers

Enhanced

YES

NO NO

NO YES YES

FIFO

S32K396 CAN2 CAN3 CAN4 CAN5

YES NO NO NO

*For instance FlexCAN0.

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Table 13 shows the differences of error injection address mapping between S32K396 and S34K344.

Table 13.Difference of Error injection address mapping between S32K396 and S32K344

RAM content

Memory

Injection address

map

FlexCAN0 FlexCAN1/2 FlexCAN3/4/5 FlexCAN0/1/2

FlexCAN3/4/5

S32K344

S32K396

FlexCAN Registers ----

Not mapped

MB/s

0080h

0000h

RXIMRs

0880h

600h

400h

200h

600h

400h

RXIMR_0

0A80h

780h

500h

280h

780h

500h

RXIMR_1

0A84h

784h

504h

284h

784h

504h

RXIMR_2

0A88h

788h

508h

288h

788h

508h

RXIMR_3

0A8Ch

78Ch

50Ch

28Ch

78Ch

50Ch

RXIMR_4

0A90h

790h

510h

290h

790h

510h

RXIMR_5

0A94h

794h

514h

294h

794h

514h

Reserved

0A98h

RXMGMASK

0AA0h

7A0h

520h

2A0h

7A0h

520h

RXFGMASK

0AA4h

7A4h

524h

2A4h

7A4h

524h

RX14MASK

0AA8h

7A8h

528h

2A8h

7A8h

528h

RX15MASK

0AACh

7ACh

52Ch

2ACh

7ACh

52Ch

TX_SMB0

0AB0h/0 F28h

7B0h

530h

2B0h

7B0h

530h

RX_SMB0

0AC0h/0 F70h

7C0h/7F8h 540h/578h 2C0h/2F8h

7C0h/7F8h

540h/578h

RX_SMB1

0AD0h/0 FB0h

7D0h/840 550h/5C0h 2D0h/340h

7D0h/840

550h/5C0h

RX_SMB0_TIME_STAMP 0C20h

888h

608h

388h

888h

608h

RX_SMB1_TIME_STAMP 0C24h

88Ch

60Ch

38Ch

88Ch

60Ch

HR_TIME_STAMP 0C30h

890h

610h

390h

890h

610h

Enhanced RX FIFO 2000h

A10h

----

A10h

----

ERFFEL

3000h

1050h

----

1050h

----

All FlexCAN memory must be initialized before operation. Some of these locations are different between S32K396 and S32K344, which is shown in the following table.

Table 14.Differences of the offset address range to be initialized

Chip / Instances

S32K344

FlexCAN0

FlexCAN1/2/3/4/5

Offset address ranges

080hADFh; C20h31FFh

080hADFh; C20hFFFh

S32K396

FlexCAN0/1/2

FlexCAN3/4/5

080hADFh; C20h31FFh

080hADFh; C20hFFFh

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5.8.2 Zipwire
Serial Inter-Processor Interface (SIPI) and LVDS Fast Asynchronous Serial Transmission Interface (LFAST) modules work together as a single unit called Zipwire. There is no Zipwire implemented on S32K344.

5.8.3 LPUART
Four instances of LPUART are implemented on S32K396 as compared to sixteen instances implemented on S32K344. The configuration of all the LPUART modules on the S32K396 modules is the same as LPUART_0 to LPUART_3 on S32K344. In addition, there are LPUART_4 to LPUART_15 modules on S32K344.
Apart from standard LPUART units there is one additional LPUART_MSC that supports only receiving of the data, and not the transmitting. This module works with the MSC channel communication interface as its upstream part.

5.8.4 SAI There is no SAI implemented on S32k396.

5.8.5 QSPI flash interface
QuadSPI on S32K396 is similar to the module on S32K344, which added some new features including up to eight bidirectional data lines, support for Hyper-RAM, and secure flash protection.
The configuration for QuadSPI on S32K344 can be used for the IP on S32K396. Note: The secure flash protection must be configured properly, which can cause an error when accessing the flash.

Table 15.Differences in QuadSPI between S32K396 and S32K344

Feature

S32K344

Data lines

SDR support

YES

DDR support

AHB access

Read

AIPS access

Read/write

AHB buffer

256 B

RX/TX FIFO

128 B

LUT SIZE

Hyper-RAM support

Data learning support

Security flash protection

S32K396 Up to 8
YES YES Read Read/write 1024 B 128 B 16 YES YES YES

5.8.6 MSC
S32K396 supports a microsecond channel interface (MSC), which is a serial interface designed to provide I/O expansion by reducing the number of MCU pins required to drive output signals. MSC is composed of DSPI and LPUART_MSC modules. There is no MSC implemented on S32K344.

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S32K344 to S32K39/S32K37 Migration Guide

5.9 Debug
Additional HSE (MTB) interface is supported in S32K396.

6 Hardware migration

6.1 Power requirement

S32K396 has two main and flexible power domains VDD_HV_A and VDD_HV_B that must be supplied externally. VDD_HV_A is the main I/O and primary supply for analog modules. VDD_HV_B is secondary I/O. Those are the same as on S32K344. The third domain is V15 in which the on-chip SMPS or an external source generates 1.5 V input. The PMC module of the MCU uses this pin to measure the voltage level of V15. V11 is the domain to supply core and internal logic with 1.1 V. It is driven by an external NFET, which is controlled by a linear regulator inside the PMC.
Apart from that there are additional supply sources to power sigma-delta ADCs, Sine wave generators, and LVDS drivers for Zipwire communication.

Table 16.Power domains differences

Feature

S32K344

V15 generated internally

S32K396

Note: In the case of 1.5 V generated by on chip SMPS one external ballast generates V15 supply on S32K344. In the case of S32K396 two external transistors are needed: One PMOS for the DCDC block that generates V15 and one NMOS to generate V11. NMOS is mandatory for S32K396 to generate V11 compared to S32K344 where this supply domain does not require external NMOS.
6.2 FS26 handshake
If FS26 PMIC provides power supply for S32K396 and Standby mode entry is required for both S32K396 and FS26 certain requirements on hardware connection between MCU and PMIC were added to support Standby mode exit:
· EXTWAKE output of S32K396 (available on PTA8, PTA25, or PTE21) must be routed to WAKE1 of FS26 (pin 47) and that must be configured to detect rising edge on the PMIC side.
· RESET_b from S32K396 (PTA5) must be routed to WAKE2 of FS26 (pin 2) and that must be configured to detect the falling edge on the PMIC side.
· RESET_b from S32K396 must be also routed to RSTB of FS26 (pin 16). · PGOOD input of S32K396 (available on PTA9, PTA20, or PTA26) must be routed to GPIO2 of FS26 (pin 6). · SPI connection is requested between S32K396 and FS26 for Standby mode entry request.

AN14301
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AN14301
S32K344 to S32K39/S32K37 Migration Guide

Figure 9 illustrates the required connections between S32K396 and FS26 for low-power handshake. LDO1 and LDO2 outputs of FS26 are required to be ON during Standby mode. Not all the connections of the power domains are illustrated for the simplification here.

Figure 9.S32K396 and FS26 low-power handshake connections
6.3 Pin support
The pinout is compatible between S32K369 and S32K344, however, there are important changes that must be considered. In total, 66-pin locations have different functions between S32K344 and S32K396.
· 32 balls are new pins that are not present on S32K344 (forming a ring at the center of the package). · 18 other pins see their functionality change from S32K344 to S32K39x. These pins concern the inclusion of
zip wire, sinewave generator, and microsecond bus modules that have dedicated pins on the device. · 16 pins are now dedicated to ADC channels.

Figure 10.Comparison of PIN distribution between K344 and K396

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NXP Semiconductors

AN14301
S32K344 to S32K39/S32K37 Migration Guide

Zipwire, SWG, ADC channels, and microsecond functionalities are implemented as dedicated functions on the pin. There are no other functions on these pins other than these. On a pin that has GPIO capabilities, the goal is to keep the same muxed functions in S32K396 as in S32K344. In average, the number of functions multiplexed on one pin is bigger in S32K396 vs S32K344 to compensate for the use of dedicated pins.

7 Software migration

7.1 Summary
The primary application cores on the S32K396 devices differ from the cores on S32K344 in data cache sizes and split-lock capability and these differences may affect software functionality and performance when porting. Interrupts use a similar routing approach but the interrupt details and table are different between the S32K396 and the S32K344 devices. Except for the newly added peripherals, the addresses of other peripherals are almost the same. For the memory map the start address for the blocks that are kept are the same, the end address is different. So, the SW developed on S32K344 can be ported with not so much effort to S32K396.

7.2 Cortex-M7 code
Code, in general, can be compiled and run on the Cortex-M7 cores without modification. Consider the following guidelines when porting code. The Data cache on the S32K344 devices is half the size of the 16 kB on the S32K396.

7.3 Interrupt routing
The general operation of the interrupts on the S32K396 family is the same as on the S32K344. The sources of interrupts that are common for both devices have the same numbering. Newly added sources replace those which are no longer present in S32K344 (like SAI, eMIOS1-2, LPUART_5-15) and fills the reserved spaces. For details see S32K39_and_S32K37_interrupt_map.xlsx attached to the S32K396 reference manual.

7.4 Peripheral use
There is a high degree of compatibility between peripherals in the two families but the placement in memory is different as is the routing of interrupts and DMA triggers. There are more copies of the peripherals on the S32K396 as compared to the S32K344 and the features of each is higher than that on the S32K344.

8 Revision history
Revision history Document ID AN14301 v.1.0

Release date 25 March 2025

Description Initial release

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NXP Semiconductors

AN14301
S32K344 to S32K39/S32K37 Migration Guide

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AN14301
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AN14301
S32K344 to S32K39/S32K37 Migration Guide

Tables

Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5.
Tab. 6. Tab. 7. Tab. 8. Tab. 9. Tab. 10.

S32Kxx family feature comparison ....................2 Platform differences .......................................... 5 XBIC differences ............................................... 7 Memory general differences ..............................7 System clock comparison between s32k39 and s32k344 ......................................................8 PMC differences ................................................9 Safety module differences ...............................11 SARADC differences .......................................12 LPCMP differences ......................................... 12 eMIOS differences ...........................................12

Tab. 11. Tab. 12. Tab. 13. Tab. 14. Tab. 15. Tab. 16.

BCTU differences ............................................ 14 Differences of FlexCAN between S32K396 and S32K344 .................................................. 15 Difference of Error injection address mapping between S32K396 and S32K344 ......16 Differences of the offset address range to be initialized .................................................... 16 Differences in QuadSPI between S32K396 and S32K344 .................................................. 17 Power domains differences ............................. 18

Figures

Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5.
Fig. 6.

Intersection content of S32K3xx family ............. 2 S32K396 block diagram .................................... 5 S32K344 block diagram .................................... 5 DMAMUX block diagram ...................................7 S32K396 Power management system block diagram ..................................................10 S32K344 Power management system block diagram ..................................................11

Fig. 7. Fig. 8. Fig. 9.
Fig. 10.

eMIOS channel layout on S32K34 .................. 13 eMIOS channel layout on S32K396 ................ 14 S32K396 and FS26 low-power handshake connections ..................................................... 19 Comparison of PIN distribution between K344 and K396 ............................................... 19

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Rev. 1.0 -- 25 March 2025

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AN14301
S32K344 to S32K39/S32K37 Migration Guide

Contents

1 2 3 4 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.2 5.3 5.3.1 5.3.2 5.3.3 5.4 5.5 5.5.1 5.6 5.7 5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 5.7.6 5.7.7 5.7.8 5.7.9 5.7.10 5.7.11 5.8 5.8.1 5.8.2 5.8.3 5.8.4 5.8.5 5.8.6 5.9 6 6.1 6.2 6.3 7 7.1 7.2 7.3 7.4 8

Introduction ...................................................... 2 Context ..............................................................2 Comparison with S32K344 ..............................2 Platform architecture .......................................4 Module features difference ............................. 6 Core and systems ............................................. 6 OMU ...................................................................6 MSCM ................................................................ 6 TSPC ................................................................. 6 AXBS_lite ...........................................................6 eDMA ................................................................. 6 DMAMUX ........................................................... 6 XBIC ...................................................................7 Memories and memory overview .......................7 Clocking ............................................................. 8 Clock sources .................................................... 8 System clocks ....................................................8 Clock generation MC_CGM ...............................8 Security and device GPRs ................................ 9 Modes and power management ........................ 9 PMC ................................................................... 9 Safety ...............................................................11 Real-time control ............................................. 11 eFlexPWM ....................................................... 11 SAR ADC .........................................................12 SDADC ............................................................ 12 ADCBIST ......................................................... 12 LPCMP .............................................................12 eMIOS ..............................................................12 BCTU ............................................................... 14 TRGMUX ......................................................... 15 CoolFlux DSP .................................................. 15 eTPU ................................................................15 SGEN ...............................................................15 Communication ................................................ 15 FlexCAN ...........................................................15 Zipwire ............................................................. 17 LPUART ...........................................................17 SAI ................................................................... 17 QSPI flash interface ........................................ 17 MSC ................................................................. 17 Debug .............................................................. 18 Hardware migration ....................................... 18 Power requirement .......................................... 18 FS26 handshake ............................................. 18 Pin support ...................................................... 19 Software migration ........................................ 20 Summary ..........................................................20 Cortex-M7 code ............................................... 20 Interrupt routing ............................................... 20 Peripheral use ................................................. 20 Revision history .............................................20 Legal information ...........................................21

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'.

References

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