NXP FS23 Fail Safe System Basis Chips User Guide

Compatibility: Suitable for S32K processor-based applications and multivendor processors
Features: CAN and LIN transceivers, system and safety features, pin-to-pin and software compatibility

Variants: LDO version to DC-DC version, QM to ASIL B
Output Voltage Settings: Multiple options are available

Operating Frequency: Configurable
Powerup Sequencing: Customizable

FAQs

Q: What are the key features of the FS23 SBC?
- A: The FS23 SBC features CAN and LIN transceivers, scalability options, system and safety features, and compatibility with various processors.

Q: Where can I find more detailed information about the FS23 device?
- A: Detailed information, including the datasheet, design guidelines, and software drivers, is available on the FS23 device webpage.

Introduction

This application note is meant to be used as a launching point for software engineers, as a complement, or as a substitute for NXP’s software drivers.
This document gives guidance on the implementation of SPI or I²C communication protocol between the MCU and the FS23.

This document explains the initialization procedure of the FS23 device and provides an example of a start-up sequence.

General description

The FS23 SBC offers an expandable family of devices that is pin-to-pin and software-compatible. The devices are scalable from the LDO version to the DC-DC version, as well as from QM to ASIL B. The FS23 SBC includes CAN and LIN transceivers, along with several system and safety features for the latest generation of automotive electronic control units (ECUs).
The flexibility of the FS23 SBC makes it suitable for S32K processor-based applications, as well as multivendor processors.

Several device versions are available, offering a choice of output voltage settings, operating frequency, powerup sequencing, and input/output configuration to address multiple applications.

Reference documents

Reference documents and various materials are available on the FS23 device webpage. The webpage provides more detailed information about specific topics:
FS23 data sheet: Information, such as features, functional description, parametric description, register mapping.

FS23 Design Guidelines application note: Information such as application schematics, bill of materials, placement and layout guidelines, application validation data including ISO/non-ISO pulses, and Electromagnetic Compatibility (EMC).
The low-level software driver components are provided as part of the basic enablement for the device, and do not incur an additional charge:

FS23 AUTOSAR software drivers: AUTOSAR and ISO 26262-compliant basic start-up drivers for low-level interfaces. Technical documentation is available as part of the software driver package, detailing supported features such as:

SPI access register function and events handling (SBC_FS23)

CAN/LIN function (CANTRCV_FS23 and LINTRCV_FS23)
Watchdog function (WDG_FS23)

FS23 initialization flow chart example

Figure 1 gives an example of FS23 software initialization. After MCU reset is released (RSTB state is high), the MCU can start FS23 initialization. The initialization must be done within the dedicated 256 ms INIT window.
Running the ABIST is optional, though it is recommended for ASIL B applications. ABIST can be run multiple times in a row. In this example, the MCU checks the cause of the MCU reset (POR, LPOFF, fail-safe) and takes action accordingly. Then the MCU writes INIT safety registers, ending with INIT cyclic redundancy check (CRC).

The next step is watchdog configuration, and unlocking the INIT CRC cyclic check, followed by watchdog refreshes to clear the fault error counter. The first watchdog refresh closes the INIT phase.
Therefore, the subsequent watchdog refreshes must be sent according to watchdog timing configuration. Once the fault error counter is cleared, safety pins FS0B and LIMP0 can be released.

Start-up I²C/SPI sequence example (based on flow chart)

Table 1. Start-up I²C/SPI sequence example

I²C/SPI register mapping of main logic

Table 2. Main register mapping

Refer to Table 70 from the FS23 data sheet.

Register	#	Address							R/W SPI	R/W I²C	Read/Write
Register	#	Adr_6	Adr_5	Adr_4	Adr_3	Adr_2	Adr_1	Adr_0	R/W SPI	R/W I²C	Read/Write
M_DEV_CFG	0	0	0	0	0	0	0	0	0/1	1/0	Read only
M_DEV_PROG_ID	1	0	0	0	0	0	0	1	0/1	1/0	Read only
M_GEN_FLAG	2	0	0	0	0	0	1	0	0/1	1/0	Read only
M_STATUS	3	0	0	0	0	0	1	1	0/1	1/0	Read only
Reserved	4	0	0	0	0	1	0	0	0/1	1/0	Reserved
M_SYS_CFG	5	0	0	0	0	1	0	1	0/1	1/0	Read/Write
M_SYS1_CFG	6	0	0	0	0	1	1	0	0/1	1/0	Read/Write
M_REG_CTRL	7	0	0	0	0	1	1	1	0/1	1/0	Read/Write
Reserved	8	0	0	0	1	0	0	0	0/1	1/0	Reserved
Reserved	9	0	0	0	1	0	0	1	0/1	1/0	Reserved
M_REG_FLG	10	0	0	0	1	0	1	0	0/1	1/0	Read/Write
M_REG_MSK	11	0	0	0	1	0	1	1	0/1	1/0	Read/Write
M_REG1_FLG	12	0	0	0	1	1	0	0	0/1	1/0	Read/Write
M_REG1_MSK	13	0	0	0	1	1	0	1	0/1	1/0	Read/Write
M_IO_CTRL	14	0	0	0	1	1	1	0	0/1	1/0	Write
M_IO_TIMER_FLG	15	0	0	0	1	1	1	1	0/1	1/0	Read/Write
M_IO_TIMER_MSK	16	0	0	1	0	0	0	0	0/1	1/0	Read/Write
M_VSUP_COM_FLG	17	0	0	1	0	0	0	1	0/1	1/0	Read/Write
M_VSUP_COM_MSK	18	0	0	1	0	0	1	0	0/1	1/0	Read/Write
M_IOWU_CFG	19	0	0	1	0	0	1	1	0/1	1/0	Read/Write
M_IOWU_EN	20	0	0	1	0	1	0	0	0/1	1/0	Read/Write
M_IOWU_FLG	21	0	0	1	0	1	0	1	0/1	1/0	Read/Write
M_WU1_EN	22	0	0	1	0	1	1	0	0/1	1/0	Read/Write
M_WU1_FLG	23	0	0	1	0	1	1	1	0/1	1/0	Read/Write
M_TIMER1_CFG	24	0	0	1	1	0	0	0	0/1	1/0	Read/Write
M_TIMER2_CFG	25	0	0	1	1	0	0	1	0/1	1/0	Read/Write
M_TIMER3_CFG	26	0	0	1	1	0	1	0	0/1	1/0	Read/Write
M_PWM1_CFG	27	0	0	1	1	0	1	1	0/1	1/0	Read/Write
M_PWM2_CFG	28	0	0	1	1	1	0	0	0/1	1/0	Read/Write
M_PWM3_CFG	29	0	0	1	1	1	0	1	0/1	1/0	Read/Write
M_TIMER_PWM_CTRL	30	0	0	1	1	1	1	0	0/1	1/0	Read/Write
M_CS_CFG	31	0	0	1	1	1	1	1	0/1	1/0	Read/Write
M_CS_FLG_MSK	32	0	1	0	0	0	0	0	0/1	1/0	Read/Write
M_HSx_SRC_CFG	33	0	1	0	0	0	0	1	0/1	1/0	Read/Write
M_HSx_CTRL	34	0	1	0	0	0	1	0	0/1	1/0	Read/Write
M_HSx_FLG	35	0	1	0	0	0	1	1	0/1	1/0	Read/Write
M_HSx_MSK	36	0	1	0	0	1	0	0	0/1	1/0	Read/Write
M_AMUX_CTRL	37	0	1	0	0	1	0	1	0/1	1/0	Read/Write
M_LDT_CFG1	38	0	1	0	0	1	1	0	0/1	1/0	Read/Write
M_LDT_CFG2	39	0	1	0	0	1	1	1	0/1	1/0	Read/Write
M_LDT_CFG3	40	0	1	0	1	0	0	0	0/1	1/0	Read/Write
M_LDT_CTRL	41	0	1	0	1	0	0	1	0/1	1/0	Read/Write
M_CAN	42	0	1	0	1	0	1	0	0/1	1/0	Read/Write
M_LIN	43	0	1	0	1	0	1	1	0/1	1/0	Read/Write
M_CAN_LIN_MSK	44	0	1	0	1	1	0	0	0/1	1/0	Read/Write
M_MEMORY0	45	0	1	0	1	1	0	1	0/1	1/0	Read/Write
M_MEMORY1	46	0	1	0	1	1	1	0	0/1	1/0	Read/Write

Register mapping of fail-safe logic

Table 3. Safety-related register mapping
Refer to Table 71 from the FS23 data sheet.

Register	#	Address							R/W SPI	R/W I²C	Read/Write
Register	#	Adr_6	Adr_5	Adr_4	Adr_3	Adr_2	Adr_1	Adr_0	R/W SPI	R/W I²C	Read/Write
FS_I_OVUV_CFG1	50	0	1	1	0	0	1	0	0/1	1/0	Write during INIT, then read only
FS_I_OVUV_CFG2	51	0	1	1	0	0	1	1	0/1	1/0	Write during INIT, then read only
FS_I_FCCU_CFG	52	0	1	1	0	1	0	0	0/1	1/0	Write during INIT, then read only
Reserved	53	0	1	1	0	1	0	1	0/1	1/0	Reserved
FS_I_FSSM_CFG	54	0	1	1	0	1	1	0	0/1	1/0	Write during INIT, thenr ead only
FS_I_WD_CFG	55	0	1	1	0	1	1	1	0/1	1/0	Write during INIT, then read only
FS_WDW_CFG	56	0	1	1	1	0	0	0	0/1	1/0	Read/Write
FS_WD_TOKEN	57	0	1	1	1	0	0	1	0/1	1/0	Read only
FS_WD_ANSWER	58	0	1	1	1	0	1	0	0/1	1/0	Write only
FS_LIMP12_CFG	59	0	1	1	1	0	1	1	0/1	1/0	Read/Write
FS_FS0B_LIMP0_REL	60	0	1	1	1	1	0	0	0/1	1/0	Read/Write
FS_ABIST	61	0	1	1	1	1	0	1	0/1	1/0	Read/Write
Reserved	62	0	1	1	1	1	1	0	0/1	1/0	Reserved
FS_SAFETY_OUTPUTS	63	0	1	1	1	1	1	1	0/1	1/0	Read/Write
FS_SAFETY_FLG	64	1	0	0	0	0	0	0	0/1	1/0	Read/Write
FS_CRC	65	1	0	0	0	0	0	1	0/1	1/0	Read/Write

Readable registers

Table 4. Readable registers

Logic

Register name

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11 Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Main

M_DEV_CFG

CAN_EN

LIN_EN

LDTIM_EN HSD13_EN

HSD24_EN

V2_EN

V1_PNP_EN

ABIST_EN

FCCU_EN

FS0B_EN

LIMP0_EN

V0MON_EN

M_DEV_PROG_ID

FULL_LAYER_REV

METAL_LAYER_REV

PROG_IDH

PROG_IDL

M_GEN_FLAG

0 0

HSxG

SAFETYG

PHYG

WUG

IOTIMG

COMG

VSUPG

VxG

M_STATUS

V1TWARN_S

LPON_S

NORMAL_S

INIT_S

0 WK2_S

WK1_S

HVIO2_S

HVIO1_S

LVI5_S

LVIO4_S

LVIO3_S

V1_MODE

V1_S

V2_S

V3_S

M_SYS_CFG

BAT_FAIL

POR

0 LOCK_INIT

INT_TO_ WUEN

INTB_DUR

MOD_CONF

MOD_EN

M_SYS1_CFG

VBOS2

V1_SW_ ALWAYS_EN

0 LOAD_

OTP_BYP

SLOT_BYP

TSLOT_ DOWN_CFG

DBG_MODE

OTP_MODE

M_REG_CTRL

BUCK_SRHSOFF

BUCK_SRHSON

V2ON_LPON

V3ON_LPON

M_REG_FLG

V0UV_I

V0OV_I

V1TWARN_I

V1TSD_I

V2TSD_I V3TSD_I

V2OL_I

V1UV_I

V2UV_I

V3UV_I

V1OV_I

V2OV_I

V3OV_I

V1OC_I

V2OC_I

V3OC_I

M_REG_MSK

V0UV_M

V0OV_M

V1TWARN_M

V1TSD_M

V2TSD_M V3TSD_M

V2OL_M

V1UV_M

V2UV_M

V3UV_M

V1OV_M

V2OV_M

V3OV_M

V1OC_M

V2OC_M

V3OC_M

M_REG1_FLG

0 0

V1_OCLS_I

M_REG1_MSK

0 0

V1_OCLS_M

M_IO_TIMER_FLG

0 0

LDT_I

LVI5_I

LVIO4_I

LVIO3_I

HVIO2_I

HVIO1_I

WK2_I

WK1_I

M_IO_ TIMER_MSK

0 0

LDT_M

LVI5_M

LVIO4_M

LVIO3_M

HVIO2_M

HVIO1_M

WK2_M

WK1_M

M_VSUP_ COM_FLG

VBOS2 V1SW_S

VBOS_UV 0

I2C_CRC_I

I2C_REQ_I

SPI_CRC_I

SPI_CLK_I

SPI_REQ_I

VSHS_OV_I

VSHS_UV_I

VSUPOV_I

VSUPUV_I

M_VSUP_ COM_MSK

0 0

I2C_CRC_M

I2C_REQ_M

SPI_CRC_M

SPI_CLK_M

SPI_REQ_M

VSHS_OV_M

VSHS_UV_M

VSUPOV_M

VSUPUV_M

M_IOWU_CFG

LVI5_WUCFG

LVIO4_ WUCFG

LVIO3_ WUCFG

HVIO2_DGLT HVIO1_DGLT

WK2_DGLT

WK1_DGLT

HVIO2_WUCFG

HVIO1_WUCFG

WK2_WUCFG

WK1_WUCFG

M_IOWU_EN

LVI5_WUEN

LVIO4_WUEN LVIO3_WUEN

HVIO2_WUEN

HVIO1_WUEN

WK2_WUEN

WK1_WUEN

M_IOWU_FLG

LVI5_WU_I

LVIO4_WU_I

LVIO3_WU_I

HVIO2_ HVIO1_

CYS_RDY CYS_RDY

HVIO2_CYC_S

HVIO1_CYC_S

HVIO2_WU_I

HVIO1_WU_I

WK2_ CYS_RDY

WK1_ CYS_RDY

WK2_CYC_S

WK1_CYC_S

WK2_WU_I

WK1_WU_I

M_WU1_EN

0 0

LDT_WUEN

LIN_WUEN

CAN_WUEN

M_WU1_FLG

0 0

FS_EVT

EXT_ RSTB_WU

WD_OFL_WU

V1_UVLP_WU

INT_TO_WU

GO2 NORMAL_WU

LDT_WU_I

LIN_WU_I

CAN_WU_I

M_TIMER1_CFG

0 0

TIMER1_DLY

TIMER1_ON

TIMER1_PER

M_TIMER2_CFG

0 0

TIMER2_DLY

TIMER2_ON

TIMER2_PER

M_TIMER3_CFG

0 0

TIMER3_DLY

TIMER3_ON

TIMER3_PER

M_PWM1_CFG

PWM1_DLY

PWM1_F

PWM1_DC

M_PWM2_CFG

PWM2_DLY

PWM2_F

PWM2_DC

M_PWM3_CFG

PWM3_DLY

PWM3_F

PWM3_DC

M_TIMER_ PWM_CTRL

0 0

TIM1_EN

TIM2_EN

TIM3_EN

PWM1_EN

PWM2_EN

PWM3_EN

M_CS_CFG

0 0

HS_FLT_ WU_FORCE

HVIO2_HS_SEL

HVIO1_HS_SEL

WK2_HS_SEL

WK1_HS_SEL

M_CS_FLG_MSK

0 0

HVIO2_OL_M

HVIO1_OL_M

WAKE2_OL_M

WAKE1_OL_M

HVIO2_OL_I

HVIO1_OL_I

WAKE2_OL_I

WAKE1_OL_I

M_HSx_SRC_CFG

HS4_SRC_SEL

HS3_SRC_SEL

HS2_SRC_SEL

HS1_SRC_SEL

M_HSx_CTRL

HS_ VSHSUVOV_ REC

HS_ VSHSUV_DIS

HS_ VSHSOV_DIS

0 0

HS4_EN

HS3_EN

HS2_EN

HS1_EN

M_HSx_FLG

HS4_OL_I

HS4_OC_I 0

HS3_OL_I

HS3_OC_I

HS34_TSD_I

HS2_OL_I

HS2_OC_I

HS1_OL_I

HS1_OC_I

HS12_TSD_I

Logic

Register name

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

M_HSx_MSK

HS4_OL_M

HS4_OC_M

HS3_OL_M

HS3_OC_M

HS34_TSD_M

HS2_OL_M

HS2_OC_M

HS1_OL_M

HS1_OC_M

HS12_TSD_M

M_AMUX_CTRL

AMUX_EN

AMUX_DIV

AMUX

M_LDT_CFG1

LDT_AFTER_RUN

M_LDT_CFG2

LDT_WUP_L

M_LDT_CFG3

LDT_WUP_H

M_LDT_CTRL

LDT2LP

LDT_FNCT

LDT_SEL

LDT_MODE

LDT_EN

LDT_RUN

M_CAN

CAN_MODE

CAN_ACTIVE_ MODE_S

CAN_FS_DIS

CAN_ TXD_TO_I

CAN_TSD_I

M_LIN

LIN_MODE

LIN_SLOPE

LIN_FS_DIS

LIN_ VSHSUV_DIS

LIN_SC

LIN_TXD_TO

LIN_SC_I

LIN_TXD_TO_I

LIN_TSD_I

M_CAN_LIN_MSK

LIN_FSM_STATE_S

LIN_SC_M

LIN_TXD_ TO_M

LIN_TSD_M

CAN_FSM_STATE_S

CAN_TXD_ TO_M

CAN_TSD_M

M_MEMORY0

MEMORY0[15]

MEMORY0[14]

MEMORY0[13]

MEMORY0[12]

MEMORY0[11]

MEMORY0[10]

MEMORY0[9]

MEMORY0[8]

MEMORY0[7]

MEMORY0[6]

MEMORY0[5]

MEMORY0[4]

MEMORY0[3]

MEMORY0[2]

MEMORY0[1]

MEMORY0[0]

M_MEMORY1

MEMORY1[15]

MEMORY1[14]

MEMORY1[13]

MEMORY1[12]

MEMORY1[11]

MEMORY1[10]

MEMORY1[9]

MEMORY1[8]

MEMORY1[7]

MEMORY1[6]

MEMORY1[5]

MEMORY1[4]

MEMORY1[3]

MEMORY1[2]

MEMORY1[1]

MEMORY1[0]

Fail- safe

FS_I_OVUV_ CFG1

V1MON_ OV_RSTB_ IMPACT

V1MON_OV_ FS0B_ IMPACT

V1MON_ OV_LIMP0_ IMPACT

V1MON_ UV_RSTB_ IMPACT

V1MON_UV_ FS0B_ IMPACT

V1MON_ UV_LIMP0_ IMPACT

V2MON_OV_ RSTB_IMPACT

V2MON_OV_ FS0B_IMPACT

V2MON_ OV_LIMP0_ IMPACT

V2MON_UV_ RSTB_IMPACT

V2MON_UV_ FS0B_IMPACT

V2MON_ UV_LIMP0_ IMPACT

FS_I_OVUV_ CFG2

V3MON_ OV_RSTB_ IMPACT

V3MON_OV_ FS0B_IMPACT

V3MON_ OV_LIMP0_ IMPACT

V3MON_ UV_RSTB_ IMPACT

V3MON_UV_ FS0B_ IMPACT

V3MON_ UV_LIMP0_ IMPACT

V0MON_OV_ RSTB_IMPACT

V0MON_OV_ FS0B_IMPACT

V0MON_ OV_LIMP0_ IMPACT

V0MON_UV_ RSTB_IMPACT

V0MON_UV_ FS0B_IMPACT

V0MON_ UV_LIMP0_ IMPACT

FS_I_FCCU_CFG

FCCU_CFG

FCCU2_ASSIGN

FCCU12_ FLT_POL

FCCU2_ FLT_POL

FCCU1_ FLT_POL

FCCU2_ RSTB_ IMPACT

FCCU2_FS0 B_ IMPACT

FCCU2_ LIMP0_ IMPACT

FCCU1_ RSTB_ IMPACT

FCCU1_FS0 B_ IMPACT

FCCU1_ LIMP0_ IMPACT

FS_I_FSSM_CFG

EXT_ RSTB_DIS

RSTB8S_DIS

RSTB_DUR

LIMP0_ SC_RSTB_ IMPACT

EXTRSTB_FS0 B_ IMPACT

FS0B_SC_ RSTB_ IMPACT

FLT_ERR_LIMIT

FLT_MID_ RSTB_ IMPACT

FLT_MID_FS0 B_ IMPACT

FLT_MID_ LIMP0_ IMPACT

FLT_ERR_CNT

FS_I_WD_CFG

WD_RSTB_ IMPACT

WD_FS0 B_IMPACT

WD_LIMP0_ IMPACT

WD_DIS_ LPON

WD_RFR_LIMIT

WD_ERR_LIMIT

WD_RFR_CNT

WD_ERR_CNT

FS_WDW_CFG

WDW_ REC_EN

WDW_EN

WDW_PERIOD

WDW_RECOVERY

FS_WD_TOKEN

WD_TOKEN

FS_LIMP12_CFG

LIMP2_DC_CFG

LIMP2_CFG

LIMP1_CFG

FS_FS0B_ LIMP0_REL

FS_ABIST

ABIST_READY

ABIST_DONE

ABIST_ ONGOING

ABIST_V0 MON_DIAG

ABIST_V1 UVLP_DIAG

ABIST_V1 MON_DIAG

ABIST_V2 MON_DIAG

ABIST_V3 MON_DIAG

ABIST_V0MON

ABIST_ V1UVLP

ABIST_V1MON

ABIST_V2MON

ABIST_V3MON

FS_SAFETY_ OUTPUTS

RSTB_EXT

RSTB_EVT

RSTB_DRV

RSTB_SNS

RSTB_DIAG

FS0B_DRV

FS0B_SNS

FS0B_DIAG

LIMP0_DRV

LIMP0_SNS

LIMP0_DIAG

FS_SAFETY_FLG

FCCU12_ ERR_S

FCCU1_ ERR_S

FCCU2_ ERR_S

INIT_CRC_ NOK_M

INIT_CRC_ NOK_I

WD_NOK_M

WD_NOK_I

FCCU12_M

FCCU1_M

FCCU2_M

FCCU12_I

FCCU1_I

FCCU2_I

FCCU1_S

FCCU2_S

FS_CRC

INIT_CRC_FS0 B_ IMPACT

INIT_CRC_ LIMP0_ IMPACT

CRC_VALUE

Writable registers

Table 5. Writable registers

Logic

Register name

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default value

Main

M_SYS_CFG

–

LOCK_INIT

GO2INIT

GO2NORMAL

GO2LPON

GO2LPOFF

INT_TO_ WUEN

INTB_REQ

INTB_DUR

–

MOD_CONF

MOD_EN

OTP fuse

M_SYS1_CFG

–

VBOS2

V1_SW_ ALWAYS_EN

–

LOAD_ OTP_BYP

SLOT_BYP

TSLOT_ DOWN_ CFG

–

SOFTPOR_ REQ

–

DBG_EXIT

–

OTP_EXIT

–

OTP fuse

M_REG_CTRL

–

BUCK_SRHSOFF

BUCK_SRHSON

–

V2ON_LPON

V2EN

V2DIS

V3ON_LPON

V3EN

V3DIS

OTP fuse

M_REG_MSK

V0UV_M

V0OV_M

V1TWARN_M

V1TSD_M

V2TSD_M

V3TSD_M

V2OL_M

V1UV_M

V2UV_M

V3UV_M

V1OV_M

V2OV_M

V3OV_M

V1OC_M

V2OC_M

V3OC_M

0x0000

M_REG1_CTRL

–

V1_OCLS_I

0x0000

M_REG1_MSK

–

V1_OCLS_M

0x0000

M_IO_CTRL

–

HVIO1HI

HVIO1LO

HVIO2HI

HVIO2LO

LVIO3HI

LVIO3LO

LVIO4HI

LVIO4LO

LVO6HI

LVO6LO

0x0000

M_IO_TIMER_MSK

–

LDT_M

LVI5_M

LVIO4_M

LVIO3_M

HVIO2_M

HVIO1_M

–

WK2_M

WK1_M

0x0000

M_VSUP_COM_MSK

–

I2C_CRC_M

I2C_REQ_M

SPI_CRC_M

SPI_CLK_M

SPI_REQ_M

–

VSHS_OV_M

VSHS_UV_M

VSUPOV_M

VSUPUV_M

0x0000

M_IOWU_CFG

LVI5_WUCFG

LVIO4_ WUCFG

LVIO3_ WUCFG

Reserved

HVIO2_DGLT

HVIO1_DGLT

WK2_DGLT

WK1_DGLT

HVIO2_WUCFG

HVIO1_WUCFG

WK2_WUCFG

WK1_WUCFG

0x0005

M_IOWU_EN

–

LVI5_WUEN

LVIO4_WUEN

LVIO3_WUEN

HVIO2_WUEN

HVIO1_WUEN

WK2_WUEN

WK1_WUEN

0x00FF

M_WU1_EN

–

LDT_WUEN

LIN_WUEN

CAN_WUEN

0x000F

M_TIMER1_CFG

–

TIMER1_DLY

TIMER1_ON

TIMER1_PER

0x0000

M_TIMER2_CFG

–

TIMER2_DLY

TIMER2_ON

TIMER2_PER

0x0000

M_TIMER3_CFG

–

TIMER3_DLY

TIMER3_ON

TIMER3_PER

0x0000

M_PWM1_CFG

–

PWM1_DLY

PWM1_F

PWM1_DC

0x0000

M_PWM2_CFG

–

PWM2_DLY

PWM2_F

PWM2_DC

0x0000

M_PWM3_CFG

–

PWM3_DLY

PWM3_F

PWM3_DC

0x0000

M_TIMER_ PWM_CTRL

–

TIM1_EN

TIM2_EN

TIM3_EN

–

PWM1_EN

PWM2_EN

PWM3_EN

0x0000

M_CS_CFG

–

HS_FLT_ WU_FORCE

–

HVIO2_HS_SEL

HVIO1_HS_SEL

WK2_HS_SEL

WK1_HS_SEL

0x0000

M_CS_FLG_MSK

–

HVIO2_OL_M

HVIO1_OL_M

WAKE2_ OL_M

WAKE1_ OL_M

–

0x0000

M_HSx_SRC_CFG

HS4_SRC_SEL

HS3_SRC_SEL

HS2_SRC_SEL

HS1_SRC_SEL

0x0000

M_HSx_CTRL

–

HS_ VSHSUVOV_ REC

HS_ VSHSUV_DIS

HS_ VSHSOV_DIS

–

HS4_EN

–

HS3_EN

–

HS2_EN

–

HS1_EN

0x0000

M_HSx_MSK

–

HS4_OL_M

HS4_OC_M

–

HS3_OL_M

HS3_OC_M

HS34_ TSD_M

–

HS2_OL_M

HS2_OC_M

–

HS1_OL_M

HS1_OC_M

HS12_ TSD_M

0x0000

M_AMUX_CTRL

–

AMUX_EN

AMUX_DIV

–

AMUX

0x0000

M_LDT_CFG1

LDT_AFTER_RUN

0x0000

M_LDT_CFG2

LDT_WUP_L

0x0000

M_LDT_CFG3

–

LDT_WUP_H

0x0000

M_LDT_CTRL

–

LDT2LP

LDT_FNCT

LDT_SEL

LDT_MODE

LDT_EN

–

0x0000

M_CAN

–

CAN_MODE

–

CAN_FS_DIS

–

CAN_ TXD_TO_I

CAN_TSD_I

0x0000

M_LIN

–

LIN_MODE

LIN_SLOPE

LIN_FS_DIS

LIN_ VSHSUV_DIS

LIN_SC

LIN_TXD_TO

–

LIN_SC_I

LIN_TXD_ TO_I

LIN_TSD_I

0x0000

M_CAN_LIN_MSK

–

LIN_FSM_STATE_S

LIN_SC_M

LIN_TXD_ TO_M

LIN_TSD_M

–

CAN_FSM_STATE_S

CAN_TXD_ TO_M

CAN_TSD_M

0x0000

Logic

Register name

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default value

M_MEMORY0

MEMORY0

0x0000

M_MEMORY1

MEMORY1

0x0000

Fail-safe

FS_I_OVUV_CFG1

–

V1MON_ OV_RSTB_ IMPACT

V1MON_ OV_FS0 B_IMPACT

V1MON_ OV_LIMP0_ IMPACT

V1MON_ UV_RSTB_ IMPACT

V1MON_ UV_FS0 B_IMPACT

V1MON_ UV_LIMP0_ IMPACT

–

V2MON_ OV_RSTB_ IMPACT

V2MON_ OV_FS0 B_IMPACT

V2MON_ OV_LIMP0_ IMPACT

V2MON_ UV_RSTB_ IMPACT

V2MON_ UV_FS0 B_IMPACT

V2MON_ UV_LIMP0_ IMPACT

OTP fuse

FS_I_OVUV_CFG2

–

V3MON_ OV_RSTB_ IMPACT

V3MON_ OV_FS0 B_IMPACT

V3MON_ OV_LIMP0_ IMPACT

V3MON_ UV_RSTB_ IMPACT

V3MON_ UV_FS0 B_IMPACT

V3MON_ UV_LIMP0_ IMPACT

–

V0MON_ OV_RSTB_ IMPACT

V0MON_ OV_FS0 B_IMPACT

V0MON_ OV_LIMP0_ IMPACT

V0MON_ UV_RSTB_ IMPACT

V0MON_ UV_FS0 B_IMPACT

V0MON_ UV_LIMP0_ IMPACT

OTP fuse

FS_I_FCCU_CFG

–

FCCU_CFG

FCCU2_ASSIGN

FCCU12_ FLT_POL

FCCU2_ FLT_POL

FCCU1_ FLT_POL

FCCU2_ RSTB_ IMPACT

FCCU2_FS0 B_ IMPACT

FCCU2_ LIMP0_ IMPACT

FCCU1_ RSTB_ IMPACT

FCCU1_FS0 B_ IMPACT

FCCU1_ LIMP0_ IMPACT

0X103F

FS_I_FSSM_CFG

–

EXT_ RSTB_DIS

RSTB8S_DIS

RSTB_DUR

LIMP0_ SC_RSTB_ IMPACT

EXTRSTB_ FS0B_ IMPACT

FS0B_SC_ RSTB_ IMPACT

FLT_ERR_LIMIT

FLT_MID_ RSTB_ IMPACT

FLT_MID_ FS0B_ IMPACT

FLT_MID_ LIMP0_ IMPACT

FLT_ERR_CNT

OTP fuse

FS_I_WD_CFG

–

WD_RSTB_ IMPACT

WD_FS0 B_IMPACT

WD_LIMP0_ IMPACT

WD_DIS_ LPON

WD_RFR_LIMIT

WD_ERR_LIMIT

–

0x7080

FS_WDW_CFG

–

WDW_ REC_EN

WDW_EN

–

WDW_PERIOD

–

WDW_RECOVERY

0x01AB

FS_WD_ANSWER

WD_ANSWER

0x0000

FS_LIMP12_CFG

–

LIMP2_DC_CFG

LIMP2_CFG

LIMP2_REQ

–

LIMP1_CFG

LIMP1_REQ

OTP fuse

FS_FS0B_ LIMP0_REL

RELEASE_FS0B_LIMP0

0x0000

FS_ABIST

–

LAUNCH_ ABIST

CLEAR_ ABIST

–

ABIST_ V0MON

ABIST_ V1UVLP

ABIST_ V1MON

ABIST_ V2MON

ABIST_ V3MON

0x0000

FS_SAFETY_ OUTPUTS

–

RSTB_REQ

–

FS0B_REQ

–

LIMP0_REQ

0x0000

FS_SAFETY_FLG

–

INIT_CRC_ NOK_M

–

WD_NOK_M

–

FCCU12_M

FCCU1_M

FCCU2_M

–

0x0000

FS_CRC

–

INIT_ CRC_REQ

–

INIT_CRC_ FS0B_ IMPACT

INIT_CRC_ LIMP0_ IMPACT

–

CRC_VALUE

0x0000

FS0B and or LIMP0 release calculation procedure

When the fail-safe output FS0B is asserted low by the device because of a fault, or after a power up, some conditions must be validated before allowing the FS0B pin to be released by the device.

These conditions are:

No fault affecting FS0B reported
Fault error counter equal to zero
Device in Normal mode
Device not in Debug mode and not in INIT mode

FS_FS0B_LIMP0_REL register filled with the correct value, depending on current WD_TOKEN[15:0] value as per Table 6. Refer to Table 56 from the FS23 data sheet:

Table 6. FS0B and/or LIMP0 release commands

FS_FS0B_LIMP0_REL[15:0]

B15

B14

B13

B12

B11

B10

Release FS0B

NOT(WD_TOKEN[0:12])

Release LIMP0

NOT(WD_TOKEN[3:15])

Release both FS0B and LIMP0

NOT(WD_TOKEN[0:6])

NOT(WD_TOKEN[10:15])

Watchdog answer procedure

[1] Refer to Section 20.2 from the FS23 data sheet.

The watchdog uses two keys, 0x5AB2 (default value after POR) and 0xD564 to validate the answer. The key is stored in the WD_TOKEN register, and is changed alternatively after each good WD refresh.
The MCU reads the WD_TOKEN register and writes the correct answer (WD_TOKEN register value) through the SPI/I2C in WD_ANSWER register, in the right timing. The WD error counter is incremented when the answer is wrong or not given at the right moment, or not given at all at the end of the watchdog period. Refer to
Table 35 from the FS23 data sheet.

The first good watchdog refresh closes the INIT phase. This first good watchdog refresh is sent by the MCU in less than 256 ms (default period duration). Then the watchdog window is running and the MCU must refresh the watchdog every period.

Table 7. Watchdog answer and refresh validation

SPI / I²C	Window watchdog		Timeout watchdog
SPI / I²C	CLOSED	OPEN	(always open)
BAD key	WD_NOK	WD_NOK	WD_NOK
GOOD key	WD_NOK	WD_OK	WD_OK
None (timeout)	NA	WD_NOK	WD_NOK

SPI/I2C CRC calculation procedure

An 8-bit CRC is required for each write and read SPI command. Computation of a CRC is derived from the mathematics of polynomial division, modulo two.

The CRC parameters are:

Polynomial: x^8+x^4+x^3+x^2+1 (identified by 0x1D)

Seed: 0xFF.

For SPI communication
SPI message construction includes the register address, the read/write bit, data, and CRC. Refer to Tables 65 and 66 from the FS23 data sheet. The bit B32 must be set to 1 to execute a write command, and to 0 to execute a read command.

Table 8. SPI write command message construction

B31

B30

B29

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

MOSI

R/W

Write data [15:8]

MISO

General status flag

B15

B14

B13

B12

B11

B10

MOSI

Write data [7:0]

CRC[7:0]

MISO

CRC[7:0] – response

Table 9. SPI read command message construction

B31

B30

B29

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

MOSI

R/W

0x00

MISO

General status flag

Read data [15:8]

B15

B14

B13

B12

B11

B10

MOSI

0x00

CRC[7:0]

MISO

Read data [7:0]

CRC[7:0] – response

When using SPI communication, the input for CRC calculation is a 24-bit word composed of the register address, the read/write bit, and data.

For I2C communication
I²C message construction includes the device address, read/write bit, register address, data, and CRC. Refer to Table 61 from the FS23 data sheet. The bit B32 must be set to 0 to execute a write command, and to 1 to execute a read command.

Table 10. I²C message construction

B39

B38

B37

B36

B35

B34

B33

B32

ID[6:0]

R/W

Device address

R/W

B31

B30

B29

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

ADR[6:0]

DATA[15:8]

Data MSB

B15

B14

B13

B12

B11

B10

DATA[7:0]

CRC[7:0]

Data LSB

CRC

When using I²C communication, the input for CRC calculation is a 32-bit word composed of device address, read/write bit, register address and data.

INIT CRC calculation procedure

INIT fail-safe registers are protected by a CRC. The same polynomial and seed used for SPI/I²C CRC are necessary to compute this INIT CRC: The polynomial is x^8+x^4+x^3+x^2+1 (identified by 0x1D) with the seed value of 0xFF.

Three steps are required to compute INIT CRC:

Read the FS configuration registers and extract the following bits.

Create the 58-bit word by concatenating the 58 bits.
Compute INIT CRC bitwise using 0x1D polynomial. The figure below gives an example for bitwise CRC computation algorithm.

Revision history

Document ID

Release date

Description

AN14041 v.2.0

23 January 2025

• Global editing for grammar and style.

• Moved document from secure files to public access on nxp.com.

• Section 12 was relocated from the front of this document to the end to conform with NXP’s document content hierarchy.

• Updated Legal information

AN14041 v.1.0

13 September 2023

Initial version

References

Documentation
- [1] FS23 application note – product guidelines, nxp.com
- [2] FS23 data sheet, nxp.com
Software resources
- [3] FS23 AUTOSAR software drivers, nxp.com
- [4] Real-Time Drivers (RTD) general information, nxp.com
Evaluation resources
- [5] FS23 graphical user interface (GUI), revision 3.1.382, nxp.com
- [6] FS23 user manual for socketed / soldered Buck / soldered LDO EVB, nxp.com

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Document information

Information	Content
Keywords	FS2300, FS2320, safety system basis chip, SBC, body and comfort, controller area network (CAN) FD, local interconnect network (LIN)
Abstract	This application note is intended for the engineers involved in software implementation of FS23 fail-safe system basis chips.

CONTACT INFORMATION

For more information, please visit: https://www.nxp.com.
Date of release: 23 January 2025
Document identifier: AN14041

Documents / Resources

NXP FS23 Fail Safe System Basis Chips [pdf] User Guide
FS2300, FS2320, FS23 Fail Safe System Basis Chips, FS23, Fail Safe System Basis Chips, Safe System Basis Chips, Basis Chips, Chips

References

User Manual

NXP FS23 Fail Safe System Basis Chips

Specifications

FAQs

Introduction

FS23 initialization flow chart example

Register mapping of fail-safe logic

Readable registers

Writable registers

FS0B and or LIMP0 release calculation procedure

Watchdog answer procedure

INIT CRC calculation procedure

Legal information

CONTACT INFORMATION

Documents / Resources

References

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