MICROCHIP 1AGL1000 ARM Cortex-M1-enabled IGLOO Development Kit
Introduction
Microchip’s ARM Cortex-M1-enabled IGLOO development kit is an advanced microprocessor-based Field Programmable Gate Array (FPGA) development and evaluation kit. The architecture provides access to a onechip FPGA solution that includes a Cortex-M1 32-bit RISC processor as well as digital peripheral components.
This development kit is ideal for development and verification of embedded microprocessor-based systems or subsystems, product development platforms, and algorithm development.
| Quantity | Description |
| 1 | IGLOO® FPGA M1AGL1000V2-FGG484 development board with built-in FlashPro3 programming circuit |
| 2 | USB A to Mini-B cable |
| 1 | 5V external power supply with international adapters |
| 1 | Quick start card |
Figure 1. Kit Diagram
Hardware FeaturesThe ARM Cortex-M1-enabled IGLOO development kit supports the following features:
- Microchip’s M1AGL1000 IGLOO FPGA
- 1 MB SRAM
- 16 MB Flash
- USB–RS232 converter chip
- GPIO connectors
- Ultra-low power with Flash*Freeze technology
- On-board FlashPro3 circuitry
- 20-Pin Cortex-M1 JTAG connector
- Socketed crystal oscillator
- Push button Power-on Reset circuit
- 10 test LEDs
- 10 test switches
- Expansion connectors
Jumper SettingsThe ARM Cortex-M1-enabled IGLOO development kit comes with the following default jumper settings.
Table 2. Jumper Settings
| Jumper | Development Kit Function | Factory Default |
| JP1 | Provides 3.3V to Prog. USB interface | Installed |
| JP2 | Provides 2.5V to FlashPro3 FPGA | Installed |
| JP3 | Provides 1.2V and/or 1.5V core voltage to IGLOO® FPGA | Installed 2–3 |
| JP4 | Provides 3.3V to FlashPro3 FPGA | Installed |
| JP5 | Selects 1.2V and/or 1.5V core voltage for IGLOO FPGA | Depends on whether FPGA is V2 or V5. V2: Installed 2–3. V5: Not installed (Auto Switch mode) |
| JP6 | Connects 3.3V to Pin 2 of P1 connector | Installed |
| JP7 | Connects VIN (5V) to Pin 1 of P1 connector | Installed |
| JP8 | Connects push button reset to P3 | Not installed |
| JP9 | Connects 3.3V to VPUMP pin on FPGA | Installed 2–3 |
| JP10 | Connects 2.5V to Pin 2 of P2 connector | Installed |
| JP11 | Connects RS232_TX signal from FPGA to RXD input of Serial-to-USB chip | Installed |
| JP12 | Connects RS232_RX signal from FPGA to TXD input of Serial-to-USB chip | Installed |
| JP13 | Connects 3.3V to Bank 3 of IGLOO FPGA | Installed 2–3 |
| JP14 | Connects VIN (5V) to Pin 1 of P2 connector | Installed |
| JP15 | Provides 3.3V to non-FlashPro3 portion of board | Installed |
| JP16 | Connects 3.3V to Bank 0 of IGLOO FPGA | Installed 2–3 |
| JP17 | Connects 2.5V to Bank 1 of IGLOO FPGA | Installed 2–3 |
| JP18 | Connects 3.3V to Bank 2 of IGLOO FPGA | Current is measured at this point |
| JP19 | Connects 3.3V to IGLOO FPGA | Current is measured at this point |
| JP20 | Supplies voltage to PLL | 1–2 connects core voltage to PLL 2–3 shorts VCCPLF to GND to disable PLL and insure it does not consume power |
| JP21 | Selects source of Flash*Freeze pin. | 1–2 connects GPIOB_0 to FF Pin. 2–3 connects push button circuit with RC and Schmitt trigger buffer |
| JP22 | Selects input power (5V) to the main board logic | Factory installed between Pins 1 and 4 to select power from 2.1 mm external power supply connector. Other jumper positions have been removed and are no longer supported |
| JP23 | Connects VIIN (5V) to Pin 1 of P5 connector | Current is measured at this point |
| JP24 | Connects 3.3V to Pin 2 of P5 connector | Current is measured at this point |
Running the Demo
The M1AGL development board is shipped with the pre-programmed demo loaded in the M1AGL FPGA. The embedded software image of the traffic light controller is also loaded into external Flash. When you first power up the M1AGL development board, the traffic light demo starts executing and the timed sequence of LEDs illuminates on U8. Instructions on how to run the demo design are available in the ARM Cortex-M1-enabled IGLOO development kit user guide. For more information, see Documentation Resources.
Software and Licensing
The Libero® SoC Design Suite offers high productivity with its comprehensive, easy-to-learn, easy-to-adopt development tools for designing with Microchips’s low power Flash FPGAs and SoC. The suite integrates industry standard Synopsys Synplify Pro® synthesis and Mentor Graphics ModelSim® simulation with best-in-class constraints management and debug capabilities.
Download the latest Libero SoC release from Libero SoC v12.0 or later website.
Generate a Libero Silver license for your kit at www.microchipdirect.com/fpga-software-products.
Documentation Resources
For more information about the ARM Cortex-M1-enabled IGLOO development kit, including user guides, tutorials, and design examples, see the documentation at www.microchip.com/en-us/development-tool/M1AGL1000-DEVKIT#Documentation.
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Documents / Resources
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MICROCHIP 1AGL1000 ARM Cortex-M1-enabled IGLOO Development Kit [pdf] Instruction Manual M1AGL1000-DEV-KIT, 1AGL1000 ARM Cortex-M1-enabled IGLOO Development Kit, ARM Cortex-M1-enabled IGLOO Development Kit, Cortex-M1-enabled IGLOO Development Kit, IGLOO Development Kit, Development Kit |