MICROCHIP 1AGL1000 ARM Cortex-M1-enabled IGLOO Development Kit
Taw qhia
Microchip’s ARM Cortex-M1-enabled IGLOO development kit is an advanced microprocessor-based Field Programmable Gate Array (FPGA) development and evaluation kit. The architecture provides access to a onechip FPGA solution that includes a Cortex-M1 32-bit RISC processor as well as digital peripheral components.
This development kit is ideal for development and verification of embedded microprocessor-based systems or subsystems, product development platforms, and algorithm development.
| Ntau | Kev piav qhia |
| 1 | IGLOO® FPGA M1AGL1000V2-FGG484 development board with built-in FlashPro3 programming circuit |
| 2 | USB A rau Mini-B cable |
| 1 | 5V sab nraud fais fab mov nrog thoob ntiaj teb adapters |
| 1 | Daim npav pib nrawm |
Daim duab 1. Daim duab kos duab
Kho vajtse ntaThe ARM Cortex-M1-enabled IGLOO development kit supports the following features:
- Microchip’s M1AGL1000 IGLOO FPGA
- 1 MB SRAM
- 16 MB Flash
- USB–RS232 converter chip
- GPIO connectors
- Ultra-low power with Flash*Freeze technology
- On-board FlashPro3 circuitry
- 20-Pin Cortex-M1 JTAG txuas
- Socketed crystal oscillator
- Push button Power-on Reset circuit
- 10 kuaj LEDs
- 10 test switches
- Expansion connectors
Jumper SettingsThe ARM Cortex-M1-enabled IGLOO development kit comes with the following default jumper settings.
Table 2. Jumper Settings
| Jumper | Development Kit Function | Factory Default |
| jp1 ua | Provides 3.3V to Prog. USB interface | Nruab |
| jp2 ua | Muab 2.5V rau FlashPro3 FPGA | Nruab |
| jp3 ua | Muab 1.2V thiab / lossis 1.5V core voltage to IGLOO® FPGA | Installed 2–3 |
| jp4 ua | Muab 3.3V rau FlashPro3 FPGA | Nruab |
| jp5 ua | Xaiv 1.2V thiab / lossis 1.5V core voltage for IGLOO FPGA | Depends on whether FPGA is V2 or V5. V2: Installed 2–3. V5: Not installed (Auto Switch mode) |
| jp6 ua | Txuas 3.3V rau Pin 2 ntawm P1 connector | Nruab |
| jp7 ua | Txuas VIN (5V) rau Pin 1 ntawm P1 connector | Nruab |
| jp8 ua | Txuas lub laub khawm pib dua rau P3 | Tsis ntsia |
| jp9 ua | Txuas 3.3V rau VPUMP tus pin ntawm FPGA | Installed 2–3 |
| jp10 ua | Txuas 2.5V rau Pin 2 ntawm P2 connector | Nruab |
| jp11 ua | Txuas RS232_TX teeb liab los ntawm FPGA rau RXD cov tswv yim ntawm Serial-rau-USB nti | Nruab |
| jp12 ua | Txuas RS232_RX teeb liab los ntawm FPGA rau TXD input ntawm Serial-rau-USB nti | Nruab |
| jp13 ua | Txuas 3.3V rau Bank 3 ntawm IGLOO FPGA | Installed 2–3 |
| jp14 ua | Txuas VIN (5V) rau Pin 1 ntawm P2 connector | Nruab |
| jp15 ua | Muab 3.3V rau cov uas tsis yog-FlashPro3 feem ntawm lub rooj tsavxwm | Nruab |
| jp16 ua | Txuas 3.3V rau Bank 0 ntawm IGLOO FPGA | Installed 2–3 |
| jp17 ua | Txuas 2.5V rau Bank 1 ntawm IGLOO FPGA | Installed 2–3 |
| jp18 ua | Txuas 3.3V rau Bank 2 ntawm IGLOO FPGA | Tam sim no ntsuas ntawm qhov no |
| jp19 ua | Txuas 3.3V rau IGLOO FPGA | Tam sim no ntsuas ntawm qhov no |
| jp20 ua | Cov khoom siv voltage rau PLL | 1–2 connects core voltage to PLL 2–3 shorts VCCPLF to GND to disable PLL and insure it does not consume power |
| jp21 ua | Xaiv qhov chaw ntawm Flash * Freeze tus pin. | 1–2 connects GPIOB_0 to FF Pin. 2–3 connects push button circuit with RC and Schmitt trigger buffer |
| jp22 ua | Xaiv lub zog hluav taws xob (5V) rau lub rooj tsav xwm loj | Factory ntsia nruab nrab ntawm Pins 1 thiab 4 los xaiv lub hwj chim los ntawm 2.1 hli sab nraud fais fab mov connector. Lwm txoj haujlwm jumper tau raug tshem tawm thiab tsis muaj kev txhawb nqa ntxiv lawm |
| jp23 ua | Connects VIIN (5V) to Pin 1 of P5 connector | Tam sim no ntsuas ntawm qhov no |
| jp24 ua | Txuas 3.3V rau Pin 2 ntawm P5 connector | Tam sim no ntsuas ntawm qhov no |
Si laim Demo
M1AGL kev txhim kho pawg thawj coj tau xa nrog cov kev ua haujlwm ua ntej demo loaded hauv M1AGL FPGA. Cov duab kos software ntawm lub teeb tswj lub teeb kuj tseem thauj khoom mus rau sab nraud Flash. Thaum koj thawj lub zog ntawm M1AGL kev txhim kho pawg thawj coj saib, lub teeb pom kev ua haujlwm pib pib ua haujlwm thiab lub sijhawm ua ntu zus ntawm LEDs illuminates ntawm U8. Cov lus qhia yuav ua li cas khiav tus qauv tsim muaj nyob rau hauv ARM Cortex-M1-enabled IGLOO cov khoom siv txhim kho cov neeg siv. Yog xav paub ntxiv, saib Cov Ntaub Ntawv Cov Ntaub Ntawv.
Software thiab Licensing
Libero® SoC Design Suite muaj cov khoom tsim tau zoo nrog nws cov kev paub, yooj yim-rau-kawm, yooj yim-rau-coj cov cuab yeej tsim kho rau kev tsim nrog Microchips lub zog qis Flash FPGAs thiab SoC. Cov suite koom ua ke nrog kev lag luam tus qauv Synopsys Synplify Pro® synthesis thiab Mentor Graphics ModelSim® simulation nrog cov kev txwv zoo tshaj plaws hauv chav kawm kev tswj hwm thiab kev paub daws teeb meem.
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Cov ntaub ntawv pov thawj
For more information about the ARM Cortex-M1-enabled IGLOO development kit, including user guides, tutorials, and design examples, saib cov ntaub ntawv ntawm www.microchip.com/en-us/development-tool/M1AGL1000-DEVKIT#Documentation.
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MICROCHIP 1AGL1000 ARM Cortex-M1-enabled IGLOO Development Kit [ua pdf] Phau ntawv qhia M1AGL1000-DEV-KIT, 1AGL1000 ARM Cortex-M1-enabled IGLOO Development Kit, ARM Cortex-M1-enabled IGLOO Development Kit, Cortex-M1-enabled IGLOO Development Kit, IGLOO Development Kit, Development Kit |