Setting CSV parameters

About this document

Scope and purpose: The Clock Supervision (CSV) feature in TRAVEOTM T2G family enables you to check the frequency of the monitored clock to ensure that it is within the allowed frequency window. To understand the functionality described and terminology used in this guide, see the “Clocking System” chapter in the architecture technical reference manual (TRM). This guide describes how to calculate and set the CSV parameters using the CSV calculator.

Intended audience: This document is intended for anyone using the TRAVEOTM T2G family to determine the CSV parameters.

1 Overview

Figure 1 shows the signal example of the CSV. The diagram illustrates a signal timing diagram for Clock Supervision (CSV) operation, featuring a 'Monitored Clock' and a 'Reference Clock'. Key timing points are marked: 'Period' (representing the monitored clock count), 'Target' (representing the reference clock count), 'Monitor Event' (a point in time related to the monitored clock), and 'Lower Limit' and 'Upper Limit' (thresholds for the Monitor Event). The diagram visually represents how the Monitor Event is compared against these limits to detect frequency deviations.

The basic operation principle of the CSV circuit is as follows:

• Period is the monitored clock count while ‘Target' is the reference clock count. In an ideal case, these two are the same.
• The monitored clock generates a Monitor event (Period), and the reference clock generates Lower and Upper limits.
• The Monitor event is compared against the Lower and Upper limits.
• An error is reported if the Monitor event ≤ Lower limit, or Monitor event > Upper limit.

2 Parameters related to CSV

2.1 Check the clock specifications

Check the following clock specifications:

• Reference clock frequency and tolerance (integer %)
• Monitored clock frequency and required tolerance (integer %)

The required monitored clock tolerance should be equal to or larger than the reference clock tolerance.

Notes on monitored clock types:

• FLL, PLL200, or PLL400: Set the nominal frequency (Fc) of the configured VCO or PLL400 output for fractional mode or SSCG in down spread mode to the monitor clock frequency. Refer to the “Root and intermediate clocks" table in the TRAVEOTM T2G cluster device datasheet or SID341/SID341A(4)/SID341B(4)/SID351 in the TRAVEOTM T2G body device datasheet for maximum frequency. Note that the maximum frequency is reduced in PLL400 with SSCG/fractional mode.
• PLL200 or PLL400 without SSCG/fractional mode: Set '3 or more' for the PLL jitter consideration in the monitored clock tolerance.
• PLL400 with SSCG/fractional mode: Set '5 or more' for the PLL jitter consideration, as shown in Figure 2, to the monitored clock tolerance.
• PLL400 with SSCG mode: Set the modulation depth corresponding to your configuration.

Figure 2 is a graph illustrating 'PLL clock frequency tolerance' over 'Time'. The Y-axis represents 'Frequency', showing a nominal frequency 'Fc' with upper and lower bounds indicating frequency tolerance. Jitter is depicted as variations around Fc, and 'Modulation depth (ΔF)' and 'Modulation rate (1/Modulation_frequency)' are also indicated.

2.2 Determine the target

Check the minimum Target with Equation 1 using the CSV calculator.

Equation 1: Min Target = 200 / Reference clock tolerance

Determine and enter the Target highlighted in orange of the CSV calculator referring the calculated minimum Target. The Target should be equal to or greater than the minimum Target. If the Target is smaller than the minimum Target, the ‘Value' cell of the Target will be highlighted in red.

2.3 Calculate the lower and upper limit

Calculate the Lower limit with Equation 2 using the CSV calculator.

Equation 2: Lower limit = Period × (1 + (Reference clock frequency / Monitored clock frequency) × (1 - Reference clock tolerance / 100))

Calculate the Upper limit with Equation 3 using the CSV calculator.

Equation 3: Upper limit = Period × (1 + (Reference clock frequency / Monitored clock frequency) × (1 + Reference clock tolerance / 100))

Only for PLL400 SSCG mode:

Upper limit = Period × (1 + (Reference clock frequency / Monitored clock frequency) × (1 + (Reference clock tolerance + Modulation depth) / 100))

2.4 Calculate the period

Calculate the Period with Equation 4 using the CSV calculator. If the Period value is less than one, increase the Target value. To avoid the round off error of the Period value, the value should be as close to an integral value as possible and not a decimal value. This can be achieved by adjusting Target value.

Equation 4: Period = Target × (Monitored clock frequency / Reference clock frequency)

2.5 Calculate the startup delay

Calculate the Startup Delay with Equation 5 using the CSV calculator. In the case of WCO, the startup time is unused (0). CSV should be enabled after WCO is started (BACKUP_STATUS.WCO_OK = 1).

Equation 5: Startup Delay = Maximum startup time for monitored clock × Reference clock frequency × (1 + Reference clock tolerance / 100)

2.6 Check the values for CSV register settings

You should set the values obtained by subtracting 1 from the above calculated values in the CSV register. The CSV calculator calculates these CSV register values based on the above parameters and automatically displays the values in cells highlighted in green. If the Value is larger than 65535, the cell will be highlighted in red.

When determining the final CSV parameters, evaluate the CSV function sufficiently in the user system environment.

3 CSV calculator example

3.1 PLL200 example

This section shows the CSV calculator example of PLL200 with the following parameters:

• Reference clock frequency: 8 MHz (ECO)
• Reference clock tolerance: 1 % (ECO)
• Target: 200 (use the same value as the calculated minimum Target)
• Monitored clock frequency: 50 MHz (CSV_HF0/PLL200)
• Monitored clock tolerance: 3 % (CSV_HF0/PLL200)
• Monitored clock tolerance (Modulation depth): 0% (CSV_HF0/PLL200)
• Startup time for Monitored clock: 35 µs (PLL200)

Enter the above parameters in the cells, highlighted in orange, of the CSV calculator.

The CSV Calculator calculates the CSV register values based on the entered parameters and automatically displays the values in cells highlighted in green.

3.2 PLL400 example

This section shows the CSV calculator example of PLL400 with the following parameters:

• Reference clock frequency: 8 MHz (ECO)
• Reference clock tolerance: 1 % (ECO)
• Target: 400 (use the twice value of the calculated minimum Target)
• Monitored clock frequency: 200 MHz (CSV_HF1/PLL400 with SSCG)
• Monitored clock tolerance: 5 % (CSV_HF1/PLL400 with SSCG)
• Monitored clock tolerance (Modulation depth): 3 %
• Startup time for Monitored clock: 50 µs (PLL400)

Enter the above parameters in the cells, highlighted in orange, of the CSV calculator.

The CSV calculator calculates the CSV register values based on the entered parameters and automatically displays the values in cells highlighted in green.

3.3 FLL example

This section shows the CSV calculator example of FLL with the following parameters:

• Reference clock frequency: 8 MHz (IMO)
• Reference clock tolerance: 4 % (IMO)
• Target: 50 (use the same value as the calculated minimum Target)
• Monitored clock frequency: 100 MHz (CSV_HF0/FLL)
• Monitored clock tolerance: 5 % (Reference clock tolerance + SID352)
• Monitored clock tolerance (Modulation depth): 0 % (CSV_HF0/FLL)
• Startup time for Monitored clock: 5 µs (FLL)

Enter the above parameters in the cells, highlighted in orange, of the CSV calculator.

The CSV calculator calculates the CSV register values based on the entered parameters and automatically displays the values in cells highlighted in green.

References

The following are the TRAVEOTM T2G family series datasheets and technical reference manuals. Contact Technical Support to obtain these documents.

1. Device datasheets
   • CYT2B6 datasheet 32-bit Arm® Cortex®-M4F microcontroller TRAVEOTM T2G family
   • CYT2B7 datasheet 32-bit Arm® Cortex®-M4F microcontroller TRAVEOTM T2G family
   • CYT2B9 datasheet 32-bit Arm® Cortex®-M4F microcontroller TRAVEOTM T2G family
   • CYT4BF datasheet 32-bit Arm® Cortex®-M7 microcontroller TRAVEOTM T2G family
   • CYT3BB/4BB datasheet 32-bit Arm® Cortex®-M7 microcontroller TRAVEOTM T2G family
   • CYT4DN datasheet 32-bit Arm® Cortex®-M7 microcontroller TRAVEOTM T2G family (Doc No. 002-24601)
   • CYT3DL datasheet 32-bit Arm® Cortex®-M7 microcontroller TRAVEOTM T2G family (Doc No. 002-27763)
   • CYT2CL datasheet 32-bit Arm® Cortex®-M4F microcontroller TRAVEOTM T2G family (Doc No. 002-32508)
2. Body controller entry family TRMs
   • TRAVEOTM T2G automotive body controller entry family architecture technical reference manual (TRM)
   • TRAVEOTM T2G automotive body controller entry registers technical reference manual (TRM) for CYT2B7
   • TRAVEOTM T2G automotive body controller entry registers technical reference manual (TRM) for CYT2B9
3. Body controller high family TRMs
   • TRAVEOTM T2G automotive body controller high family architecture technical reference manual (TRM)
   • TRAVEOTM T2G automotive body controller high registers technical reference manual (TRM) for CYT4BF
   • TRAVEOTM T2G automotive body controller high registers technical reference manual (TRM) for CYT3BB/4BB
4. Cluster 2D family TRMs
   • TRAVEOTM T2G automotive cluster 2D family architecture technical reference manual (TRM) (Doc No. 002-25800)
   • TRAVEOTM T2G automotive cluster 2D registers technical reference manual (TRM) for CYT4DN (Doc No. 002-25923)
   • TRAVEOTM T2G automotive cluster 2D registers technical reference manual (TRM) for CYT3DL (Doc No. 002-29854)
5. Cluster entry family TRMs
   • TRAVEOTM T2G automotive cluster entry family architecture technical reference manual (TRM) (Doc No. 002-33175)
   • TRAVEOTM T2G automotive cluster entry registers technical reference manual (TRM) for CYT4DN (Doc No. 002-33404)

Revision history

Trademarks and Notices

All referenced product or service names and trademarks are the property of their respective owners.

Edition: 2021-11-04

Published by: Infineon Technologies AG, 81726 Munich, Germany

© 2021 Infineon Technologies AG. All Rights Reserved.

Document reference: 002-32474 Rev.*B

Do you have a question about this document? Go to www.cypress.com/support

IMPORTANT NOTICE

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie").

With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party.

In addition, any information given in this document is subject to customer's compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications.

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application.

For further information

For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office (www.infineon.com).

WARNINGS

Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office.

Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies' products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.