CMT2219A: 300 – 960 MHz OOK/(G)FSK Receiver

Features

• Optional Chip Feature Configuration Schemes:
• On-Line Registers Configuration
• Off-Line EEPROM Programming
• Frequency Range: 300 to 960 MHz
• FSK, GFSK and OOK Demodulation
• Symbol Rate: 0.1 to 100 ksps
• Sensitivity: -109 dBm @ 9.6 ksps, FSK, 868.35 MHz
• 4-wire SPI Interface
• Direct, Buffer and Packet Mode Supported
• Configurable Data Handler and 32-Byte FIFO
• Manchester Decoding and Data De-Whitening
• Supply Voltage: 1.8 to 3.6 V
• Low Power Consumption: 5.7 mA
• Low Sleep Current: 60 nA (Sleep Timer Off), 440 nA (Sleep Timer On)
• RoHS Compliant
• 16-pin QFN 3x3 Package

Applications

• Low-Cost Consumer Electronics Applications
• Home and Building Automation
• Infrared Receiver Replacements
• Industrial Monitoring and Controls
• Remote Automated Meter Reading
• Remote Lighting Control System
• Wireless Alarm and Security Systems
• Remote Keyless Entry (RKE)

Ordering Information

More Ordering Info: See Section 6.

Description

The CMT2219A is an ultra low power, high performance, OOK and (G)FSK receiver for various 300 to 960 MHz wireless applications. It is part of the CMOSTEK NextGenRF™ family, which includes a complete line of transmitters, receivers and transceivers. All features can be configured either by off-line EEPROM programming or on-line registers writing. The configuration file to be written into the registers is generated by the smart RFPDK. The CMT2219A operates from a supply voltage of 1.8 V to 3.6 V, consuming only 5.7 mA current while achieving -109 dBm receiving sensitivity (FSK, 9.6 ksps symbol rate, 868.35 MHz), and only 60 nA sleep current for superior battery life. The device supports packet handling, 32-byte FIFO, Manchester decoding and data de-whitening for received data processing. It can also output power-on reset, system clock, and 2 configurable interrupts. The CMT2219A receiver together with the CMT211xA transmitter enables a powerful RF link.

Pin Assignments

The CMT2219A is a 16-pin QFN package. The pinout is as follows:

• Pin 1: CSB (SPI Chip Select Input)
• Pin 2: SDA (SPI Data Input/Output)
• Pin 3: SCL (SPI Clock Input)
• Pin 4: FCSB (SPI FIFO Select Input)
• Pin 5: GPO4 (General Purpose Output)
• Pin 6: GPO3 (General Purpose Output)
• Pin 7: XOUT (Crystal Oscillator Output)
• Pin 8: XIN (Crystal Oscillator Input / External Clock Input)
• Pin 9: GPO2 (General Purpose Output)
• Pin 10: GPO1 (General Purpose Output)
• Pin 11: VCOP (VCO Tank Connection)
• Pin 12: VCON (VCO Tank Connection)
• Pin 13, 15: GND (Ground)
• Pin 14: RFIN (RF Signal Input)
• Pin 16: VDD (Power Supply Input)

A diagram shows the top view of the 16-pin QFN package with pins numbered 1 through 16.

Typical Application Schematic

The typical application schematic shows the CMT2219A integrated into a circuit with an antenna, an inductor (L1, L2), capacitors (C0, C1, C2, C3), a crystal (X1), and a microcontroller (U2). Connector J1 is indicated for EEPROM programming.

The Bill of Materials (BOM) for the typical application includes the CMT2219A receiver (CMOSTEK), an MCU (EPSON), a 26 MHz crystal (EPSON), inductors (Murata LQG18), and capacitors (Murata GRM15).

Abbreviations

The document provides a comprehensive list of abbreviations used, such as ADC, AFC, AGC, BER, BOM, FIFO, FSK, GFSK, LNA, MCU, OOK, PCB, RF, SPI, SR, STBY, etc.

Electrical Characteristics

Recommended Operation Conditions:

Absolute Maximum Ratings:

Caution: ESD sensitive device. Precautions should be used when handling the device to prevent permanent damage.

Receiver Specifications

Key specifications include:

• Frequency Range: 300 to 960 MHz
• Symbol Rate: 0.1 to 40 ksps (OOK), 0.1 to 100 ksps ((G)FSK)
• Sensitivity (e.g., -109 dBm for 9.6 ksps FSK at 868.35 MHz)
• Working Current: 3.5 to 5.9 mA (typical, depending on mode and frequency)
• Sleep Current: 60 nA (Sleep Timer Off), 440 nA (Sleep Timer On)
• Receiver Bandwidth: 50 to 500 kHz
• Receiver Start-up Time: 7.3 ms (Always Receive Mode)
• Receiver Wake-up Time: 0.61 ms (Duty-Cycle Receive Mode)

Crystal Oscillator

The crystal oscillator requires a 26 MHz crystal. Specifications include tolerance, load capacitance, and ESR. The startup time is also provided.

LPOSC (Low Power Oscillator)

An internal 1 kHz low power oscillator is integrated for the sleep timer. It is automatically calibrated to maintain frequency tolerance.

Pin Descriptions

Detailed descriptions for each of the 16 pins are provided, including their name, I/O type, and function. Pins include SPI interface signals (CSB, SDA, SCL, FCSB), General Purpose Outputs (GPO1-GPO4), oscillator pins (XIN, XOUT), RF input (RFIN), power supply (VDD, GND), and VCO connections (VCOP, VCON).

Typical Performance Characteristics

The datasheet includes several graphs illustrating performance:

• Current vs. Voltage: Shows current consumption across different supply voltages for 433.92 MHz and 868.35 MHz, OOK modulation, and 1 ksps symbol rate.
• Current vs. Temperature: Displays current consumption across various temperatures for different voltage and frequency settings with FSK modulation at 1 ksps.
• Sensitivity vs. Supply Voltage: Illustrates receiver sensitivity across supply voltages for 433.92 MHz and 868.35 MHz, OOK modulation, and 1 ksps symbol rate with 0.1% BER.
• Sensitivity vs. Temperature: Shows receiver sensitivity across temperatures for 433.92 MHz and 868.35 MHz, FSK modulation, 3.3V, 1 ksps symbol rate, and 0.1% BER.
• Sensitivity vs. Symbol Rate: Depicts receiver sensitivity as a function of symbol rate for 433.92 MHz and 868.35 MHz, OOK modulation, 3.3V, and 0.1% BER.
• Sensitivity vs. BER: Illustrates receiver sensitivity versus Bit Error Rate for 433.92 MHz and 868.35 MHz, 3.3V, and 1 ksps symbol rate.

Functional Descriptions

Overview: The CMT2219A is a low-power, high-performance RF receiver for 300-960 MHz wireless applications, part of the CMOSTEK NextGenRF™ family. It uses a low-IF architecture with minimal external components. The RF signal is amplified, down-converted, filtered, and then processed by a digital demodulator. It features a fractional-N PLL synthesizer, automatic calibration, packet handling, 32-byte FIFO, Manchester decoding, and data de-whitening. The device supports configuration via EEPROM or on-line registers using SPI.

Modulation, Frequency and Symbol Rate: Supports OOK (0.1-40 ksps) and (G)FSK (0.1-100 ksps) demodulation across 300-960 MHz. The frequency resolution is 24.8 Hz.

Embedded EEPROM and RFPDK: The RFPDK (RF Products Development Kit) is a PC application for configuring the device. Configurations can be burned to the embedded EEPROM (off-line) or exported as HEX files for on-line configuration via MCU. The process involves connecting a USB programmer to the PC and device, setting parameters in RFPDK, and burning the configuration.

Configurable Options: A wide range of options are available for customization via RFPDK's Basic and Advanced modes, including frequency, demodulation type, symbol rate, squelch threshold, crystal tolerance, operation mode (Active/Passive), sleep timer, receive timer, system clock output, wake-on-radio, demodulation methods (OOK), RSSI peak drop settings, (G)FSK deviation, sync clock type, data representation, thresholds, AFC, data modes (Direct, Buffer, Packet), packet types (Fixed/Variable Length), FIFO settings, preamble, sync word, Node ID, data length, and CRC options.

Internal Blocks Description:

• RF Front-end and AGC: Includes LNA, I/Q mixer, and power detector, with an AGC loop for optimal linearity and sensitivity.
• IF Filter: A 3rd-order band-pass image rejection filter with dynamically adjusted center frequency.
• RSSI: Receives signal strength indication via I/Q Log amplifiers, providing DC voltages proportional to input signal level.
• SAR ADC: An 8-bit ADC digitizes RSSI output for FSK/GFSK demodulator control or OOK demodulation.
• Crystal Oscillator: Provides reference clock for PLL synthesizer and digital blocks, requiring a 26 MHz crystal.
• Frequency Synthesizer: Fractional-N synthesizer generating LO frequency for the mixer, covering 300-960 MHz with 24.8 Hz resolution.
• LPOSC: An internal 1 kHz low power oscillator for the sleep timer, with automatic calibration.
• OOK Demodulation: Compares RSSI to a threshold, supporting Fixed TH and Peak TH methods.
• (G)FSK Demodulation: High-performance demodulation supporting various deviations. Modulation index and frequency error are key parameters.

SPI Interface

The device communicates via a 4-wire SPI interface. Active-low CSB and FCSB signals are used for register and FIFO access, respectively. SCL is the serial clock, and SDA is the bi-directional data pin. Data is transmitted MSB first.

Register Read & Write Operation: Involves sending an r/w bit followed by a 7-bit register address. Timing requirements for CSB and SCL are specified.

FIFO Read Operation: The internal read pointer increments after each byte. FCSB must be low for at least 1 SCL cycle before the first rising edge of SCL. Timing for subsequent reads is also detailed.

Timing diagrams illustrate SPI read, write, and FIFO read operations.

Operation States, Timing and Power

Power-Up Sequence: Starts with a power-on reset (POR), followed by crystal oscillation stabilization, internal block calibration, and finally entering the SLEEP state. The total time is approximately 9.5 ms.

Operating States: The device supports six states: PUP (Power Up), SLEEP, STBY (Standby), TUNE, RX (Receive), and EEPROM. Transitions between states are controlled by MCU commands via registers.

• PUP: Initial power-up sequence.
• SLEEP: Low power state, SPI accessible, FIFO not accessible. Sleep current < 60 nA.
• STBY: Crystal oscillator on, synthesizer/RF front-end off. Power consumption ~520 uA.
• TUNE: Frequency synthesizer tuned. Power consumption ~2 mA.
• RX: All blocks active for receiving data. Power consumption varies.
• EEPROM: Access to EEPROM User Space.

A state machine diagram shows transitions between these states. A timing diagram illustrates power consumption during a typical receive cycle from SLEEP to RX state.

GPOs and Interrupts

Four General Purpose Outputs (GPOs) are available, configurable for various functions like data output (DOUT), clock output (DCLK, CLKO), reset signal (nRSTO), or interrupt signals (INT1, INT2).

Two interrupt outputs (INT1, INT2) respond to multiple sources, including RSSI valid, preamble detection, sync word detection, Node ID, CRC validation, packet done, sleep timer timeout, receive timer timeout, FIFO status (not empty, threshold, full, overflow), and RSSI indication. Interrupts can be cleared by the MCU.

A diagram shows the multiplexing and control of interrupts to INT1 and assignment to GPOs.

Data Handling

The device supports three data access modes: Direct, Buffer, and Packet mode, utilizing a packet handler and a 32-byte FIFO.

• Direct Mode: Demodulated data is output directly via DOUT, with sync clock on DCLK. Preamble and sync word detection interrupts are optional.
• Buffer Mode: Data is shifted into the FIFO after sync word detection. MCU reads FIFO via SPI. Preamble detection is optional, sync word detection is mandatory.
• Packet Mode: Data is first decoded by the packet handler, then filled into the FIFO. Supports various decoding and validation options.

Packet types include Fixed Length and Variable Length, with configurable preamble, sync word, Node ID, data, and CRC fields. Diagrams illustrate packet structures.

Receiver Operation Control

Various operating behavior options are available, primarily for power saving. Features include a sleep timer, receive timer, and wake-on-radio (WOR) operation. Details are in "AN138 CMT2219A Configuration Guideline".

User Registers

Registers are organized into two banks: Configuration Bank (0x00-0x3D) and Control Bank. Configuration registers store device features and are typically programmed once via RFPDK. Control registers manage GPO/interrupts, RSSI reading, function enabling, operation modes, and soft reset.

Key registers include INT_EN (interrupt enable), IO_SEL (GPO signal selection), INTCTL_A/B/C/D (interrupt control), RSSI (RSSI value), FUNC_EN (function enable), OP_CTRL (operation status/switch), and SOFTRST (soft reset).

Ordering Information

The CMT2219A-EQR is available for 300-960 MHz OOK/(G)FSK reception, in a QFN16 (3x3) package, tape & reel option, for an operating condition of 1.8 to 3.6 V, -40 to 85 °C, with a Minimum Order Quantity (MOQ) of 5,000 pieces.

Package Outline

The device is supplied in a 16-pin QFN 3x3 package. Dimensions for the package outline are provided in a table, including values for A, A1, b, c, D, D2, e, E, E2, and L in millimeters.

Top Marking

The top marking for the CMT2219A includes the part number "219A", an internal tracking number "1234", and a date code "YWW" (last digit of mold year and workweek). The marking method is laser, with a specified font size and pin 1 indicator.

Other Documentations

Related documentation includes:

• AN103: CMT211xA-221xA One-Way RF Link Development Kits Users Guide
• AN107: CMT221x Schematic and PCB Layout Design Guideline
• AN138: CMT2219A Configuration Guideline

Document Change List

The document history tracks revisions from 0.2 to 1.3, detailing changes such as initial release, table updates, typo corrections, and VCO inductor value changes.

Contact Information

Shenzhen Hope Microelectronics Co., Ltd. is located in Shenzhen, China. Contact details include Tel: +86-755-82973805 / 4001-189-180, Fax: +86-755-82973550, Sales: sales@hoperf.com, and Website: www.hoperf.com.

Copyright © Shenzhen Hope Microelectronics Co., Ltd. All rights reserved.

The information provided is believed to be accurate but subject to change without notice. HOPERF products are not authorized for use in critical components in life support devices without express written approval.