Silicon Labs EFR32BG26 Errata

2.1 DCDC_E304 - Leakage Current at High Temperatures Exceeds PFM Mode Maximum Output Current

Description of Errata

By default, the DCDC operates in PFM mode, which supports up to 60 mA of output current. When additional current is required, 120 mA is available by enabling PFMX mode. RAIL typically enables PFMX mode for TX/RX events and then reverts to PFM mode after radio operation is complete.

Because digital leakage currents on EFR32xG26 at high temperatures can exceed 60 mA with no MCU or radio activity at all, PFMX mode must be enabled at all times in EM0 or EM1.

PFM mode may safely be used in EM2 and EM3.

Affected Conditions / Impacts

At lower load currents, PFMX mode may have reduced efficiency compared to PFM mode. See the efficiency curves in 4.28.3 DC-DC Converter of the EFR32BG26 data sheet.

Workaround

RAIL enables PFMX mode for EM0/1 operation on EFR32xG26 devices and no additional workaround is required. PFMX mode can be enabled before RAIL initialization by setting the DCDC->CTRL.PFMXEXTREQ bit.

Resolution

There is currently no resolution for this issue.

2.2 LCD_E301 - LOADBUSY Status Goes Inactive Early With Prescaled Clock

Description of Errata

The LCD_STATUS_LOADBUSY bit erroneously reports completion of writes to the LCD_BACTRL, LCD_AREGA, LCD_AREGB, and LCD_SEGDn registers before synchronization is complete when LCD_CTRL_PRESCALE > 3.

Affected Conditions / Impacts

If LOADBUSY is used to gate consecutive writes to one of the affected registers, only the data associated with the last write is guaranteed to be latched into the register.

Workaround

For each write to one of the affected registers, insert a delay equal to LCD_CTRL_PRESCALE + fLCDCLK after LOADBUSY transitions from 1 to 0 before issuing the next write to the same register.

Note: LOADBUSY reports when data written from the PCLK register domain into the LCD controller's low-frequency clock domain has been synchronized. It does not indicate when data written into one of the affected registers is actually driven on the LCD controller pins.

In cases where writes to these registers, such as LCD_SEGDn, are intended to have the change in pin state be observable on the connected display, LOADBUSY should not be used to gate consecutive writes. Instead, the CPU should issue the register write and wait to issue the next write until a display update event or frame counter update event occurs as reported by the LCD_IF register DISPLAY or FC flag bits. Interrupts associated with these flags can and should be enabled in such cases to minimize energy use by keeping the CPU in a low-energy mode (e.g., EM2) between such consecutive register writes.

Resolution

There is currently no resolution for this issue.

2.3 SE_E302 – DPA Countermeasure Unavailable for Some Operations

Description of Errata

Differential power analysis (DPA) countermeasures for ECDH on Curve25519, ECDH on Curve448, and EdDSA signing on Curve25519 are unavailable due to a lack of hardware support on all Series 2 devices with a Hardware Secure Engine (HSE).

Affected Conditions / Impacts

A successful DPA attack may be possible if the impacted algorithms are implemented in a customer's product. However, a DPA attack is not an easy/straightforward attack as it requires specific equipment, many traces, physical access to the device, and some control over device operation.

If a successful DPA attack occurs, an attacker may be able to gain access to confidential information, such as private keys or encrypted communications between devices.

Workaround

No fix is available to provide the affected DPA countermeasures on Series 2 devices. Refer to Security Advisory A-00000534 for mitigation recommendations, which include refreshing key pairs or using a key pair only once to reduce the risk of a successful DPA attack.

Resolution

There is currently no resolution for this issue.

2.4 USART_E304 – PRS Transmit Unavailable in Synchronous Secondary Mode

Description of Errata

When the USART is configured for synchronous secondary operation, the transmit output (MISO) is not driven if the signal is routed to a pin using the PRS producer (e.g., SOURCESEL = 0x20 and SIGSEL = 0x4 for USART0).

Affected Conditions / Impacts

Systems cannot operate the USART in synchronous secondary mode if the PRS is used to route the transmit output to the RX (MISO) pin. Operation is not affected in main mode when the transmit output is routed to the TX (MOSI) pin using the PRS producer nor is operation affected in any mode when the GPIO_USARTn_RXROUTE and GPIO_USARTn_TXROUTE registers are used.

Workaround

There is currently no workaround for this issue.

Resolution

There is currently no resolution for this issue.