EFR32MG24 Errata

Overview

This document contains information on the EFR32MG24 errata. The latest available revision of this device is revision B. Errata that have been resolved remain documented and can be referenced for previous revisions of this device. The device data sheet explains how to identify the chip revision, either from the package marking or electronically.

Errata effective date: June, 2025.

Current Errata Descriptions

CUR_E302 – Extra EM1 Current if FPU is Disabled

Description of Errata: When the Floating Point Unit (FPU) is disabled, the on-demand Fast Startup RC Oscillator (FSRCO) remains on after an energy mode transition from EM0 to EM1 is complete. This leads to higher current consumption in EM1.

Affected Conditions / Impacts: The enabled FSRCO increases EM1 current consumption by approximately 500 μA.

Workaround: Always enable the FPU at the beginning of code execution via the Coprocessor Access Control Register (CPACR) in the System Control Block (SCB).

Resolution: There is currently no resolution for this issue.

EUSART_E302 - Synchronous EUSART Module Disable Lockup

Description of Errata: The EUSART freezes and does not function if firmware initializes the EUSART in synchronous main mode, disables it and reconfigures it to synchronous secondary or asynchronous mode, re-enables it, transfers data, and then disables it again. A handshake signal fails to fully propagate through the EUSART disable logic when leaving synchronous main mode.

Affected Conditions / Impacts: Systems that use the EUSART in synchronous main mode cannot simply switch to another mode because this causes the module to freeze. This issue occurs only when firmware attempts to switch from synchronous main mode to another mode. Switching between all other modes is unaffected.

Workaround: Firmware can manually generate additional clock edges after the module is disabled to fully propagate the handshake signal and allow the next disable sequence to happen as usual.

Resolution: There is currently no resolution for this issue.

EUSART_E303 – EUSART Receiver Enters Lockup State when Using Low Frequency IrDA Mode

Description of Errata: When low frequency IrDA mode is enabled (EUSART_IRLFCFG_IRLFEN = 1), the receiver can block incoming traffic if it receives either a 0 if EUSART_CFG0_RXINV = 0 or 1 if EUSART_CFG0_RXINV = 1 before the EUSART module is enabled (EUSART_EN_EN =1), the receiver is enabled (EUSART_CMD_RXEN =1), and the write to enable the receiver (RXEN = 1) has been synchronized (EUSART_SYNCBUSY_RXEN = 0).

Affected Conditions / Impacts: Incoming traffic will be blocked at the EUSART receiver. Subsequent interrupts and status flags will not be set correctly.

Workaround: To avoid entering the lockup state, use one of the workarounds mentioned below:

• When the receiver (RX) input is routed through the PRS: Force the input to the IrDA demodulator to high by using the PRS before enabling EUSART. Keep it this way until the receiver has been enabled and the EUSART_CMD_RXEN bit is synchronized.
• When the receiver (RX) input is not routed through the PRS: Force the input to the IrDA demodulator to high by using a GPIO pin other than the current EUSART RX pin before enabling the EUSART. Keep it this way until the receiver has been enabled and the EUSART_CMD_RXEN bit is synchronized.

Resolution: There is currently no resolution for this issue.

EUSART_E304 – Incorrect Stop Bits Lock Receiver

Description of Errata: When low frequency IrDA mode is enabled (EUSART_IRLFCFG_IRLFEN = 1), the receiver can block incoming traffic if it receives either a 0 if EUSART_CFG0_RXINV = 0 or 1 if EUSART_CFG0_RXINV = 1 when it is expecting a stop bit.

Affected Conditions / Impacts: Incoming traffic will be blocked at the EUSART receiver. Subsequent interrupts and status flags will not be set correctly.

Workaround: To avoid receiver lock-up in the application firmware caused by formatting errors in the received data, change the receiver GPIO pin routing to force the input to the IrDA demodulator to 1 for the anticipated period of time during which such data can be received.

Resolution: There is currently no resolution for this issue.

IADC_E306 - Changing Gain During a Scan Sequence Causes an Erroneous IADC Result

Description of Errata: Differences in the ANALOGGAIN setting within multiple IADC_CFGx groups during a scan sequence introduces a transient condition that may result in an inaccurate IADC conversion.

Affected Conditions / Impacts: The result of the IADC scan measurement may not match the expected result for the voltage present on the pin during the conversion.

Workaround: Both 1 and 2 shown below must be implemented:

1. If there is a difference in the ANALOGGAIN setting between IADC_CFGx groups during a scan sequence, the IADC_SCHEDX clock prescaler must also change to an appropriate setting. This forces a warmup state (5 µs delay) in between ANALOGGAIN changes.
2. The first and last entry of a scan group should use IADC_CFG0, which is the default configuration of the IADC at the start and end of a scan conversion sequence.

Resolution: There is currently no resolution for this issue.

KEYSCAN_E301 - Unused Rows Are Not Properly Gated Off

Description of Errata: Unused KEYSCAN row inputs cause the KEY bit in the KEYSCAN_IF register to be set at all times indicating a key was pressed. This prevents the interrupt flag from clearing and stops the scan procedure.

Affected Conditions / Impacts: The KEY bit in the KEYSCAN_IF register is always set when rows are left unused.

Workaround: Configure the GPIO_KEYSCAN_ROWSENSEnROUTE registers for any unused row inputs to the same GPIO port and pin associated with any of the row inputs that are used.

Resolution: There is currently no resolution for this issue.

RADIO_E307 – BLE 2 Mbps and IEEE 802.15.4 Sensitivity and Selectivity Degradation with Crystals Below 39 MHz

Description of Errata: Sensitivity and selectivity degradation using the BLE 2 Mbps or 802.15.4 PHYs when using crystals below 39 MHz.

Affected Conditions / Impacts: The BLE 2 Mbps PHY and 802.15.4 PHY will show sensitivity degradation of approximately 8 dB at higher frequencies, and 3 dB up to 37 dB selectivity degradation based on the channel, when using crystals below 39 MHz.

Workaround: There is currently no workaround for either a 38 MHz or 38.4 MHz crystal with releases of Gecko SDK prior to 4.1.0. Use of a 39 MHz or 40 MHz crystal avoids the sensitivity and selectivity degradation when using earlier SDK releases.

Resolution: This issue is resolved by upgrading to Gecko SDK 4.1.0 or later.

SE_E301 – Bricked Device After SE Firmware Upgrade or Bootloader Upgrade

Description of Errata: Devices with a date code less than 2216 may become permanently disabled during an over-the-air (OTA) or over-the-wire (OTW) upgrade of the SE firmware or the bootloader in certain configurations.

Affected Conditions / Impacts: Devices with a date code before 2216 and SE firmware prior to version 2.1.8 will fail to upgrade properly and become permanently disabled at step #5 of the upgrade procedure if the SE or bootloader upgrade image is staged such that any portion of it extends beyond a 512 kB (address offset 0x7D000) boundary.

• Changing the staging offset for SE firmware and bootloader upgrade images is not common.
• Devices with affected date codes that are upgraded to SE firmware version 2.1.8 or later will verify that the SE firmware or bootloader upgrade image does not extend beyond the 512 kB boundary and, in such cases, will not perform the upgrade and will return an error code.
• OTA and OTW (serial port) upgrades of the application firmware are not impacted.
• Upgrades of SE firmware or the bootloader over the serial wire debug interface are also not impacted.
• Devices with date code 2216 or later are unaffected.

Workaround:

• Upgrade the bootloader over the debug interface with a configuration that uses the default staging offset at 0x8000.
• Upgrade the SE firmware over the debug interface to version 2.1.8 or later.

Resolution: Use one of the workarounds for affected devices.

SE_E302 – DPA Countermeasure Unavailable for Some Operations

Description of Errata: Differential power analysis (DPA) countermeasures for ECDH on Curve25519, ECDH on Curve448, and EdDSA signing on Curve25519 are unavailable due to a lack of hardware support on all Series 2 devices with a Hardware Secure Engine (HSE).

Affected Conditions / Impacts: A successful DPA attack may be possible if the impacted algorithms are implemented in a customer's product. However, a DPA attack is not an easy/straightforward attack as it requires specific equipment, many traces, physical access to the device, and some control over device operation.

Workaround: No fix is available to provide the affected DPA countermeasures on Series 2 devices. Refer to Security Advisory A-00000534 for mitigation recommendations.

Resolution: There is currently no resolution for this issue.

USART_E304 – PRS Transmit Unavailable in Synchronous Secondary Mode

Description of Errata: When the USART is configured for synchronous secondary operation, the transmit output (MISO) is not driven if the signal is routed to a pin using the PRS producer.

Affected Conditions / Impacts: Systems cannot operate the USART in synchronous secondary mode if the PRS is used to route the transmit output to the RX (MISO) pin. Operation is not affected in main mode when the transmit output is routed to the TX (MOSI) pin using the PRS producer nor is operation affected in any mode when the GPIO_USARTn_RXROUTE and GPIO_USARTn_TXROUTE registers are used.

Workaround: There is currently no workaround for this issue.

Resolution: There is currently no resolution for this issue.

Resolved Errata Descriptions

CUR_E303 - Active Charge Pump Clock Causes High Current

Description of Errata: When the ACMP0, ACMP1, or IADC0 peripherals are active, the clock to the internal analog mux charge pump may also be activated, resulting in extra supply current.

Affected Conditions / Impacts:

• ACMP0 and ACMP1: The charge pump clock is activated whenever either module is enabled via the ACMPn_EN_EN bit or when enabled by the LESENSE state machine.
• IADC0: The charge pump clock is activated when any portion of the IADC analog circuitry is on.

The extra current is from a shared block and increases supply current by an approximate total of 25 µA when any of the above conditions are true.

Workaround: No workaround exists to entirely eliminate the extra current. The impact of the current can be reduced by duty-cycling the peripheral.

Resolution: This issue is resolved in revision B devices.

DCDC_E302 – DCDC Interrupts Block EM2/3 Entry or Cause Unexpected Wake-up

Description of Errata: Regardless of the setting of the DCDC Interrupt Enable (DCDC_IEN) register, if the DCDC interrupt is enabled in the NVIC, the BYPSW, WARM, RUNNING, or TMAX interrupt requests can wake the device from EM2/3 or prevent it from entering EM2/3.

Affected Conditions / Impacts: The errata is limited to the BYPSW, WARM, RUNNING, or TMAX requests as reflected in the DCDC Interrupt Flag (DCDC_IF) register, which also function as wake-up sources from EM2/3.

Workaround: To prevent unwanted wake-up from or blocked entry into EM2/3, disable the DCDC interrupt using NVIC_DisableIRQ (DCDC_IRQn) before entering EM2/3 and re-enable the DCDC interrupt using NVIC_EnableIRQ(DCDC_IRQn) after EM2/3 wake-up.

Resolution: This issue is resolved in revision B devices.

EMU_E304 – Higher Than Expected EM2 Current

Description of Errata: Current consumption in EM2 is higher than the data sheet specification.

Affected Conditions / Impacts: Systems operating in EM2 have higher than expected current consumption, regardless of whether the DCDC is enabled.

Workaround: There is currently no workaround for this issue.

Resolution: This issue is resolved in revision B devices.

RADIO_E304 - Zigbee Signal Identifier False Detection

Description of Errata: The Zigbee signal identifier sometimes indicates a false detection when a BLE 1 Mbps or Continuous Wave (CW) signal is present.

Affected Conditions / Impacts: Systems that are exposed to BLE 1 Mbps or Continuous Wave (CW) signals sometimes falsely indicate the presence of non-existent Zigbee signals.

Workaround: There is currently no workaround for this issue.

Resolution: This issue is resolved in revision B devices.

RADIO_E305 - Channel Clear Detection

Description of Errata: The Listen Before Talk (LBT) and Carrier Sense Multiple Access-Collision Avoidance (CSMA-CA) algorithms always indicate that the channel is clear, even when this is not the case.

Affected Conditions / Impacts: The LBT and CSMA-CA algorithms cannot be used.

Workaround: There is currently no workaround for this issue.

Resolution: This issue is resolved in revision B devices.

Revision History

Revision 0.8 (June, 2025)

• Minor updates to EUSART_E302.
• Added SE_E302.

Revision 0.7 (December, 2022)

• Added EUSART_E303 and EUSART_E304.
• Fixed workaround routing for KEYSCAN_E301.

Revision 0.6 (June, 2022)

• RADIO_E307 updated to include workaround.

Revision 0.5 (April, 2022)

• Added SE_E301.
• Updated RADIO_E307.

Revision 0.4 (March, 2022)

• Added CUR_E303.
• Added IADC_E306.
• Added KEYSCAN_E301.
• Added RADIO_E307.

Revision 0.3 (January, 2022)

• Updated for device revision B.
• Resolved and moved DCDC_E302, EMU_E304, RADIO_E304 and RADIO_E305 to Resolved Errata.
• Added USART_E304.
• Replaced select terms with inclusive lexicon.

Revision 0.2 (August, 2021)

• Added CUR_E302 and DCDC_E302.

Revision 0.1 (June, 2021)

• Initial release