S32K1xx ADC Guidelines, Specifications, and Configuration

1. Introduction

NXP S32K1xx automotive microcontroller devices feature a 12-bit successive approximation Analog-to-Digital converter (SAR ADC) for acquiring and digitalizing analog input signals. This application note provides information on basic topics to maximize the benefit from the ADC module, including understanding common terminology, error sources, specifications, best practices for accuracy, and common triggering configuration examples for the S32K1xx family.

2. ADC Concepts, Error Sources, and Specification

This section explains the concepts and terminology used to characterize an ADC, potential error sources, and the specification parameters found in the S32K1xx family datasheet.

2.1. ADC Basic Concepts

• Resolution: The number of bits in the ADC digital output representing an analog input signal. For S32K1xx devices, resolution can be configured to 8, 10, or 12 bits.
• Reference Voltage: The ADC requires a reference voltage (VREFH - VREFL) for comparison with the analog input to produce a digital output.
• ADC Output Formula: The conversion equation is ADC result = (2^N * Vin) / VREF, where N is the ADC resolution.
• Least Significant Bits (LSB): An LSB is a unit of voltage equal to the smallest resolution of the ADC, calculated as LSB = VREF / 2^N.
• ADC Actual Transfer Function: Describes the ADC's behavior, including inherent errors.
• ADC Ideal Transfer Function: Represents a perfectly linear ADC, with steps based on quantization methods (Uncompensated or 1/2 LSB Compensated).

2.2. Sources of Error in ADC Measurements

• Reference Voltage Noise: Instability in the reference voltage causes changes in digital outputs. An example shows a 50 mV increase in VREF causing an 8 LSB error.
• Analog Input Signal Noise: High-frequency variations in the analog input signal can cause conversion errors. Noise exceeding 1 LSB reduces the number of reliable bits.
• Analog-Signal Source Resistance: Series resistance (R_IN) between the source and the ADC input causes a voltage drop, leading to lower converted values if sampling time is insufficient. This is related to the 'Source Impedance (Rs)' parameter in the datasheet.
• Temperature Influence: Temperature variations can cause offset and gain error drift, and affect the reference voltage. Firmware adjustments can help compensate for these errors.
• I/O Pin Crosstalk: Switching I/O pins near an analog input can introduce noise through capacitive coupling, impacting conversion accuracy.

2.3. S32K1xx ADC Specifications

• ADC Clock Frequency (f_ADCK): The input conversion clock frequency, determining conversion time.
• ADC Conversion Frequency (f_CONV): Also known as conversion rate or sampling rate, it measures how quickly analog signals are converted. It depends on ADC clock frequency, hardware averaging, number of samples, and configuration.
• Differential Non-Linearity (DNL): The difference between the actual code width and the ideal transition voltage of 1 LSB. DNL errors can lead to missing codes (DNL = -1.0 LSB) or non-monotonicity (DNL > 1.0 LSB).
• Integral Non-Linearity (INL): The cumulative effect of DNL errors, calculated as the sum of DNLs up to the code of interest.
• Total Unadjusted Error (TUE): The summation of offset, gain, linearity, and quantization errors, representing the real expected accuracy of the ADC in LSBs for static/DC inputs.

3. Best Practices to Increase Accuracy

• ADC Calibration: The S32K1xx ADC has a self-calibration mechanism. It is mandatory to run this after each Power On Reset. Calibration values can be saved to non-volatile memory to avoid recalibration. Recommendations include: ensuring digital I/Os are silent, using a stable and high VREFH, isolating VREFH pins, running calibration with ADC clock <= 25 MHz if the application clock is faster, setting hardware averaging to maximum (32 samples), and performing calibration once at room temperature after POR.
• Reference Voltage and Power Supply: The power supply should have good line, load regulation, and temperature drift characteristics as the ADC uses VREF or VDDA as reference. Using a high-precision regulator for VREF is recommended.
• Using Bandgap to Monitor Reference Voltage: The internal bandgap channel (channel 27) can be used to monitor VREF changes. The VREF can be calculated using the formula: VREF(mV) = (1000 * 2^N) / BG_ADCresult.
• Analog Source Resistance Match: Keep source resistance as low as possible. If high source resistance is unavoidable, consider lowering ADC clock frequencies and increasing sample times (using the SMPLTS field in CFG2 register).
• Minimizing I/O Pin Crosstalk: Shield analog signals by placing clear analog ground tracks between adjacent PCB tracks or MCU pins.

4. ADC Triggering Mode Examples

The S32K1xx ADC offers flexible trigger source configurations. The following examples are based on the S32K144 EVB board.

4.1. Software Trigger

The simplest trigger mode, initiated by writing to the ADCH field in the ADCx_SC1A register. A single conversion is triggered with each write. The result is available in the ADCx_RA register.

4.2. PDB Trigger

The PDB (Programmable Delay Block) timer module is the suggested hardware trigger method. It can trigger ADC conversions periodically. The trigger can follow a direct path or a PDB/TRGMUX multiplexed path, depending on the SC1n register used.

4.3. PDB Trigger in Back-to-Back Mode

In this mode, ADC conversion complete flags trigger subsequent PDB channels' pre-trigger and trigger outputs sequentially. This is useful for sampling multiple ADC channels consecutively. The direct and multiplexed paths for PDB triggers still apply.

4.4. TRGMUX Trigger

The TRGMUX (Trigger Multiplexer) module synchronizes ADC conversions with various internal and external trigger signals. It can be used for SC1n registers 0 to 3 and always goes through the trigger latching gasket. The example shows triggering an ADC conversion on the rising edge of an external signal (TRGMUX_IN0).

5. References

• S32K1xx Datasheet
• S32K1xx Reference Manual
• AN5426 Hardware Design Guidelines for S32K1xx
• AN4373 Cookbook for SAR ADC Measurements
• ADC Calibration document

Appendix A. Example code: ADC software triggering

Provides C code for ADC software triggering using the S32K144 microcontroller.

Appendix B. Example code: ADC with PDB trigger

Provides C code for ADC triggering using the PDB module on the S32K144 microcontroller.

Appendix C. Example code: ADC with PDB and back-to-back triggers

Provides C code for ADC triggering using PDB in back-to-back mode on the S32K144 microcontroller.

Appendix D. Example code: ADC with TRGMUX trigger

Provides C code for ADC triggering using the TRGMUX module on the S32K144 microcontroller.

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