• 120 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz Memories and memory interfaces • Up to 256 KB of embedded flash and 64 KB of SRAM • Preprogrammed Kinetis Flashloader for one-time, in-system factory programming System peripherals • Flexible low-power modes, multiple wake up sources
NXP Semiconductors Data Sheet: Technical Data KS22P100M120SF0 Rev. 3, 04/2016 KS22/KS20 Microcontroller 120 MHz ARM® Cortex®-M4, with up to 256 KB Flash The KS2x product family is built on the ARM® Cortex®-M4 processor with lower power and higher memory densities in multiple packages. This device offers 120 MHz performance with an integrated single-precision floating point unit (FPU). Embedded flash memory sizes range from 128 KB to 256KB. This device also includes: · USB FS OTG 2.0 with crystal-less functionality · FlexCAN, supporting CAN protocol according to the ISO 11898-1 standard and CAN 2.0 B protocol specifications · FlexIO, a highly configurable module providing a wide range of protocols including, but not limited to UART, LPI2C, SPI, I2S, and PWM/Waveform generation. MKS22FN256Vxx12 MKS22FN128Vxx12 MKS20FN256Vxx12 MKS20FN128Vxx12 100 & 64 LQFP (LL & LH) 48 QFN (FT) 14×14×1.7 mm Pitch 7×7×0.65 mm Pitch 0.5 0.5 mm; 10×10×1.6 mm mm Pitch 0.5 mm Performance Analog modules · 120 MHz ARM Cortex-M4 core with DSP instructions · One 16-bit ADC module with up to 17 single-end delivering 1.25 Dhrystone MIPS per MHz channels and 4 differential channels, and up to 1.2 Memories and memory interfaces Msps at 13-bit mode · One 12-bit DAC module · Up to 256 KB of embedded flash and 64 KB of SRAM · One analog comparator (CMP) module · Preprogrammed Kinetis Flashloader for one-time, in- system factory programming Communication interfaces System peripherals · USB full-speed 2.0 device controller · One FlexIO module · Flexible low-power modes, multiple wake up sources · Three UART modules (one supporting ISO7816, · 16-channel asynchronous DMA controller and the other two operating up to 1.5 Mbit/s) · Independent external and software watchdog monitor · One LPUART module supporting asynchronous Clocks · Two crystal oscillators: 32 kHz (RTC), and 32-40 kHz or 3-32 MHz · Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz · Multi-purpose clock generator (MCG) with PLL and FLL operation in low-power modes · Two LPI2C modules supporting up to 5 Mbit/s, asynchronous operation in low-power modes supported · Two 16-bit SPI modules supporting up to 30 Mbit/s · Two FlexCAN modules for KS22, One FlexCAN for Security and integrity modules · Hardware CRC module KS20 · Two I2S modules · 128-bit unique identification (UID) number per chip · Hardware random-number generator · Flash access control (FAC) to protect proprietary software Timers · Three 16-bit low-power timer PWM modules (TPM) · One low-power timer (LPTMR) · Periodic interrupt timer (PIT) Human-machine interfaces · Up to 66 general-purpose input/output pins (GPIO) · Real time clock (RTC), with independent power domain · Programmable delay block (PDB) NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. © 20152016 NXP B.V. Operating characteristics · Voltage range (including flash writes): 1.71 to 3.6 V · Temperature range (ambient): 40 to 105 °C Related Resources Type Selector Guide Product Brief Reference Manual Data Sheet Chip Errata Package drawing Description Resource The Freescale Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor The Product Brief contains concise overview/summary information to KS22PB 1 enable quick evaluation of a device for design suitability. The Reference Manual contains a comprehensive description of the KS22P100M120SF0RM1 structure and function (operation) of a device. The Data Sheet includes electrical characteristics and signal connections. The chip mask set Errata provides additional or corrective information for a particular device mask set. This document: KS22P100M120SF01 KINETIS_K_0N87R 1 Package dimensions are provided in package drawings. LQFP 100-pin: 98ASS23308W LQFP 64-pin: 98ASS23234W QFN 48-pin: 98ASA00616D 1. To find the associated resource, go to http://www.freescale.com and perform a search using this term. 2 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 ARM ® CortexTM-M4 Core Debug interfaces Interrupt controller DSP FPU System Memories and Memory Interfaces eDMA (16ch) DMAMUX Low-leakage wake-up unit Program flash Flash cache RAM WDOG EWM Clocks Phaselocked loop Frequencylocked loop Low/high frequency oscillators Internal reference clocks Security and Integrity CRC Randomnumber generator Flash access control Analog 16-bit ADC x1 Comparator with 6-bit DAC x1 12-bit DAC x1 PMC Timers TPM x1 (6ch) x2 (2ch) Programmable delay block PIT (4ch) 16-bit low-power timer Independent real-time clock Communication Interfaces LPI2C I2S x2 x2 Human-Machine Interface (HMI) Up to 66 GPIOs UART x3 USB fullspeed OTG LPUART x1 FlexIO SPI x2 FlexCAN * Note: for KS22, CAN x2; for KS20, CAN x1. Figure 1. Functional block diagram NOTE DAC0 and I2S1 are NOT supported in the 48-QFN package. For more details, see the "Signal Multiplexing and Pin Assignments" section. KS22/KS20 Microcontroller, Rev. 3, 04/2016 3 NXP Semiconductors Table of Contents 1 Ordering information............................................................... 5 2 Overview................................................................................. 6 2.1 System features...............................................................7 2.1.1 ARM Cortex-M4 core........................................ 7 2.1.2 NVIC..................................................................7 2.1.3 AWIC.................................................................7 2.1.4 Memory............................................................. 8 2.1.5 Reset and boot..................................................9 2.1.6 Clock options.....................................................10 2.1.7 Security............................................................. 13 2.1.8 Power management.......................................... 14 2.1.9 LLWU................................................................ 16 2.1.10 Debug controller................................................17 2.1.11 Computer operating properly (COP) watchdog timer.................................................................. 17 2.2 Peripheral features.......................................................... 17 2.2.1 eDMA and DMAMUX........................................ 18 2.2.2 TPM...................................................................18 2.2.3 ADC...................................................................19 2.2.4 DAC...................................................................19 2.2.5 CMP.................................................................. 20 2.2.6 RTC...................................................................21 2.2.7 PIT.....................................................................21 2.2.8 PDB...................................................................21 2.2.9 LPTMR.............................................................. 22 2.2.10 CRC.................................................................. 22 2.2.11 UART................................................................ 23 2.2.12 LPUART............................................................ 23 2.2.13 SPI.................................................................... 24 2.2.14 FlexCAN............................................................24 2.2.15 LPI2C................................................................ 26 2.2.16 USB...................................................................26 2.2.17 I2S.....................................................................27 2.2.18 FlexIO................................................................27 2.2.19 Port control and GPIO.......................................28 3 Memory map........................................................................... 30 4 Pinouts.................................................................................... 31 4.1 Signal Multiplexing and Pin Assignments........................ 31 4.2 Pin properties.................................................................. 34 4.3 Module Signal Description Tables................................... 39 4.3.1 Core Modules....................................................39 4.3.2 System Modules................................................40 4.3.3 Clock Modules...................................................40 4.3.4 Analog............................................................... 41 4.3.5 Timer Modules.................................................. 42 4.3.6 Communication Interfaces................................ 43 4.3.7 Human-Machine Interfaces (HMI)..................... 47 4.4 Pinouts.............................................................................47 4.5 Package dimensions....................................................... 50 5 Electrical characteristics..........................................................56 5.1 Terminology and guidelines.............................................56 5.1.1 Definitions......................................................... 56 5.1.2 Examples.......................................................... 57 5.1.3 Typical-value conditions....................................58 5.1.4 Relationship between ratings and operating requirements..................................................... 58 5.1.5 Guidelines for ratings and operating requirements..................................................... 59 5.2 Ratings............................................................................ 59 5.2.1 Thermal handling ratings...................................59 5.2.2 Moisture handling ratings.................................. 60 5.2.3 ESD handling ratings........................................ 60 5.2.4 Voltage and current operating ratings............... 60 5.3 General............................................................................ 60 5.3.1 AC electrical characteristics.............................. 61 5.3.2 Nonswitching electrical specifications............... 61 5.3.3 Switching specifications.................................... 72 5.3.4 Thermal specification........................................ 74 5.4 Peripheral operating requirements and behaviors...........75 5.4.1 Debug modules................................................. 75 5.4.2 System modules................................................80 5.4.3 Clock modules...................................................80 5.4.4 Memories and memory interfaces.....................86 5.4.5 Security and integrity modules.......................... 87 5.4.6 Analog............................................................... 87 5.4.7 Timers............................................................... 97 5.4.8 Communication interfaces.................................97 6 Design considerations.............................................................108 6.1 Hardware design considerations..................................... 108 6.1.1 Printed circuit board recommendations.............108 6.1.2 Power delivery system...................................... 108 6.1.3 Analog design................................................... 109 6.1.4 Digital design.....................................................110 6.1.5 Crystal oscillator................................................112 6.2 Software considerations.................................................. 114 7 Part identification.....................................................................114 7.1 Description.......................................................................114 7.2 Format............................................................................. 115 7.3 Fields............................................................................... 115 7.4 Example...........................................................................115 8 Revision history.......................................................................116 4 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Ordering information 1 Ordering information The following chips are available for ordering. Table 1. Ordering information Product Memory Part Marking number (Line1/Line2) Flash (KB) SRAM (KB) MKS22F MKS22FN256 / 256 64 N256VLL VLL12 12 MKS22F MKS22FN256 / 256 64 N256VLH VLH12 12 MKS22F MKS22FN256 / 256 64 N256VFT VFT12 12 MKS22F MKS22FN128 / 128 64 N128VLL VLL12 12 MKS22F MKS22FN128 / 128 64 N128VLH VLH12 12 MKS22F MKS22FN128 / 128 64 N128VFT VFT12 12 MKS20F MKS20FN256 / 256 64 N256VLL VLL12 12 MKS20F MKS20FN256 / 256 64 N256VLH VLH12 12 MKS20F MKS20FN256 / 256 64 N256VFT VFT12 12 MKS20F MKS20FN128 / 128 64 N128VLL VLL12 12 MKS20F MKS20FN128 / 128 64 N128VLH VLH12 12 MKS20F MKS20FN128 / 128 64 N128VFT VFT12 12 Package Pin Package count 100 LQFP IO and ADC channel GPIOs GPIOs (INT/HD) 1 ADC channel s (SE/DP) 2 Commu nication FlexCAN 66 66/8 17/4 2 64 LQFP 40 40/8 14/2 3 2 48 QFN 35 35/8 13/-- 2 100 LQFP 66 66/8 17/4 2 64 LQFP 40 40/8 14/2 3 2 48 QFN 35 35/8 13/-- 2 100 LQFP 66 66/8 17/4 1 64 LQFP 40 40/8 14/2 3 1 48 QFN 35 35/8 13/-- 1 100 LQFP 66 66/8 17/4 1 64 LQFP 40 40/8 14/2 3 1 48 QFN 35 35/8 13/-- 1 KS22/KS20 Microcontroller, Rev. 3, 04/2016 5 NXP Semiconductors Overview 1. INT: interrupt pin numbers; HD: high drive pin numbers 2. SE: single-ended; DP: differential pair 3. ADC0_DP1 is for single-ended (SE) mode only in 64-LQFP. 2 Overview The following figure shows the system diagram of this device. Cortex M4 IOPORT Debug (SWD/JTAG) CM4 core NVIC Master M0 code bus M1 system bus Slave Flash 128-256 KB S0 FMC eDMA M2 DMA MUX M4 USB FS Clock Source 4 MHz IRC FLL 32 kHz IRC PLL OSC LPO IRC48M RTC Oscillator S1 SRAM_L and _U, 64 KB in total S2 S3 MUX Peripheral Bridge 0 (Bus Clock - Max 60 MHz) Crossabar Switch (Platform Clcok - Max 120 MHz) GPIOA GPIOB GPIOC GPIOD GPIOE ADC (16-bit) CMP (with 6-bit DAC) DAC (12-bit) PDB TPM0 (6-channel) TPM1 (2-channel) TPM2 (2-channel) Low Power Timer Periodic Interrupt Timer RTC CAN x2 (KS22), x1 (KS20) UART x3 LPUART DSPI x2 LPI2C x2 FlexIO I2S x2 CRC RNG EWM Watchdog (COP) Register File (32 Bytes) Low Leakage Wakeup Unit Reset Control Module System Mode Control Power Management Control Figure 2. System diagram The crossbar switch connects bus masters and slaves using a crossbar switch structure. This structure allows up to four bus masters to access different bus slaves simultaneously, while providing arbitration among the bus masters when they access the same slave. 6 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Overview 2.1 System features The following sections describe the high-level system features. 2.1.1 ARM Cortex-M4 core The ARM Cortex-M4 is the member of the Cortex M Series of processors targeting microcontroller cores focused on very cost sensitive, deterministic, interrupt driven environments. The Cortex M4 processor is based on the ARMv7 Architecture and Thumb®-2 ISA and is upward compatible with the Cortex M3, Cortex M1, and Cortex M0 architectures. Cortex M4 improvements include an ARMv7 Thumb-2 DSP (ported from the ARMv7-A/R profile architectures) providing 32-bit instructions with SIMD (single instruction multiple data) DSP style multiply-accumulates and saturating arithmetic. 2.1.2 NVIC The Nested Vectored Interrupt Controller supports nested interrupts and 16 priority levels for interrupts. In the NVIC, each source in the IPR registers contains 4 bits. It also differs in number of interrupt sources and supports 240 interrupt vectors. The Cortex-M family uses a number of methods to improve interrupt latency . It also can be used to wake the MCU core from Wait and VLPW modes. 2.1.3 AWIC The asynchronous wake-up interrupt controller (AWIC) is used to detect asynchronous wake-up events in Stop mode and signal to clock control logic to resume system clocking. After clock restarts, the NVIC observes the pending interrupt and performs the normal interrupt or event processing. The AWIC can be used to wake MCU core from Partial Stop, Stop and VLPS modes. KS22/KS20 Microcontroller, Rev. 3, 04/2016 7 NXP Semiconductors Overview Wake-up sources for this SoC are listed as below: Table 2. AWIC Partial Stop, Stop and VLPS Wake-up Sources Wake-up source Available system resets Low voltage detect Low voltage warning High voltage detect Pin interrupts ADC CMP LPI2C FlexIO TPM UART LPUART USB FS/LS Controller LPTMR RTC I2S (SAI) TPM CAN NMI Description RESET pin and WDOG when LPO is its clock source, and JTAG Power Mode Controller Power Mode Controller Power Mode Controller Port Control Module - Any enabled pin interrupt is capable of waking the system The ADC is functional when using internal clock source Since no system clocks are available, functionality is limited, trigger mode provides wakeup functionality with periodic sampling Functional when using clock source which is active in Stop and VLPS modes Functional when using clock source which is active in Stop and VLPS modes Functional when using clock source which is active in Stop and VLPS modes Active edge on RXD Functional when using clock source which is active in Stop and VLPS modes Wakeup Functional when using clock source which is active in Stop and VLPS modes Functional in Stop/VLPS modes Functional when using an external bit clock or external master clock Functional when using clock source which is active in Stop and VLPS modes Wakeup on edge (CANx_RX) Non-maskable interrupt 2.1.4 Memory This device has the following features: · 64 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait states. · The non-volatile memory is divided into · 128/256 KB of embedded program memory The program flash memory contains a 16-byte flash configuration field that stores default protection settings and security information. The page size of program flash is 2 KB. The protection setting can protect 32 regions of the program flash memory from unintended erase or program operations. 8 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Overview The security circuitry prevents unauthorized access to RAM or flash contents from debug port. · System register file This device contains a 32-byte register file that is powered in all power modes. Also, it retains contents during low power modes and is reset only during a power-on reset. 2.1.5 Reset and boot The following table lists all the reset sources supported by this device. NOTE In the following table, Y means the specific module, except for the registers, bits or conditions mentioned in the footnote, is reset by the corresponding Reset source. N means the specific module is not reset by the corresponding Reset source. Table 3. Reset source Reset sources Descriptions Modules PMC SIM SMC RCM LLWU Reset pin is negated POR reset Power-on reset (POR) Y Y Y Y Y Y System resets Low-voltage detect (LVD) Y1 Y Y Y Y Y Low leakage wakeup N Y2 N Y N Y3 (LLWU) reset External pin reset (RESET) Y1 Y2 Y4 Y Y Y Watchdog (WDOG) reset Y1 Y2 Y4 Y5 Y Y Multipurpose clock Y1 Y2 Y4 Y5 Y Y generator loss of clock (LOC) reset Multipurpose clock Y1 Y2 Y4 Y5 Y Y generator loss of lock (LOL) reset Stop mode acknowledge Y1 Y2 Y4 Y5 Y Y error (SACKERR) Software reset (SW) Y1 Y2 Y4 Y5 Y Y Lockup reset (LOCKUP) Y1 Y2 Y4 Y5 Y Y Table continues on the next page... RTC Y N N N N N N N N N LPTM Others R Y Y Y Y N Y N Y N Y N Y N Y N Y N Y N Y KS22/KS20 Microcontroller, Rev. 3, 04/2016 9 NXP Semiconductors Overview Table 3. Reset source (continued) Reset sources Descriptions MDM DAP system reset Debug reset Debug reset Modules PMC SIM SMC RCM LLWU Reset RTC LPTM Others pin is R negated Y1 Y2 Y4 Y5 Y Y N N Y Y1 Y2 Y4 Y5 Y Y N N Y 1. Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV] 2. Except SIM_SOPT1 3. Only if RESET is used to wake from VLLS mode. 4. Except SMC_PMCTRL, SMC_STOPCTRL, SMC_PMSTAT 5. Except RCM_RPFC, RCM_RPFW, RCM_FM This device supports booting from: · internal flash 2.1.6 Clock options The MCG module controls which clock source is used to derive the system clocks. The clock generation logic divides the selected clock source into a variety of clock domains, including the clocks for the system bus masters, system bus slaves, and flash memory . The clock generation logic also implements module-specific clock gating to allow granular shutoff of modules. The primary clocks for the system are generated from the MCGOUTCLK clock. The clock generation circuitry provides several clock dividers that allow different portions of the device to be clocked at different frequencies. This allows for trade-offs between performance and power dissipation. Various modules, such as the USB OTG Controller, have module-specific clocks that can be generated from the IRC48MCLK or MCGPLLCLK or MCGFLLCLK clock. In addition, there are various other module-specific clocks that have other alternate sources. Clock selection for most modules is controlled by the SOPT registers in the SIM module. For more details on the clock operations and configurations, see the Clock Distribution chapter in the Reference Manual. The following figure is a high level block diagram of the clock generation. 10 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Overview MCG SIM 4 MHz IRC 32 kHz IRC FCRDIV CG MCGIRCLK MCGFFCLK Clock options for some peripherals (see note) FLL OUTDIV1 CG Core / system clocks PLL PRDIV FRDIV EXTAL0 XTAL0 EXTAL32 XTAL32 System oscillator OSC logic XTAL_CLK OSCCLK DIV OSC32KCLK RTC oscillator 32.768 kHz OSC logic 1 Hz IRC48M internal oscillator IRC48M logic IRC48MCLK MCGOUTCLK OUTDIV2 CG Bus clock MCGFLLCLK MCGPLLCLK OUTDIV4 CG Flash clock MCGPLLCLK/ MCGFLLCLK/ IRC48MCLK Clock options for some peripherals (see note) IRC48MCLK OSCERCLK_UNDIV OSCERCLK ERCLK32K PMC PMC logic LPO RTC_CLKOUT CG -- Clock gate Note: See subsequent sections for details on where these clocks are used. Figure 3. Clock block diagram In order to provide flexibility, many peripherals can select the clock source to use for operation. This enables the peripheral to select a clock that will always be available during operation in various operational modes. The following table summarizes the clocks associated with each module. Module ARM Cortex-M4 core NVIC DAP Table 4. Module clocks Bus interface clock Internal clocks Core modules System clock Core clock System clock -- System clock -- Table continues on the next page... I/O interface clocks -- -- -- KS22/KS20 Microcontroller, Rev. 3, 04/2016 11 NXP Semiconductors Overview Module ITM cJTAG, JTAGC DMA DMA Mux Port control Crossbar Switch Peripheral bridges LLWU, PMC, SIM, RCM Mode controller MCM EWM Watchdog timer MCG OSC IRC48M Flash Controller Flash memory CRC RNGA ADC CMP DAC TPM PDB PIT LPTMR RTC 12 NXP Semiconductors Table 4. Module clocks (continued) Bus interface clock Internal clocks I/O interface clocks System clock -- -- -- -- JTAG_CLK System modules System clock -- -- Bus clock -- -- Bus clock LPO -- System clock -- -- System clock Bus clock, Flash clock -- Flash clock LPO -- Flash clock -- -- System clock -- -- Bus clock LPO -- Bus clock LPO -- Clocks Flash clock MCGOUTCLK, -- MCGPLLCLK, MCGFLLCLK, MCGIRCLK, OSCCLK, RTC OSC, IRC48MCLK Bus clock OSCERCLK, OSCCLK, -- OSCERCLK_UNDIV, OSC32KCLK -- IRC48MCLK -- Memory and memory interfaces System clock Flash clock -- Flash clock -- -- Security Bus clock -- -- Bus clock -- -- Analog Bus clock OSCERCLK , IRC48MCLK -- Bus clock -- -- Bus clock -- -- Timers Bus clock TPM clock TPM_CLKIN0, TPM_CLKIN1 Bus clock -- -- Bus clock -- -- Flash clock LPO, OSCERCLK, -- MCGIRCLK, ERCLK32K Flash clock EXTAL32 -- Communication interfaces Table continues on the next page... KS22/KS20 Microcontroller, Rev. 3, 04/2016 Module USB FS OTG DSPI LPI2C UART0, UART1 UART2 LPUART0 I2S FlexCAN FlexIO GPIO Table 4. Module clocks (continued) Bus interface clock System clock Bus clock Bus clock System clock Bus clock Bus clock Bus clock Internal clocks USB FS clock -- LPI2C clock -- -- LPUART0 clock I2S master clock Bus clock FlexCAN clock Bus clock FlexIO clock Human-machine interfaces Platform clock -- Overview I/O interface clocks -- DSPI_SCK I2C_SCL -- -- -- I2S_TX_BCLK, I2S_RX_BCLK -- -- -- 2.1.7 Security Security state can be enabled via programming flash configure field (0x40e). After enabling device security, the SWD/JTAG port cannot access the memory resources of the MCU. External interface SWD/JTAG port Security Unsecure Can't access memory source by SWD/ JTAG interface the debugger can write to the Flash Mass Erase in Progress field of the MDM-AP Control register to trigger a mass erase (Erase All Blocks) command 2.1.7.1 Flash Access Control (FAC) The FAC is a native or third-party configurable memory protection scheme optimized to allow end users to utilize software libraries while offering programmable restrictions to these libraries. The flash memory is divided into equal size segments that provide protection to proprietary software libraries. The protection of these segments is controlled as the FAC provides a cycle-by-cycle evaluation of the access rights for each transaction routed to the on-chip flash memory. Configurability allows an increasing number of protected segments while supporting two levels of vendors adding their proprietary software to a device. KS22/KS20 Microcontroller, Rev. 3, 04/2016 13 NXP Semiconductors Overview 2.1.8 Power management The Power Management Controller (PMC) expands upon ARM's operational modes of Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes can be used to optimize current consumption for a wide range of applications. The WFI or WFE instruction invokes a Wait or a Stop mode, depending on the current configuration. For more information on ARM's operational modes, See the ARM® Cortex® User Guide. The PMC provides High Speed Run (HSRUN), Normal Run (RUN), and Very Low Power Run (VLPR) configurations in ARM's Run operation mode. In these modes, the MCU core is active and can access all peripherals. The difference between the modes is the maximum clock frequency of the system and therefore the power consumption. The configuration that matches the power versus performance requirements of the application can be selected. The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in ARM's Sleep operation mode. In these modes, even though the MCU core is inactive, all of the peripherals can be enabled and operate as programmed. The difference between the modes is the maximum clock frequency of the system and therefore the power consumption. The PMC provides Stop (Stop), Very Low Power Stop (VLPS), Low Leakage Stop (LLS), and Very Low Leakage Stop (VLLS) configurations in ARM's Deep Sleep operational mode. In these modes, the MCU core and most of the peripherals are disabled. Depending on the requirements of the application, different portions of the analog, logic, and memory can be retained or disabled to conserve power. The Battery Backup mode allows the VBAT voltage domain to operate while the rest of the device is disabled to conserve power. All modules in the VBAT domain are functional in this mode of operation. The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up Interrupt Controller (AWIC), and the Low Leakage Wake-Up Controller (LLWU) are used to wake up the MCU from low power states. The NVIC is used to wake up the MCU core from WAIT and VLPW modes. The AWIC is used to wake up the MCU core from STOP and VLPS modes. The LLWU is used to wake up the MCU core from LLS and VLLSx modes. For additional information regarding operational modes, power management, the NVIC, AWIC, or the LLWU, please refer to the Reference Manual. 14 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Overview The following table provides information about the state of the peripherals in the various operational modes and the modules that can wake MCU from low power modes. Table 6. Peripherals states in different operational modes Core mode Device mode Run mode High Speed Run Run Very Low Power Run Sleep mode Wait Very Low Power Wait Deep sleep Stop Very Low Power Stop Low Leakage Stop (LLS3/LLS2) Descriptions In HSRun mode, MCU is able to operate at a faster frequency, and all device modules are operational. In Run mode, all device modules are operational. In VLPR mode, all device modules are operational at a reduced frequency except the Low Voltage Detect (LVD) monitor, which is disabled. In Wait mode, all peripheral modules are operational. The MCU core is placed into Sleep mode. In VLPW mode, all peripheral modules are operational at a reduced frequency except the Low Voltage Detect (LVD) monitor, which is disabled. The MCU core is placed into Sleep mode. In Stop mode, most peripheral clocks are disabled and placed in a static state. Stop mode retains all registers and SRAMs while maintaining Low Voltage Detection protection. In Stop mode, the ADC, DAC, CMP, LPTMR, RTC, and pin interrupts are operational. The NVIC is disabled, but the AWIC can be used to wake up from an interrupt. In VLPS mode, the contents of the SRAM are retained. The CMP (low speed), ADC, OSC, RTC, LPTMR, TPM, FlexIO, LPUART, LPI2C,USB, and DMA are operational, LVD and NVIC are disabled, AWIC is used to wake up from interrupt. State retention power mode. Most peripherals are in state retention mode (with clocks stopped), but LLWU, LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is used to wake up. Powered Off NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. In LLS3 mode, all SRAM is operating (content retained and I/O states held). In LLS2 mode, a portion of SRAM_U remains powered on (content retained and I/O states held). Very Low Leakage Stop Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer, (VLLSx) RTC, CMP, DAC can be used. NVIC is disabled; LLWU is used to wake up. In VLLS3, SRAM_U and SRAM_L remain powered on (content retained and I/O states held). In VLLS2, SRAM_L is powered off. A portion of SRAM_U remains powered on (content retained and I/O states held). In VLLS1 and VLLS0, all of SRAM_U and SRAM_L are powered off. The 32byte system register file and 32-byte VBAT register file remain powered for customer-critical data. In VLLS0, The POR detect circuit can be optionally powered off. Battery Backup The RTC and 32-byte VBAT register file are powered from the VBAT domain and is fully functional. The rest of the device is powered down. KS22/KS20 Microcontroller, Rev. 3, 04/2016 15 NXP Semiconductors Overview 2.1.9 LLWU The LLWU module is used to wake MCU from low leakage power mode (LLS and VLLSx) and functional only on entry into a low-leakage power mode. After recovery from LLS, the LLWU is immediately disabled. After recovery from VLLSx, the LLWU continues to detect wake-up events until the user has acknowledged the wake-up event. The following is internal peripheral and external pin inputs as wakeup sources to the LLWU module. Table 7. Wakeup sources for LLWU inputs Input LLWU_P0 LLWU_P1 LLWU_P2 LLWU_P3 LLWU_P4 LLWU_P5 LLWU_P6 LLWU_P7 LLWU_P8 LLWU_P9 LLWU_P10 LLWU_P11 LLWU_P12 LLWU_P13 LLWU_P14 LLWU_P15 LLWU_P16 LLWU_P17 LLWU_P18 LLWU_P19 LLWU_P20 LLWU_P21 LLWU_P22 LLWU_P23 LLWU_P24 LLWU_P25 LLWU_P26 Wakeup source PTE1/LLWU_P0 pin PTE2/LLWU_P1 pin PTE4/LLWU_P2 pin PTA4/LLWU_P3 pin1 PTA13/LLWU_P4 pin PTB0/LLWU_P5 pin PTC1/LLWU_P6 pin PTC3/LLWU_P7 pin PTC4/LLWU_P8 pin PTC5/LLWU_P9 pin PTC6/LLWU_P10 pin PTC11/LLWU_P11 pin PTD0/LLWU_P12 pin PTD2/LLWU_P13 pin PTD4/LLWU_P14 pin PTD6/LLWU_P15 pin Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved USBVDD Table continues on the next page... 16 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Overview Table 7. Wakeup sources for LLWU inputs (continued) Input LLWU_P27 LLWU_P28 LLWU_P29 LLWU_P30 LLWU_P31 LLWU_M0IF LLWU_M1IF LLWU_M2IF LLWU_M3IF LLWU_M4IF LLWU_M5IF LLWU_M6IF LLWU_M7IF Wakeup source USB0_DP USB0_DM2 Reserved Reserved Reserved LPTMR3 CMP0 Reserved Reserved Reserved RTC Alarm3 Reserved RTC Seconds3 1. If NMI was enabled on entry to LLS/VLLS, asserting the NMI pin generates an NMI interrupt on exit from the low power mode. NMI can also be disabled via the FOPT[NMI_DIS] bit. 2. As a wakeup source of LLWU, USB0_DP and USB0_DM are only available when the chip is in USB host mode. 3. It requires the peripheral and the peripheral interrupt to be enabled. The LLWU's WUME bit enables the internal module flag as a wakeup input. After wakeup, the flags are cleared based on the peripheral clearing mechanism. 2.1.10 Debug controller This device has extensive debug capabilities including run control and tracing capabilities. The standard ARM debug port supports SWD/JTAG interface. Also the cJTAG interface is supported on this device. 2.1.11 Computer operating properly (COP) watchdog timer The computer operating properly (COP) watchdog timer (WDOG) monitors the operation of the system by expecting periodic communication from the software. This communication is generally known as servicing (or refreshing) the COP watchdog. If this periodic refreshing does not occur, the watchdog issues a system reset. 2.2 Peripheral features The following sections describe the features of each peripherals of the chip. KS22/KS20 Microcontroller, Rev. 3, 04/2016 17 NXP Semiconductors Overview 2.2.1 eDMA and DMAMUX The eDMA is a highly programmable data-transfer engine optimized to minimize any required intervention from the host processor. It is intended for use in applications where the data size to be transferred is statically known and not defined within the transferred data itself. The DMA controller in this device implements 16 channels which can be routed from up to 63 DMA request sources through DMA MUX module. Main features of eDMA are listed below: · All data movement via dual-address transfers: read from source, write to destination · 16-channel implementation that performs complex data transfers with minimal intervention from a host processor · Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations · Channel activation via one of three methods · Fixed-priority and round-robin channel arbitration · Channel completion reported via programmable interrupt requests · Programmable support for scatter/gather DMA processing · Support for complex data structures 2.2.2 TPM This device contains three low power Timer/PWM Modules (TPM), one with 6 channels and the other two with 2 channels. All TPM modules are functional in Stop/ VLPS mode if the clock source is enabled. The TPM features are as follows: · TPM clock mode is selectable (can increment on every edge of the asynchronous counter clock, or only on on rising edge of an external clock input synchronized to the asynchronous counter clock) · Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 · Include a 16-bit counter · Include 6 or 2 channels (1×6ch, 2×2ch) that can be configured for input capture, output compare, edge-aligned PWM mode, or center-aligned PWM mode · Support the generation of an interrupt and/or DMA request per channel or counter overflow 18 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Overview · Support selectable trigger input to optionally reset or cause the counter to start or stop incrementing · Support the generation of hardware triggers when the counter overflows and per channel 2.2.3 ADC This device contains one ADC module. This ADC module supports hardware triggers from TPM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports wakeup of MCU in low power mode when using internal clock source or external crystal clock. ADC module has the following features: · Linear successive approximation algorithm with up to 16-bit resolution · Up to four pairs of differential and 17 single-ended external analog inputs · Support selectable 16-bit, 13-bit, 11-bit, and 9-bit differential output mode, or 16bit, 12-bit, 10-bit, and 8-bit single-ended output modes · Single or continuous conversion · Configurable sample time and conversion speed/power · Selectable clock source up to three · Operation in low-power modes for lower noise · Asynchronous clock source for lower noise operation with option to output the clock · Selectable hardware conversion trigger · Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value · Temperature sensor · Hardware average function up to 32× · Voltage reference: from external · Self-calibration mode 2.2.3.1 Temperature sensor This device contains one temperature sensor internally connected to the input channel of AD26, see Table 66 for details of the linearity factor. The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031. KS22/KS20 Microcontroller, Rev. 3, 04/2016 19 NXP Semiconductors Overview 2.2.4 DAC The 12-bit digital-to-analog converter (DAC) is a low-power, general-purpose DAC. The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator, or ADC. DAC module has the following features: · On-chip programmable reference generator output. The voltage output range is from 1/4096 Vin to Vin, and the step is 1/4096 Vin, where Vin is the input voltage. · Vin can be selected from the reference source VDDA · Static operation in Normal Stop mode · 16-word data buffer supported with multiple operation modes · DMA support 2.2.5 CMP The device contains one high-speed comparator and two 8-input multiplexers for both the inverting and non-inverting inputs of the comparator. Each CMP input channel connects to both muxes. The CMP includes one 6-bit DAC, which provides a selectable voltage reference for various user application cases. Besides, the CMP also has several module-to-module interconnects in order to facilitate ADC triggering, TPM triggering, and interfaces. The CMP has the following features: · Inputs may range from rail to rail · Programmable hysteresis control · Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator output · Selectable inversion on comparator output · Capability to produce a wide range of outputs such as sampled, digitally filtered · External hysteresis can be used at the same time that the output filter is used for internal functions · Two software selectable performance levels: shorter propagation delay at the expense of higher power and Low power with longer propagation delay · DMA transfer support · Functional in all modes of operation except in VLLS0 mode · The filter functions are not available in Stop, VLPS, LLS, or VLLSx modes · Integrated 6-bit DAC with selectable supply reference source and can be power down to conserve power · Two 8-to-1 channel mux 20 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Overview 2.2.6 RTC The RTC is an always powered-on block that remains active in all low power modes. The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an external crystal using the RTC oscillator. RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all RTC registers. The RTC module has the following features · 32-bit seconds counter with roll-over protection and 32-bit alarm · 16-bit prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm · Register write protection with register lock mechanism · 1 Hz square wave or second pulse output with optional interrupt 2.2.7 PIT The Periodic Interrupt Timer (PIT) is used to generate periodic interrupt to the CPU. It has four independent channels and each channel has a 32-bit counter. Both channels can be chained together to form a 64-bit counter. Channel 0 can be used to periodically trigger DMA channel 0, and channel 1 can be used to periodically trigger DMA channel 1. Either channel can be programmed as an ADC trigger source, or TPM trigger source. Channel 0 can be programmed to trigger DAC. The PIT module has the following features: · Each 32-bit timers is able to generate DMA trigger · Each 32-bit timers is able to generate timeout interrupts · Two timers can be cascaded to form a 64-bit timer · Each timer can be programmed as ADC/TPM trigger source 2.2.8 PDB The Programmable Delay Block (PDB) provides controllable delays from either an internal or an external trigger, or a programmable interval tick, to the hardware trigger inputs of ADCs and/or generates the interval triggers to DACs, so that the precise KS22/KS20 Microcontroller, Rev. 3, 04/2016 21 NXP Semiconductors Overview timing between ADC conversions and/or DAC updates can be achieved. The PDB can optionally provide pulse outputs (Pulse-Out's) that are used as the sample window in the CMP block. The PIT module has the following features: · Up to 15 trigger input sources and one software trigger source · Up to 8 configurable PDB channels for ADC hardware trigger · Up to 8 pulse outputs (pulse-out's) 2.2.9 LPTMR The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter. The LPTMR module has the following features: · 16-bit time counter or pulse counter with compare · Optional interrupt can generate asynchronous wakeup from any low-power mode · Hardware trigger output · Counter supports free-running mode or reset on compare · Configurable clock source for prescaler/glitch filter · Configurable input source for pulse counter 2.2.10 CRC This device contains one cyclic redundancy check (CRC) module which can generate 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard. The CRC module has the following features: · Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift register · Programmable initial seed value and polynomial · Option to transpose input data or output data (the CRC result) bitwise or bytewise. · Option for inversion of final CRC result · 32-bit CPU register programming interface 22 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Overview 2.2.11 UART This device contains 3 basic universal asynchronous receiver/transmitter (UART) modules with DMA function supported. Generally, this module is used in RS-232, RS-485, and other communications. It also supports LIN slave operation and ISO7816. The UART module has the following features: · Full-duplex operation · 13-bit baud rate selection with /32 fractional divide, based on the module clock frequency · Programmable 8-bit or 9-bit data format · Programmable transmitter output polarity · Programmable receive input polarity · Up to 14-bit break character transmission. · 11-bit break character detection option · Two receiver wakeup methods with idle line or address mark wakeup · Address match feature in the receiver to reduce address mark wakeup ISR overhead · Ability to select MSB or LSB to be the first bit on wire · UART0 supporting ISO-7816 protocol to interface with SIM cards and smart cards · Receiver framing error detection · Hardware parity generation and checking · 1/16 bit-time noise detection · DMA interface 2.2.12 LPUART This device contains one Low-Power UART module, and can work in Stop and VLPS modes. The module also supports 4× to 32× data oversampling rate to meet different applications. The LPUART module has the following features: · Programmable baud rates (13-bit modulo divider) with configurable oversampling ratio from 4× to 32× · Transmit and receive baud rate can operate asynchronous to the bus clock and can be configured independently of the bus clock frequency, support operation in Stop mode KS22/KS20 Microcontroller, Rev. 3, 04/2016 23 NXP Semiconductors Overview · Interrupt, DMA or polled operation · Hardware parity generation and checking · Programmable 8-bit, 9-bit or 10-bit character length · Programmable 1-bit or 2-bit stop bits · Three receiver wakeup methods · Idle line wakeup · Address mark wakeup · Receive data match · Automatic address matching to reduce ISR overhead: · Address mark matching · Idle line address matching · Address match start, address match end · Optional 13-bit break character generation / 11-bit break character detection · Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle characters · Selectable transmitter output and receiver input polarity 2.2.13 SPI This device contains two SPI modules. The SPI module provides a synchronous serial bus for communication between a chip and an external peripheral device. The SPI modules have the following features: · Full-duplex, three-wire synchronous transfers · Master mode, or slave mode · Data streaming operation in Slave mode with continuous slave selection · Buffered transmit/receive operation using the transmit/receive first in first out (TX/RX FIFO) with depth of 4 entries · Programmable transfer attributes on a per-frame basis · Multiple peripheral chip select (PCS) (6 PCS available for SPI0 and 4 PCS for SPI1), expandable to 64 with external demultiplexer · Deglitching support for up to 32 peripheral chip selects (PCSes) with external demultiplexer · DMA support for adding entries to TX FIFO and removing entries from RX FIFO · Global interrupt request line · Modified SPI transfer formats for communication with slower peripheral devices · Power-saving architectural features 24 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Overview 2.2.14 FlexCAN For KS22, the device contains two FlexCAN modules. For KS20, it has only one FlexCAN module. The FlexCAN module is a communication controller implementing the CAN protocol according to the ISO 11898-1 standard and CAN 2.0 B protocol specifications. The FlexCAN module contains 16 message buffers. Each message buffer is 16 bytes. The FlexCAN module has the following features: · Flexible mailboxes of zero to eight bytes data length · Each mailbox configurable as receive or transmit, all supporting standard and extended messages · Individual Rx Mask registers per mailbox · Full-featured Rx FIFO with storage capacity for up to six frames and automatic internal pointer handling with DMA support · Transmission abort capability · Programmable clock source to the CAN Protocol Interface, either peripheral clock or oscillator clock · RAM not used by reception or transmission structures can be used as general purpose RAM space · Listen-Only mode capability · Programmable Loop-Back mode supporting self-test operation · Programmable transmission priority scheme: lowest ID, lowest buffer number, or highest priority · Time stamp based on 16-bit free-running timer · Global network time, synchronized by a specific message · Maskable interrupts · Independence from the transmission medium (an external transceiver is assumed) · Short latency time due to an arbitration scheme for high-priority messages · Low power modes, with programmable wake up on bus activity · Remote request frames may be handled automatically or by software · CAN bit time settings and configuration bits can only be written in Freeze mode · Tx mailbox status (Lowest priority buffer or empty buffer) · Identifier Acceptance Filter Hit Indicator (IDHIT) register for received frames · SYNCH bit available in Error in Status 1 register to inform that the module is synchronous with CAN bus · CRC status for transmitted message · Rx FIFO Global Mask register KS22/KS20 Microcontroller, Rev. 3, 04/2016 25 NXP Semiconductors Overview · Selectable priority between mailboxes and Rx FIFO during matching process · Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either 128 extended, 256 standard, or 512 partial (8 bit) IDs, with up to 32 individual masking capability 2.2.15 LPI2C This device contains two LPI2C modules. The LPI2C is a low power Inter-Integrated Circuit (I2C) module that supports an efficient interface to an I2C bus as a master and/or a slave. The LPI2C can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses. The LPI2C implements logic support for standardmode, fast-mode, fast-mode plus and ultra-fast modes of operation. The LPI2C module also complies with the System Management Bus (SMBus) Specification, version 2. The LPI2C modules have the following features: · Standard, Fast, Fast+ and Ultra Fast modes are supported · HS-mode supported in slave mode · Multi-master support including synchronization and arbitration · Clock stretching · General call, 7-bit and 10-bit addressing · Software reset, START byte and Device ID require software support · For master mode: · command/transmit FIFO of 4 words · receive FIFO of 4 words · For slave mode: · separate I2C slave registers to minimize software overhead due to master/slave switching · support for 7-bit or 10-bit addressing, address range, SMBus alert and general call address · transmit/receive data register supporting interrupt or DMA requests 2.2.16 USB This device contains one USB module which implements a USB2.0 full-speed compliant peripheral and interfaces to the on-chip USBFS transceiver. It enables IRC48M to allow crystal-less USB operation. The USBFS has the following features: 26 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Overview · USB 1.1 and 2.0 compliant full-speed device controller · 16 bidirectional end points · DMA or FIFO data stream interfaces · Low-power consumption · IRC48M with clock-recovery is supported to eliminate the 48 MHz crystal. It is used for USB device-only implementation. 2.2.17 I2S The I2S module provides a synchronous audio interface (SAI), which can be clocked by bus clock, PLL/FLL output clock or external oscillator clock. The module supports asynchronous bit clocks (BCLKs) that can be generated internally from the audio master clock or supplied externally. And also supports the option for synchronous operation between the receiver and transmitter. And it can be functional in stop or very low power mode. I2S module has the following features: · Transmitter with independent bit clock and frame sync supporting 1 data channel · Receiver with independent bit clock and frame sync supporting 1 data channel · Maximum frame size of 16 words · Word size of between 8-bits and 32-bits · Word size configured separately for first word and remaining words in frame · Asynchronous 8 × 32-bit FIFO for each transmit and receive channels · Supports graceful restart after FIFO error · Supports automatic restart after FIFO error without software intervention · Supports packing of 8-bit and 16-bit data into each 32-bit FIFO word 2.2.18 FlexIO The FlexIO is a highly configurable module providing a wide range of protocols including, but not limited to UART, I2C, SPI, I2S, and PWM/Waveform generation. The module supports programmable baud rates independent of bus clock frequency, with automatic start/stop bit generation. The FlexIO module has the following features: · Functional in VLPR/VLPW/Stop/VLPS mode provided the clock it is using remains enabled · Four 32-bit double buffered shift registers with transmit, receive, and data match modes, and continuous data transfer KS22/KS20 Microcontroller, Rev. 3, 04/2016 27 NXP Semiconductors Overview · The timing of the shifter's shift, load and store events are controlled by the highly flexible 16-bit timer assigned to the shifter · Two or more shifters can be concatenated to support large data transfer sizes · Each 16-bit timers operates independently, supports for reset, enable and disable on a variety of internal or external trigger conditions with programmable trigger polarity · Flexible pin configuration supporting output disabled, open drain, bidirectional output data and output mode · Supports interrupt, DMA or polled transmit/receive operation 2.2.19 Port control and GPIO The Port Control and Interrupt (PORT) module provides support for port control, digital filtering, and external interrupt functions. The GPIO data direction and output data registers control the direction and output data of each pin when the pin is configured for the GPIO function. The GPIO input data register displays the logic value on each pin when the pin is configured for any digital function, provided the corresponding Port Control and Interrupt module for that pin is enabled. The following figure shows the basic I/O pad structure. This diagram applies to all I/O pins except RESET_b and those configured as pseudo open-drain outputs. RESET_b is a true open-drain pin without p-channel output driver or diode to the ESD bus. Pseudo open-drain pins have the p-channel output driver disabled when configured for opendrain operation. None of the I/O pins, including open-drain and pseudo open-drain pins, are allowed to go above VDD. 28 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Digital input IBE=1 whenever MUX000 PFE IBE LPF ESD Bus MUX VDD PE RPULL PS Analog input Digital output DSE SRE Overview Figure 4. I/O simplified block diagram The PORT module has the following features: · all PIN support interrupt enable · Configurable edge (rising, falling, or both) or level sensitive interrupt type · Support DMA request · Asynchronous wake-up in low-power modes · Configurable pullup, pulldown, and pull-disable on select pins · Configurable high and low drive strength on selected pins · Configurable fast and slow slew rates on selected pins · Configurable passive filter on selected pins · Individual mux control field supporting analog or pin disabled, GPIO, and up to chip-specific digital functions · Pad configuration fields are functional in all digital pin muxing modes. The GPIO module has the following features: · Port Data Input register visible in all digital pin-multiplexing modes · Port Data Output register with corresponding set/clear/toggle registers KS22/KS20 Microcontroller, Rev. 3, 04/2016 29 NXP Semiconductors Memory map · Port Data Direction register · GPIO support single-cycle access via fast GPIO. 3 Memory map This device contains various memories and memory-mapped peripherals which are located in a 4 GB memory space. For more details of the system memory and peripheral locations, see the Memory Map chapter in the Reference Manual. 0x0000_0000 Flash 0x0000_0000 Code space 0x0800_0000 Reserved 0x07FF_FFFF note: take 256 KB flash memory as an example 0x1C00_0000 Data space 0x1C00_0000 SRAM_L 0x2010_0000 0x2000_0000 SRAM_U 0x4000_0000 Reserved * 0x200F_FFFF note: 0x2200_00000x23FF_FFFF: Aliased to SRAM_U bitband 0x3000_00000x33FF_FFF: Program Flash and read only data 0x4010_0000 0xE000_0000 Public peripherals Reserved * 0x4000_0000 AIPS 0x4007_FFFF peripherals 0x4008_0000 0x400F_EFFF Reserved note: 0x4200_00000x42FF_FFFF GPIO : Aliased to peripheral bridge (AIPS-lite) bitband 0x43FE_00000x43FF_FFFF : Aliased to general purpose input/output(GPIO) bitband 0x400F_F000 0x400F_FFFF Private Peripheral Bus (PPB) * 0xFFFF_FFFF note: 0xE000_00000xE000_0FFF: Instrumentation Trace Macrocell (ITM) 0xE000_10000xE000_1FFF: Data Watchpoint and Trace (DWT) 0xE000_20000xE000_2FFF: Flash Patch and Breakpoint (FPB) 0xE000_30000xE000_DFFF: Reserved 0xE000_E0000xE000_EFFF: System Control Space (SCS) (for NVIC and FPU) 0xE000_F0000xE003_FFFF: Reserved 0xE004_00000xE004_0FFF: Trace Port Interface Unit (TPIU) 0xE004_10000xE004_1FFF: Reserved 0xE004_20000xE004_2FFF: Reserved 0xE004_30000xE004_3FFF: Reserved 0xE004_40000xE007_FFFF: Reserved 0xE008_00000xE008_0FFF: Miscellaneous Control Module (MCM) 0xE008_10000xE008_1FFF: Reserved 0xE008_20000xE00F_EFFF: Reserved 0xE00F_F0000xE00F_FFFF: ROM Table - allows auto-detection of debug components 0xE010_00000xFFFF_FFFF: Reserved 0x4000_0000 0x4000_8000 0x4000_9000 0x4000_A000 0x4001_F000 0x4002_0000 0x4002_1000 0x4002_2000 0x4002_4000 0x4002_5000 0x4002_6000 0x4002_9000 0x4002_A000 0x4002_B000 0x4002_C000 0x4002_D000 0x4002_E000 0x4002_F000 0x4003_0000 0x4003_1000 0x4003_2000 0x4003_3000 0x4003_6000 0x4003_7000 0x4003_8000 0x4003_9000 0x4003_A000 0x4003_B000 0x4003_C000 0x4003_D000 0x4003_E000 0x4003_F000 0x4004_0000 0x4004_1000 0x4004_2000 0x4004_7000 0x4004_8000 0x4004_9000 0x4004_A000 0x4004_B000 0x4004_C000 0x4004_D000 0x4004_E000 0x4005_2000 0x4005_3000 0x4005_F000 0x4006_0000 0x4006_1000 0x4006_2000 0x4006_4000 0x4006_5000 0x4006_6000 0x4006_7000 0x4006_8000 0x4006_A000 0x4006_B000 0x4006_C000 0x4006_D000 0x4007_2000 0x4007_3000 0x4007_4000 0x4007_C000 0x4007_D000 0x4007_E000 0x4007_F000 0x4007_FFFF Reserved DMA controller DMA controller transfer control descriptors Reserved Flash memory controller (FMC) Flash memory DMA channel mutiplexer Reserved FlexCAN 0 FlexCAN 1 (only for KS22) Reserved Random Number Generator (RNGA) LPUART 0 Reserved SPI 0 SPI 1 Reserved I2S 0 I2S 1 Reserved CRC Reserved Programmable delay block (PDB) Periodic interrupt timers (PIT) TPM 0 TPM 1 TPM 2 ADC 0 Reserved Real-time clock (RTC) VBAT register file DAC 0 Low-power timer (LPTMR) System register file Reserved SIM low-power logic System integration module (SIM) Port A multiplexing control Port B multiplexing control Port C multiplexing control Port D multiplexing control Port E multiplexing control Reserved Software watchdog Reserved FlexIO Reserved External watchdog Reserved Multi-purpose Clock Generator (MCG) System oscillator (OSC) LPI2C 0 LPI2C 1 Reserved UART 0 UART 1 UART 2 Reserved USB Full Speed OTG Controller CMP (with 6-bit DAC) Reserved Low-leakage wakeup unit (LLWU) Power management controller (PMC) System Mode controller (SMC) Reset Control Module (RCM) Figure 5. Memory map 30 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Pinouts 4 Pinouts 4.1 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE For KS20, only CAN0 exists. For KS22, there are two instances of CAN module (CAN0 and CAN1). 100 64 48 Pin Name LQFP LQFP QFN 1 1 1 PTE0/ CLKOUT32K 2 2 2 PTE1/ LLWU_P0 3 -- 3 PTE2/ LLWU_P1 4 -- 4 PTE3 Default ADC0_SE4a ADC0_SE5a ADC0_SE6a ADC0_SE7a ALT0 ADC0_SE4a ADC0_SE5a ADC0_SE6a ADC0_SE7a ALT1 PTE0/ CLKOUT32K PTE1/ LLWU_P0 PTE2/ LLWU_P1 PTE3 ALT2 SPI1_PCS1 SPI1_SOUT SPI1_SCK SPI1_SIN 5 -- 5 PTE4/ DISABLED LLWU_P2 6 -- 6 PTE5 DISABLED PTE4/ LLWU_P2 PTE5 SPI1_PCS0 SPI1_PCS2 7 -- -- PTE6 DISABLED PTE6 SPI1_PCS3 8 3 7 VDD VDD VDD 9 4 8 VSS VSS VSS 10 5 9 USB0_DP USB0_DP USB0_DP 11 6 10 USB0_DM USB0_DM USB0_DM 12 7 11 USBVDD USBVDD USBVDD 13 -- -- NC NC NC 14 8 -- ADC0_DP1 ADC0_DP1 ADC0_DP1 15 -- -- ADC0_DM1 ADC0_DM1 ADC0_DM1 16 -- -- ADC0_DP2 ADC0_DP2 ADC0_DP2 17 -- -- ADC0_DM2 ADC0_DM2 ADC0_DM2 18 9 -- ADC0_DP0 ADC0_DP0 ADC0_DP0 19 10 -- ADC0_DM0 ADC0_DM0 ADC0_DM0 20 11 -- ADC0_DP3 ADC0_DP3 ADC0_DP3 ALT3 UART1_TX UART1_RX UART1_ CTS_b UART1_ RTS_b LPUART0_ TX LPUART0_ RX LPUART0_ CTS_b ALT4 I2S0_MCLK ALT5 ALT6 ALT7 LPI2C1_SDA RTC_ CLKOUT LPI2C1_SCL SPI1_SIN SPI1_SOUT LPI2C1_SDA LPI2C1_SCL USB_SOF_ OUT KS22/KS20 Microcontroller, Rev. 3, 04/2016 31 NXP Semiconductors Pinouts 100 64 48 Pin Name LQFP LQFP QFN 21 12 -- ADC0_DM3 22 13 12 VDDA 23 14 12 VREFH 24 15 13 VREFL 25 16 13 VSSA 26 17 -- CMP0_IN5 27 18 -- DAC0_OUT/ ADC0_SE23 28 19 14 XTAL32 29 20 15 EXTAL32 30 21 16 VBAT 31 -- -- PTE24 32 -- -- PTE25 Default ADC0_DM3 VDDA VREFH VREFL VSSA CMP0_IN5 DAC0_OUT/ ADC0_SE23 XTAL32 EXTAL32 VBAT ADC0_SE17 ADC0_SE18 ALT0 ADC0_DM3 VDDA VREFH VREFL VSSA CMP0_IN5 DAC0_OUT/ ADC0_SE23 XTAL32 EXTAL32 VBAT ADC0_SE17 ADC0_SE18 ALT1 PTE24 PTE25 ALT2 CAN1_TX CAN1_RX ALT3 TPM0_CH0 TPM0_CH1 33 -- -- PTE26/ DISABLED CLKOUT32K 34 22 17 PTA0 JTAG_TCLK/ SWD_CLK 35 23 18 PTA1 JTAG_TDI PTE26/ CLKOUT32K PTA0 UART0_ CTS_b PTA1 UART0_RX TPM0_CH5 36 24 19 PTA2 JTAG_TDO/ TRACE_ SWO 37 25 20 PTA3 JTAG_TMS/ SWD_DIO 38 26 21 PTA4/ NMI_b LLWU_P3 39 27 -- PTA5 DISABLED PTA2 UART0_TX PTA3 PTA4/ LLWU_P3 PTA5 UART0_ RTS_b TPM0_CH0 TPM0_CH1 USB_CLKIN TPM0_CH2 40 -- -- VDD VDD VDD 41 -- -- VSS VSS VSS 42 28 -- PTA12 DISABLED 43 29 -- PTA13/ DISABLED LLWU_P4 44 -- -- PTA14 DISABLED PTA12 PTA13/ LLWU_P4 PTA14 CAN0_TX CAN0_RX TPM1_CH0 TPM1_CH1 SPI0_PCS0 UART0_TX 45 -- -- PTA15 46 -- -- PTA16 47 -- -- PTA17 48 30 22 VDD 49 31 23 VSS 50 32 24 PTA18 DISABLED PTA15 DISABLED PTA16 DISABLED PTA17 VDD VDD VSS VSS EXTAL0 EXTAL0 PTA18 SPI0_SCK SPI0_SOUT SPI0_SIN UART0_RX UART0_ CTS_b UART0_ RTS_b ALT4 ALT5 ALT6 ALT7 I2S1_TX_FS I2S1_TX_ BCLK I2S1_TXD0 CMP0_OUT LPI2C0_SCL EWM_OUT_b LPI2C0_SDA EWM_IN EWM_IN LPI2C1_ HREQ RTC_ CLKOUT TPM1_CH1 TPM1_CH0 EWM_OUT_b I2S0_MCLK USB_CLKIN JTAG_TCLK/ SWD_CLK JTAG_TDI JTAG_TDO/ TRACE_ SWO JTAG_TMS/ SWD_DIO NMI_b I2S0_TX_ BCLK JTAG_TRST_ b I2S0_TXD0 I2S0_TX_FS I2S0_RX_ BCLK I2S0_RXD0 I2S0_RX_FS I2S0_MCLK TPM_CLKIN0 32 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Pinouts 100 64 48 Pin Name LQFP LQFP QFN 51 33 25 PTA19 Default XTAL0 ALT0 XTAL0 ALT1 PTA19 52 34 26 RESET_b RESET_b RESET_b 53 35 27 PTB0/ ADC0_SE8 ADC0_SE8 PTB0/ LLWU_P5 LLWU_P5 54 36 28 PTB1 ADC0_SE9 ADC0_SE9 PTB1 55 37 29 PTB2 ADC0_SE12 ADC0_SE12 PTB2 56 38 30 PTB3 ADC0_SE13 ADC0_SE13 PTB3 57 -- -- PTB9 DISABLED PTB9 58 -- -- PTB10 DISABLED PTB10 59 -- -- PTB11 DISABLED PTB11 60 -- -- VSS VSS VSS 61 -- -- VDD VDD VDD 62 39 31 PTB16 DISABLED PTB16 63 40 -- PTB17 DISABLED PTB17 64 41 32 PTB18 DISABLED PTB18 65 42 33 PTB19 66 -- -- PTB20 67 -- -- PTB21 68 -- -- PTB22 69 -- -- PTB23 70 43 -- PTC0 DISABLED PTB19 DISABLED PTB20 DISABLED PTB21 DISABLED PTB22 DISABLED PTB23 ADC0_SE14 ADC0_SE14 PTC0 71 44 34 PTC1/ ADC0_SE15 ADC0_SE15 PTC1/ LLWU_P6 LLWU_P6 72 45 35 PTC2 ADC0_SE4b ADC0_SE4b PTC2 73 46 36 PTC3/ DISABLED LLWU_P7 74 47 -- VSS VSS VSS 75 48 -- VDD VDD VDD 76 49 37 PTC4/ DISABLED LLWU_P8 77 50 38 PTC5/ DISABLED LLWU_P9 PTC3/ LLWU_P7 PTC4/ LLWU_P8 PTC5/ LLWU_P9 ALT2 ALT3 ALT4 ALT5 TPM_CLKIN1 LPI2C0_SCL TPM1_CH0 LPI2C0_SDA TPM1_CH1 LPI2C0_SCL UART0_ RTS_b LPI2C0_SDA UART0_ CTS_b SPI1_PCS1 LPUART0_ CTS_b SPI1_PCS0 LPUART0_ RX SPI1_SCK LPUART0_ TX EWM_IN I2S1_TX_ BCLK I2S1_TX_FS SPI1_SOUT UART0_RX TPM_CLKIN0 SPI1_SIN CAN0_TX CAN0_RX UART0_TX TPM2_CH0 TPM2_CH1 TPM_CLKIN1 I2S0_TX_ BCLK I2S0_TX_FS SPI0_PCS4 SPI0_PCS3 SPI0_PCS2 SPI0_PCS1 SPI0_PCS5 PDB0_ EXTRG UART1_ RTS_b UART1_ CTS_b UART1_RX USB_SOF_ OUT TPM0_CH0 TPM0_CH1 TPM0_CH2 CLKOUT SPI0_PCS0 UART1_TX TPM0_CH3 SPI0_SCK LPTMR0_ ALT2 I2S0_RXD0 ALT6 ALT7 LPTMR0_ ALT1 FXIO0_D4 UART0_RX FXIO0_D5 FXIO0_D6 UART0_TX CAN1_RX FXIO0_D7 CAN1_TX EWM_IN I2S1_TXD0 (Note: 100LQFP only) EWM_OUT_b FXIO0_D0 FXIO0_D1 CMP0_OUT FXIO0_D5 FXIO0_D6 FXIO0_D7 FXIO0_D3 FXIO0_D2 FXIO0_D4 SPI0_PCS0 I2S0_TXD0 I2S0_TX_FS I2S0_TX_ BCLK LPUART0_ RTS_b LPUART0_ CTS_b LPUART0_ RX LPI2C0_ HREQ CMP0_OUT LPUART0_ TX TPM0_CH2 KS22/KS20 Microcontroller, Rev. 3, 04/2016 33 NXP Semiconductors Pinouts 100 64 48 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP LQFP QFN 78 51 39 PTC6/ CMP0_IN0 CMP0_IN0 PTC6/ SPI0_SOUT PDB0_ LLWU_P10 LLWU_P10 EXTRG I2S0_RX_ BCLK I2S0_MCLK LPI2C0_SCL 79 52 40 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_ I2S0_RX_FS OUT LPI2C0_SDA 80 53 -- PTC8 CMP0_IN2 CMP0_IN2 PTC8 LPI2C0_ SCLS I2S0_MCLK FXIO0_D0 I2S1_RXD0 81 54 -- PTC9 CMP0_IN3 CMP0_IN3 PTC9 LPI2C0_ SDAS I2S0_RX_ BCLK FXIO0_D1 I2S1_RX_ BCLK 82 55 -- PTC10 DISABLED PTC10 LPI2C1_SCL I2S0_RX_FS FXIO0_D2 I2S1_RX_FS 83 56 -- PTC11/ DISABLED LLWU_P11 PTC11/ LPI2C1_SDA LLWU_P11 FXIO0_D3 I2S1_MCLK 84 -- -- PTC12 DISABLED PTC12 LPI2C1_ SCLS TPM_CLKIN0 FXIO0_D0 85 -- -- PTC13 DISABLED PTC13 LPI2C1_ SDAS TPM_CLKIN1 FXIO0_D1 86 -- -- PTC14 DISABLED PTC14 LPUART0_ RTS_b FXIO0_D2 87 -- -- PTC15 DISABLED PTC15 LPUART0_ CTS_b FXIO0_D3 88 -- -- VSS VSS VSS 89 -- -- VDD VDD VDD 90 -- -- PTC16 DISABLED PTC16 CAN1_RX LPUART0_ RX FXIO0_D4 91 -- -- PTC17 DISABLED PTC17 CAN1_TX LPUART0_ TX FXIO0_D5 92 -- -- PTC18 DISABLED PTC18 LPUART0_ RTS_b 93 57 41 PTD0/ DISABLED LLWU_P12 PTD0/ SPI0_PCS0 UART2_ LLWU_P12 RTS_b LPUART0_ FXIO0_D6 RTS_b 94 58 42 PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK UART2_ CTS_b LPUART0_ FXIO0_D7 CTS_b 95 59 43 PTD2/ DISABLED LLWU_P13 PTD2/ SPI0_SOUT UART2_RX LLWU_P13 LPUART0_ LPI2C0_SCL RX 96 60 44 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX LPUART0_ LPI2C0_SDA TX 97 61 45 PTD4/ DISABLED LLWU_P14 PTD4/ SPI0_PCS1 UART0_ LLWU_P14 RTS_b TPM0_CH4 EWM_IN SPI1_PCS0 98 62 46 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_ CTS_b TPM0_CH5 EWM_OUT_b SPI1_SCK 99 63 47 PTD6/ ADC0_SE7b ADC0_SE7b PTD6/ SPI0_PCS3 UART0_RX LLWU_P15 LLWU_P15 SPI1_SOUT 100 64 48 PTD7 DISABLED PTD7 UART0_TX SPI1_SIN 34 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Pinouts 4.2 Pin properties The following table lists the pin properties. 100LQF 64LQFP 48QFN P Pin Name Driver Strength Default Status after POR Pull-up/ pulldown Setting after POR Slew Rate after POR 1 1 1 PTE0/ ND Hi-Z - FS CLKOUT 32K 2 2 2 PTE1/ ND Hi-Z - FS LLWU_P 0 3 3 PTE2/ ND Hi-Z - FS LLWU_P 1 4 4 PTE3 ND Hi-Z - FS 5 5 PTE4/ ND Hi-Z - FS LLWU_P 2 6 6 PTE5 ND Hi-Z - FS 7 PTE6 ND Hi-Z - FS 8 3 7 VDD - - - - 9 4 8 VSS - - - - 9 4 9 VSS - - - - 10 5 10 USB0_D - Hi-Z - - P 11 6 11 USB0_D - Hi-Z - - M 12 7 USBVDD - - - - 13 NC - - - - 14 8 ADC0_D - Hi-Z - - P1 15 ADC0_D - Hi-Z - - M1 16 ADC0_D - Hi-Z - - P2 17 ADC0_D - Hi-Z - - M2 18 9 ADC0_D - Hi-Z - - P0 19 10 ADC0_D - Hi-Z - - M0 Table continues on the next page... Passive Pin Filter after POR Open Drain N N N N N N N N N N N N N N - - - - - - - - - - - - - - - - - - - - - - - - - - Pin Interrupt Y Y Y Y Y Y Y - KS22/KS20 Microcontroller, Rev. 3, 04/2016 35 NXP Semiconductors Pinouts 100LQF 64LQFP 48QFN P Pin Name Driver Strength Default Status after POR Pull-up/ pulldown Setting after POR Slew Rate after POR 20 11 ADC0_D - Hi-Z - - P3 21 12 ADC0_D - Hi-Z - - M3 22 13 12 VDDA - - - - 23 14 12 VREFH - Hi-Z - - 24 15 13 VREFL - Hi-Z - - 25 16 13 VSSA - Hi-Z - - 26 17 CMP0_IN - Hi-Z - - 5 27 18 DAC0_O - Hi-Z - - UT/ ADC0_S E23 28 19 14 XTAL32 - Hi-Z - - 29 20 15 EXTAL32 - Hi-Z - - 30 21 16 VBAT - - - - 31 PTE24 ND Hi-Z - FS 32 PTE25 ND Hi-Z - FS 33 PTE26/ ND Hi-Z - FS CLKOUT 32K 34 22 17 PTA0 ND L PD FS 35 23 18 PTA1 ND H PU FS 36 24 19 PTA2 ND H PU FS 37 25 20 PTA3 ND H PU FS 38 26 21 PTA4/ ND H LLWU_P 3 PU FS 39 27 PTA5 ND Hi-Z - FS 40 VDD - - - - 41 VSS - - - - 42 28 PTA12 ND Hi-Z - FS 43 29 PTA13/ ND Hi-Z - FS LLWU_P 4 44 PTA14 ND Hi-Z - FS 45 PTA15 ND Hi-Z - FS 46 PTA16 ND Hi-Z - FS Table continues on the next page... Passive Pin Filter after POR Open Drain - - - - - - - - - - - - - - - - - - - - - - N N N N N N N N N N N N N N N N N N - - - - N N N N N N N N N N Pin Interrupt - - - - Y Y Y Y Y Y Y Y Y Y Y Y Y Y 36 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Pinouts 100LQF 64LQFP 48QFN P Pin Name Driver Strength Default Status after POR Pull-up/ pulldown Setting after POR Slew Rate after POR 47 PTA17 ND Hi-Z - FS 48 30 22 VDD - - - - 49 31 23 VSS - - - - 50 32 24 PTA18 ND Hi-Z - FS 51 33 25 PTA19 ND Hi-Z - FS 52 34 26 RESET_ - b H PU - 53 35 27 PTB0/ HD Hi-Z - FS LLWU_P 5 54 36 28 PTB1 HD Hi-Z - FS 55 37 29 PTB2 ND Hi-Z - FS 56 38 30 PTB3 ND Hi-Z - FS 57 PTB9 ND Hi-Z - FS 58 PTB10 ND Hi-Z - FS 59 PTB11 ND Hi-Z - FS 60 VSS - - - - 61 VDD - - - - 62 39 31 PTB16 ND Hi-Z - FS 63 40 PTB17 ND Hi-Z - FS 64 41 32 PTB18 ND Hi-Z - FS 65 42 33 PTB19 ND Hi-Z - FS 66 PTB20 ND Hi-Z - FS 67 PTB21 ND Hi-Z - FS 68 PTB22 ND Hi-Z - FS 69 PTB23 ND Hi-Z - FS 70 43 PTC0 ND Hi-Z - FS 71 44 34 PTC1/ ND Hi-Z - FS LLWU_P 6 72 45 35 PTC2 ND Hi-Z - FS 73 46 36 PTC3/ HD Hi-Z - FS LLWU_P 7 74 47 VSS - - - - 75 48 VDD - - - - Table continues on the next page... Passive Pin Filter after POR Open Drain N N - - - - N N N N Y N N N N N N N N N N N N N N N - - - - N N N N N N N N N N N N N N N N N N N N N N N N - - - - Pin Interrupt Y Y Y - Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y - KS22/KS20 Microcontroller, Rev. 3, 04/2016 37 NXP Semiconductors Pinouts 100LQF 64LQFP 48QFN P Pin Name Driver Strength Default Status after POR Pull-up/ pulldown Setting after POR Slew Rate after POR 76 49 37 PTC4/ HD Hi-Z - FS LLWU_P 8 77 50 38 PTC5/ ND Hi-Z - FS LLWU_P 9 78 51 39 PTC6/ ND Hi-Z - FS LLWU_P 10 79 52 40 PTC7 ND Hi-Z - FS 80 53 PTC8 ND Hi-Z - FS 81 54 PTC9 ND Hi-Z - FS 82 55 PTC10 ND Hi-Z - FS 83 56 PTC11/ ND Hi-Z - FS LLWU_P 11 84 PTC12 ND Hi-Z - FS 85 PTC13 ND Hi-Z - FS 86 PTC14 ND Hi-Z - FS 87 PTC15 ND Hi-Z - FS 88 VSS - - - - 89 VDD - - - - 90 PTC16 ND Hi-Z - FS 91 PTC17 ND Hi-Z - FS 92 PTC18 ND Hi-Z - FS 93 57 41 PTD0/ ND Hi-Z - FS LLWU_P 12 94 58 42 PTD1 ND Hi-Z - FS 95 59 43 PTD2/ ND Hi-Z - FS LLWU_P 13 96 60 44 PTD3 ND Hi-Z - FS 97 61 45 PTD4/ HD Hi-Z - FS LLWU_P 14 98 62 46 PTD5 HD Hi-Z - FS 99 63 47 PTD6/ HD Hi-Z - FS LLWU_P 15 Table continues on the next page... Passive Pin Filter after POR Open Drain N N N N N N N N N N N N N N N N N N N N N N N N - - - - N N N N N N N N N N N N N N N N N N N N Pin Interrupt Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 38 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Pinouts 100LQF 64LQFP 48QFN P 100 64 48 Pin Name PTD7 Driver Strength Default Status after POR Pull-up/ pulldown Setting after POR Slew Rate after POR HD Hi-Z - FS Passive Pin Filter after POR Open Drain N N Pin Interrupt Y Properties Driver strength Default status after POR Pull-up/pull-down setting after POR Slew rate after POR Passive Pin Filter after POR Open drain Pin interrupt Abbreviation ND HD Hi-Z H L PU PD FS SS N Y N Y Y Descriptions Normal drive High drive High impendence High level Low level Pull-up Pull-down Fast slew rate Slow slew rate Disabled Enabled Disabled1 Enabled Yes 1. When UART or LPUART module is enabled and a pin is functional for UART or LPUART, this pin is (pseudo-) open drain configurable. 4.3 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction. 4.3.1 Core Modules Table 9. JTAG Signal Descriptions Chip signal name JTAG_TMS Module signal name JTAG_TMS/ SWD_DIO Description JTAG Test Mode Selection Table continues on the next page... KS22/KS20 Microcontroller, Rev. 3, 04/2016 I/O I 39 NXP Semiconductors Pinouts Table 9. JTAG Signal Descriptions (continued) Chip signal name Module signal Description I/O name JTAG_TCLK JTAG_TCLK/ JTAG Test Clock I SWD_CLK JTAG_TDI JTAG_TDI JTAG Test Data Input I JTAG_TDO JTAG_TDO/ JTAG Test Data Output O TRACE_SWO JTAG_TRST JTAG_TRST_b JTAG Reset I Table 10. SWD Signal Descriptions Chip signal name Module signal Description I/O name SWD_DIO JTAG_TMS/ Serial Wire Data I SWD_DIO SWD_CLK JTAG_TCLK/ Serial Wire Clock I SWD_CLK Table 11. TPIU Signal Descriptions Chip signal name Module signal Description I/O name TRACE_SWO JTAG_TDO/ Trace output data from the ARM CoreSight debug block over a O TRACE_SWO single pin 4.3.2 System Modules Table 12. EWM Signal Descriptions Chip signal name Module signal Description I/O name EWM_IN EWM_in EWM input for safety status of external safety circuits. The polarity I of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. EWM_OUT EWM_out EWM reset out signal O 40 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 4.3.3 Clock Modules Table 13. OSC Signal Descriptions Chip signal name EXTAL0 XTAL0 Module signal name EXTAL XTAL Description External clock/Oscillator input Oscillator output Chip signal name EXTAL32 XTAL32 Table 14. RTC OSC Signal Descriptions Module signal name EXTAL32 XTAL32 Description 32.768 kHz oscillator input 32.768 kHz oscillator output Pinouts I/O I O I/O I O 4.3.4 Analog Table 15. ADC 0 Signal Descriptions Chip signal name ADC0_DP[3:0] ADC0_DM[3:0] ADC0_SEn VREFH VREFL VDDA VSSA Module signal name DADP3DADP0 DADM3DADM0 ADn VREFSH VREFSL VDDA VSSA Description Differential Analog Channel Inputs Differential Analog Channel Inputs Single-Ended Analog Channel Inputs Voltage Reference Select High Voltage Reference Select Low Analog Power Supply Analog Ground Chip signal name CMP0_IN[5:0] CMP0_OUT Table 16. CMP 0 Signal Descriptions Module signal name IN[5:0] CMPO Description Analog voltage inputs Comparator output Chip signal name DAC0_OUT Table 17. DAC 0 Signal Descriptions Module signal name -- Description DAC output KS22/KS20 Microcontroller, Rev. 3, 04/2016 I/O I I I I I I I I/O I O I/O O 41 NXP Semiconductors Pinouts 4.3.5 Timer Modules Table 18. PDB 0 Signal Descriptions Chip signal name Module signal Description I/O name PDB0_EXTRG EXTRG External Trigger Input Source I If the PDB is enabled and external trigger input source is selected, a positive edge on the EXTRG signal resets and starts the counter. Table 19. LPTMR 0 Signal Descriptions Chip signal name Module signal Description I/O name LPTMR0_ALT[2:1] LPTMR0_ALTn Pulse Counter Input pin I Table 20. RTC Signal Descriptions Chip signal name Module signal Description I/O name VBAT -- Backup battery supply for RTC and VBAT register file I RTC_CLKOUT RTC_CLKOUT 1 Hz square-wave output or OSCERCLK O Table 21. TPM 0 Signal Descriptions Chip signal name Module signal Description I/O name TPM_CLKIN[1:0] TPM_EXTCLK External clock. TPM external clock can be selected to increment I the TPM counter on every rising edge synchronized to the counter clock. TPM0_CH[5:0] TPM_CHn TPM channel (n = 5 to 0). A TPM channel pin is configured as I/O output when configured in an output compare or PWM mode and the TPM counter is enabled, otherwise the TPM channel pin is an input. Table 22. TPM 1 Signal Descriptions Chip signal name Module signal Description I/O name TPM_CLKIN[1:0] TPM_EXTCLK External clock. TPM external clock can be selected to increment I the TPM counter on every rising edge synchronized to the counter clock. Table continues on the next page... 42 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Pinouts Table 22. TPM 1 Signal Descriptions (continued) Chip signal name Module signal Description I/O name TPM1_CH[1:0] TPM_CHn TPM channel (n = 5 to 0). A TPM channel pin is configured as I/O output when configured in an output compare or PWM mode and the TPM counter is enabled, otherwise the TPM channel pin is an input. Table 23. TPM 2 Signal Descriptions Chip signal name Module signal Description I/O name TPM_CLKIN[1:0] TPM_EXTCLK External clock. TPM external clock can be selected to increment I the TPM counter on every rising edge synchronized to the counter clock. TPM2_CH[1:0] TPM_CHn TPM channel (n = 5 to 0). A TPM channel pin is configured as I/O output when configured in an output compare or PWM mode and the TPM counter is enabled, otherwise the TPM channel pin is an input. 4.3.6 Communication Interfaces Table 24. USB FS OTG Signal Descriptions Chip signal name Module signal Description I/O name USB0_DM usb_dm USB D- analog data signal on the USB bus. I/O USB0_DP usb_dp USB D+ analog data signal on the USB bus. I/O USB_CLKIN -- Alternate USB clock input I USB_SOF_OUT -- USB start of frame signal. Can be used to make the USB start of O frame available for external synchronization. Chip signal name CAN0_RX CAN0_TX Table 25. CAN 0 Signal Descriptions Module signal name CAN Rx CAN Tx Description CAN Receive Pin CAN Transmit Pin I/O Input Output KS22/KS20 Microcontroller, Rev. 3, 04/2016 43 NXP Semiconductors Pinouts Chip signal name CAN1_RX CAN1_TX Table 26. CAN 1 (for KS22 only) Signal Descriptions Module signal name CAN Rx CAN Tx Description CAN Receive Pin CAN Transmit Pin Chip signal name SPI0_PCS0 SPI0_PCS[3:1] SPI0_PCS4 SPI0_PCS5 SPI0_SIN SPI0_SOUT SPI0_SCK Table 27. SPI 0 Signal Descriptions Module signal name PCS0/SS PCS[1:3] PCS4 PCS5/ PCSS SIN SOUT SCK Description Peripheral Chip Select 0 (O) Peripheral Chip Selects 13 Peripheral Chip Select 4 Peripheral Chip Select 5 /Peripheral Chip Select Strobe Serial Data In Serial Data Out Serial Clock (O) Chip signal name SPI1_PCS0 SPI1_PCS[3:1] SPI1_SIN SPI1_SOUT SPI1_SCK Table 28. SPI 1 Signal Descriptions Module signal name PCS0/SS PCS[1:3] SIN SOUT SCK Description Peripheral Chip Select 0 (O) Peripheral Chip Selects 13 Serial Data In Serial Data Out Serial Clock (O) I/O Input Output I/O I/O O O O I O I/O I/O I/O O I O I/O Table 29. LPI2C 0 Signal Descriptions Chip signal name LPI2C0_SCL LPI2C0_SDA LPI2C0_HREQ LPI2C0_SCLS LPI2C0_SDAS Module signal Description I/O name SCL LPI2C clock line. I/O SDA LPI2C data line. I/O HREQ Host request, can initiate an LPI2C master transfer if asserted and I the I2C bus is idle. SCLS Secondary I2C clock line. If LPI2C master/slave are configured to I/O use separate pins, this the LPI2C slave SCL pin. SDAS Secondary I2C data line. If LPI2C master/slave are configured to I/O use separate pins, this the LPI2C slave SDA pin. 44 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Pinouts Chip signal name LPI2C1_SCL LPI2C1_SDA LPI2C1_HREQ LPI2C1_SCLS LPI2C1_SDAS Table 30. LPI2C 1 Signal Descriptions Module signal Description I/O name SCL LPI2C clock line. I/O SDA LPI2C data line. I/O HREQ Host request, can initiate an LPI2C master transfer if asserted I and the I2C bus is idle. SCLS Secondary I2C clock line. If LPI2C master/slave are configured to I/O use separate pins, this the LPI2C slave SCL pin. SDAS Secondary I2C data line. If LPI2C master/slave are configured to I/O use separate pins, this the LPI2C slave SDA pin. Table 31. LPUART Signal Descriptions Chip signal name Module signal Description I/O name LPUART0_TX LPUART_TX Transmit data. This pin is normally an output, but is an input O/I (tristated) in single wire mode whenever the transmitter is disabled or transmit direction is configured for receive data. LPUART0_RX LPUART_RX Receive data I LPUART0_CTS LPUART_CTS Clear to send I LPUART0_CTS LPUART_RTS Request to send I Table 32. UART 0 Signal Descriptions Chip signal name Module signal Description I/O name UART0_CTS CTS Clear to send I UART0_RTS RTS Request to send O UART0_TX TXD Transmit data O UART0_RX RXD Receive data I Table 33. UART 1 Signal Descriptions Chip signal name Module signal Description I/O name UART1_CTS CTS Clear to send I UART1_RTS RTS Request to send O UART1_TX TXD Transmit data O UART1_RX RXD Receive data I KS22/KS20 Microcontroller, Rev. 3, 04/2016 45 NXP Semiconductors Pinouts Table 34. UART 2 Signal Descriptions Chip signal name Module signal Description I/O name UART2_CTS CTS Clear to send I UART2_RTS RTS Request to send O UART2_TX TXD Transmit data O UART2_RX RXD Receive data I Table 35. I2S0 Signal Descriptions Chip signal name Module signal Description I/O name I2S0_MCLK SAI_MCLK Audio Master Clock. The master clock is an input when externally I/O generated and an output when internally generated. I2S0_RX_BCLK SAI_RX_BCLK Receive Bit Clock. The bit clock is an input when externally I/O generated and an output when internally generated. I2S0_RX_FS SAI_RX_SYNC Receive Frame Sync. The frame sync is an input sampled I/O synchronously by the bit clock when externally generated and an output generated synchronously by the bit clock when internally generated. I2S0_RXD SAI_RX_DATA Receive Data. The receive data is sampled synchronously by the I bit clock. I2S0_TX_BCLK SAI_TX_BCLK Transmit Bit Clock. The bit clock is an input when externally I/O generated and an output when internally generated. I2S0_TX_FS SAI_TX_SYNC Transmit Frame Sync. The frame sync is an input sampled I/O synchronously by the bit clock when externally generated and an output generated synchronously by the bit clock when internally generated. I2S0_TXD SAI_TX_DATA Transmit Data. The transmit data is generated synchronously by O the bit clock and is tristated whenever not transmitting a word. Table 36. I2S1 Signal Descriptions Chip signal name Module signal Description I/O name I2S1_MCLK SAI_MCLK Audio Master Clock. The master clock is an input when externally I/O generated and an output when internally generated. I2S1_RX_BCLK SAI_RX_BCLK Receive Bit Clock. The bit clock is an input when externally I/O generated and an output when internally generated. I2S1_RX_FS SAI_RX_SYNC Receive Frame Sync. The frame sync is an input sampled I/O synchronously by the bit clock when externally generated and an output generated synchronously by the bit clock when internally generated. I2S1_RXD SAI_RX_DATA Receive Data. The receive data is sampled synchronously by the I bit clock. Table continues on the next page... 46 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Pinouts Table 36. I2S1 Signal Descriptions (continued) Chip signal name Module signal Description I/O name I2S1_TX_BCLK SAI_TX_BCLK Transmit Bit Clock. The bit clock is an input when externally I/O generated and an output when internally generated. I2S1_TX_FS SAI_TX_SYNC Transmit Frame Sync. The frame sync is an input sampled I/O synchronously by the bit clock when externally generated and an output generated synchronously by the bit clock when internally generated. I2S1_TXD SAI_TX_DATA Transmit Data. The transmit data is generated synchronously by O the bit clock and is tristated whenever not transmitting a word. Table 37. FlexIO Signal Descriptions Chip signal name Module signal Description I/O name FXIO0_Dn FXIO_Dn (n=0...7) Bidirectional FlexIO Shifter and Timer pin inputs/outputs I/O 4.3.7 Human-Machine Interfaces (HMI) Table 38. GPIO Signal Descriptions Chip signal name Module signal Description I/O name PTA[31:0]1 PORTA31PORTA0 General-purpose input/output I/O PTB[31:0]1 PORTB31PORTB0 General-purpose input/output I/O PTC[31:0]1 PORTC31PORTC0 General-purpose input/output I/O PTD[31:0]1 PORTD31PORTD0 General-purpose input/output I/O PTE[31:0]1 PORTE31PORTE0 General-purpose input/output I/O 1. The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO signals are available. 4.4 Pinouts The following figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous "signal multiplexing and pin assignments" section. KS22/KS20 Microcontroller, Rev. 3, 04/2016 47 NXP Semiconductors Pinouts PTC4/LLWU_P8 PTC5/LLWU_P9 PTC6/LLWU_P10 PTC11/LLWU_P11 PTD0/LLWU_P12 PTD2/LLWU_P13 PTD4/LLWU_P14 PTD6/LLWU_P15 PTC7 PTC8 PTC9 PTC10 PTC12 PTC13 PTC14 PTC15 VSS VDD PTC16 PTC17 PTC18 PTD1 PTD3 PTD5 PTD7 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PTE0/CLKOUT32K 1 PTE1/LLWU_P0 2 PTE2/LLWU_P1 3 PTE3 4 PTE4/LLWU_P2 5 PTE5 6 PTE6 7 VDD 8 VSS 9 USB0_DP 10 USB0_DM 11 USBVDD 12 NC 13 ADC0_DP1 14 ADC0_DM1 15 ADC0_DP2 16 ADC0_DM2 17 ADC0_DP0 18 ADC0_DM0 19 ADC0_DP3 20 ADC0_DM3 21 VDDA 22 VREFH 23 VREFL 24 VSSA 25 75 VDD 74 VSS 73 PTC3/LLWU_P7 72 PTC2 71 PTC1/LLWU_P6 70 PTC0 69 PTB23 68 PTB22 67 PTB21 66 PTB20 65 PTB19 64 PTB18 63 PTB17 62 PTB16 61 VDD 60 VSS 59 PTB11 58 PTB10 57 PTB9 56 PTB3 55 PTB2 54 PTB1 53 PTB0/LLWU_P5 52 RESET_b 51 PTA19 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 PTA18 VSS VDD PTA17 PTA16 PTA15 PTA14 PTA13/LLWU_P4 PTA12 VSS VDD PTA5 PTA4/LLWU_P3 PTA3 PTA2 PTA1 PTA0 PTE26/CLKOUT32K PTE25 PTE24 VBAT EXTAL32 XTAL32 DAC0_OUT/ADC0_SE23 CMP0_IN5 Figure 6. 100 LQFP Pinout Diagram 48 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 PTE0/CLKOUT32K 1 PTE1/LLWU_P0 2 VDD 3 VSS 4 USB0_DP 5 USB0_DM 6 USBVDD 7 ADC0_DP1 8 ADC0_DP0 9 ADC0_DM0 10 ADC0_DP3 11 ADC0_DM3 12 VDDA 13 VREFH 14 VREFL 15 VSSA 16 64 PTD7 63 PTD6/LLWU_P15 62 PTD5 61 PTD4/LLWU_P14 60 PTD3 59 PTD2/LLWU_P13 58 PTD1 57 PTD0/LLWU_P12 56 PTC11/LLWU_P11 55 PTC10 54 PTC9 53 PTC8 52 PTC7 51 PTC6/LLWU_P10 50 PTC5/LLWU_P9 49 PTC4/LLWU_P8 Pinouts 48 VDD 47 VSS 46 PTC3/LLWU_P7 45 PTC2 44 PTC1/LLWU_P6 43 PTC0 42 PTB19 41 PTB18 40 PTB17 39 PTB16 38 PTB3 37 PTB2 36 PTB1 35 PTB0/LLWU_P5 34 RESET_b 33 PTA19 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PTA18 VSS VDD PTA13/LLWU_P4 PTA12 PTA5 PTA4/LLWU_P3 PTA3 PTA2 PTA1 PTA0 VBAT EXTAL32 XTAL32 DAC0_OUT/ADC0_SE23 CMP0_IN5 Figure 7. 64 LQFP Pinout Diagram KS22/KS20 Microcontroller, Rev. 3, 04/2016 49 NXP Semiconductors Pinouts PTC4/LLWU_P8 PTC5/LLWU_P9 PTC6/LLWU_P10 PTD0/LLWU_P12 PTD2/LLWU_P13 PTD4/LLWU_P14 PTD6/LLWU_P15 PTC7 PTD1 PTD3 PTD5 PTD7 37 38 39 40 41 42 43 44 45 46 47 48 PTE0/CLKOUT32K 1 PTE1/LLWU_P0 2 PTE2/LLWU_P1 3 PTE3 4 PTE4/LLWU_P2 5 PTE5 6 VDD 7 VSS 8 USB0_DP 9 USB0_DM 10 USBVDD 11 VDDA VREFH 12 36 PTC3/LLWU_P7 35 PTC2 34 PTC1/LLWU_P6 33 PTB19 32 PTB18 31 PTB16 30 PTB3 29 PTB2 28 PTB1 27 PTB0/LLWU_P5 26 RESET_b 25 PTA19 24 23 22 21 20 19 18 17 16 15 14 13 PTA18 VSS VDD PTA4/LLWU_P3 PTA3 PTA2 PTA1 PTA0 VBAT EXTAL32 XTAL32 VREFL VSSA Figure 8. 48 QFN Pinout Diagram 4.5 Package dimensions The following figures show the dimensions of the package options for the devices supported by this document. 50 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Pinouts Figure 9. 100-pin LQFP package dimensions 1 KS22/KS20 Microcontroller, Rev. 3, 04/2016 51 NXP Semiconductors Pinouts Figure 10. 100-pin LQFP package dimensions 2 52 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Pinouts Figure 11. 64-pin LQFP package dimensions 1 KS22/KS20 Microcontroller, Rev. 3, 04/2016 53 NXP Semiconductors Pinouts Figure 12. 64-pin LQFP package dimensions 2 54 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Pinouts Figure 13. 48-pin QFN package dimension 1 KS22/KS20 Microcontroller, Rev. 3, 04/2016 55 NXP Semiconductors Electrical characteristics 45° (0.05) 0.65 0.50 0.95 1.13 DETAIL F 0.25 // 0.1 C 48X 0.08 C 4 0.05 0.00 (0.2) (0.5) C SEATING PLANE DETAIL G VIEW ROTATED 90W NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 3. THIS IS A NON-JEDEC REGISTERED PACKAGE. 4. COPLANARITY APPLIES TO LEADS AND DIE ATTACH FLAG. 5. MIN. METAL GAP SHOULD BE 0.2 MM. Figure 14. 48-pin QFN package dimension 2 5 Electrical characteristics 5.1 Terminology and guidelines 56 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics 5.1.1 Definitions Key terms are defined in the following table: Term Rating Definition A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: · Operating ratings apply during operation of the chip. · Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that: · Lies within the range of values specified by the operating behavior · Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed. KS22/KS20 Microcontroller, Rev. 3, 04/2016 57 NXP Semiconductors Electrical characteristics 5.1.2 Examples Operating rating: EXAMPLE Operating requirement: EXAMPLE Operating behavior that includes a typical value: EXAMPLE 5.1.3 Typical-value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol TA VDD Description Ambient temperature Supply voltage Value 25 3.3 Unit °C V 58 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics 5.1.4 Relationship between ratings and operating requirements Fatal range Operating rating (min.) Operating requirement (min.) Operating requirement (max.) Operating rating (max.) Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure Operating (power on) Fatal range Handling rating (min.) Expected permanent failure Handling range No permanent failure Handling (power off) Handling rating (max.) Fatal range Expected permanent failure 5.1.5 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: · Never exceed any of the chip's ratings. · During normal operation, don't exceed any of the chip's operating requirements. · If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 5.2 Ratings 5.2.1 Thermal handling ratings Symbol TSTG TSDR Description Storage temperature Solder temperature, lead-free Min. 55 -- Max. 150 260 Unit Notes °C 1 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. KS22/KS20 Microcontroller, Rev. 3, 04/2016 59 NXP Semiconductors Electrical characteristics 5.2.2 Moisture handling ratings Symbol Description MSL Moisture sensitivity level Min. -- Max. 3 Unit Notes -- 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 5.2.3 ESD handling ratings Symbol VHBM VCDM ILAT Description Electrostatic discharge voltage, human body model Electrostatic discharge voltage, charged-device model Latch-up current at ambient temperature of 105°C Min. -2000 -500 -100 Max. +2000 +500 +100 Unit V V mA Notes 1 2 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 5.2.4 Voltage and current operating ratings Table 39. Voltage and current operating ratings Symbol VDD IDD VIO ID VDDA VUSB_DP VUSB_DM VBAT Description Digital supply voltage Digital supply current IO pin input voltage Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage USB_DP input voltage USB_DM input voltage RTC battery supply voltage Min. 0.3 -- 0.3 25 VDD 0.3 0.3 0.3 0.3 Max. 3.8 120 VDD + 0.3 25 VDD + 0.3 3.63 3.63 3.8 Unit V mA V mA V V V V 5.3 General 60 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics 5.3.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Low VIH Input Signal Midpoint1 Fall Time VIL High Rise Time 80% 50% 20% The midpoint is VIL + (VIH - VIL) / 2 Figure 15. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assume that the output pins have the following characteristics. · CL=30 pF loads · Slew rate disabled · Normal drive strength 5.3.2 Nonswitching electrical specifications 5.3.2.1 Voltage and current operating requirements Table 40. Voltage and current operating requirements Symbol Description VDD Supply voltage VDDA Analog supply voltage VDD VDDA VDD-to-VDDA differential voltage VSS VSSA VSS-to-VSSA differential voltage VBAT RTC battery supply voltage USBVDD USB Transceiver supply voltage VIH Input high voltage · 2.7 V VDD 3.6 V · 1.7 V VDD 2.7 V Min. Max. Unit 1.71 3.6 V 1.71 3.6 V 0.1 0.1 V 0.1 0.1 V 1.71 3.6 V 3.0 3.6 V 0.7 × VDD -- V 0.75 × VDD -- V Table continues on the next page... Notes 1 KS22/KS20 Microcontroller, Rev. 3, 04/2016 61 NXP Semiconductors Electrical characteristics Table 40. Voltage and current operating requirements (continued) Symbol VIL VHYS IICIO Description Input low voltage · 2.7 V VDD 3.6 V · 1.7 V VDD 2.7 V Input hysteresis Analog and I/O pin DC injection current -- single pin · VIN < VSS-0.3V (Negative current injection) Min. -- -- 0.06 × VDD -3 Max. 0.35 × VDD 0.3 × VDD -- -- Unit V V V mA IICcont Contiguous pin DC injection current --regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins · Negative current injection -25 -- mA VODPU Open drain pullup voltage level VDD VDD V VRAM VDD voltage required to retain RAM 1.2 -- V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT -- V Notes 2 3 1. USB nominal operating voltage is 3.3 V. 2. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or greater than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VIO_MIN-VIN)/|IICIO|. 3. Open drain outputs must be pulled to VDD. 5.3.2.2 HVD, LVD and POR operating requirements Table 41. VDD supply HVD, LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VHVDH VHVDL VPOR VLVDH High Voltage Detect (High Trip Point) High Voltage Detect (Low Trip Point) Falling VDD POR detect voltage Falling low-voltage detect threshold -- high range (LVDV=01) -- 3.72 -- V -- 3.46 -- V 0.8 1.1 1.5 V 2.48 2.56 2.64 V Low-voltage warning thresholds -- high range VLVW1H VLVW2H VLVW3H VLVW4H · Level 1 falling (LVWV=00) · Level 2 falling (LVWV=01) · Level 3 falling (LVWV=10) · Level 4 falling (LVWV=11) 2.62 2.70 2.78 V 2.72 2.80 2.88 V 2.82 2.90 2.98 V 2.92 3.00 3.08 V VHYSH Low-voltage inhibit reset/recover hysteresis -- -- 80 -- mV high range VLVDL Falling low-voltage detect threshold -- low range (LVDV=00) 1.54 1.60 1.66 V Low-voltage warning thresholds -- low range Table continues on the next page... Notes 1 1 62 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics Table 41. VDD supply HVD, LVD and POR operating requirements (continued) Symbol VLVW1L VLVW2L VLVW3L VLVW4L Description · Level 1 falling (LVWV=00) · Level 2 falling (LVWV=01) · Level 3 falling (LVWV=10) · Level 4 falling (LVWV=11) Min. 1.74 1.84 1.94 2.04 Typ. 1.80 1.90 2.00 2.10 Max. 1.86 1.96 2.06 2.16 Unit Notes V V V V VHYSL Low-voltage inhibit reset/recover hysteresis -- -- 60 -- mV low range VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period -- factory 900 1000 1100 s trimmed 1. Rising threshold is the sum of falling threshold and hysteresis voltage Table 42. VBAT power operating requirements Symbol Description VPOR_VBAT Falling VBAT supply POR detect voltage Min. 0.8 Typ. 1.1 Max. 1.5 Unit Notes V 5.3.2.3 Voltage and current operating behaviors Table 43. Voltage and current operating behaviors Symbol Description Min. Typ. VOH Output high voltage -- Normal drive pad except RESET_B 2.7 V VDD 3.6 V, IOH = -5 mA VDD 0.5 -- 1.71 V VDD 2.7 V, IOH = -2.5 mA VDD 0.5 -- VOH Output high voltage -- High drive pad except RESET_B 2.7 V VDD 3.6 V, IOH = -20 mA VDD 0.5 -- 1.71 V VDD 2.7 V, IOH = -10 mA VDD 0.5 -- IOHT Output high current total for all ports -- -- VOL Output low voltage -- Normal drive pad except RESET_B 2.7 V VDD 3.6 V, IOL = 5 mA -- -- 1.71 V VDD 2.7 V, IOL = 2.5 mA -- -- VOL Output low voltage -- High drive pad except RESET_B 2.7 V VDD 3.6 V, IOL = 20 mA 1.71 V VDD 2.7 V, IOL = 10 mA VOL Output low voltage -- RESET_B 2.7 V VDD 3.6 V, IOL = 3 mA -- -- -- -- -- -- Table continues on the next page... Max. -- -- -- -- 100 0.5 0.5 0.5 0.5 0.5 Unit V V V V mA V V V V V Notes 1 1 1 1 KS22/KS20 Microcontroller, Rev. 3, 04/2016 63 NXP Semiconductors Electrical characteristics Table 43. Voltage and current operating behaviors (continued) Symbol Description 1.71 V VDD 2.7 V, IOL = 1.5 mA IOLT Output low current total for all ports IIN Input leakage current (per pin) for full temperature range All pins other than high drive port pins High drive port pins IIN Input leakage current (total all pins) for full temperature range RPU Internal pullup resistors RPD Internal pulldown resistors Min. Typ. Max. Unit -- -- 0.5 V -- -- 100 mA -- 0.002 0.5 A -- 0.004 0.5 A -- -- 1.0 A 20 -- 50 k 20 -- 50 k Notes 1, 2 2 3 4 1. PTB0, PTB1, PTD4, PTD5, PTD6, PTD7, PTC3, and PTC4 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. Measured at VDD=3.6V 3. Measured at VDD supply voltage = VDD min and Vinput = VSS 4. Measured at VDD supply voltage = VDD min and Vinput = VDD 5.3.2.4 Power mode transition operating behaviors All specifications except tPOR and VLLSx RUN recovery times in the following table assume this clock configuration: · CPU and system clocks = 80 MHz · Bus clock = 40 MHz · Flash clock = 20 MHz · MCG mode: FEI Table 44. Power mode transition operating behaviors Symbol Description Min. Typ. Max. Unit tPOR After a POR event, amount of time from the -- point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. -- 300 s Notes 1 · VLLS0 RUN -- -- 140 s · VLLS1 RUN -- -- 140 s · VLLS2 RUN -- -- 80 s · VLLS3 RUN -- -- 80 s Table continues on the next page... 64 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics Table 44. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit · LLS2 RUN -- -- 6 s · LLS3 RUN -- -- 6 s · VLPS RUN -- -- 5.7 s · STOP RUN -- -- 5.7 s Notes 1. Normal boot (FTFA_FOPT[LPBOOT]=1) 5.3.2.5 Power consumption operating behaviors The maximum values stated in the following table represent the characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). NOTE The while(1) test is executed with flash cache enabled. Table 45. Power consumption operating behaviors Symbol Description IDDA Analog supply current IDD_HSRUN High Speed Run mode current - all peripheral clocks disabled, CoreMark benchmark code executing from flash @ 1.8V @ 3.0V IDD_HSRUN High Speed Run mode current - all peripheral clocks disabled, code executing from flash @ 1.8V @ 3.0V IDD_HSRUN High Speed Run mode current -- all peripheral clocks enabled, code executing from flash @ 1.8V @ 3.0V IDD_RUN Run mode current in Compute operation -- CoreMark benchmark code executing from flash @ 1.8V @ 3.0V Min. -- -- -- -- -- -- -- -- -- Typ. Max. Unit -- See note mA 24.17 26.215 mA 24.20 26.292 mA 20.97 23.015 mA 20.97 23.062 mA 27.77 30.028 mA 27.79 30.083 mA 15.58 16.790 mA 16.19 17.457 mA Table continues on the next page... Notes 1 2, 3, 4 2 5 3, 4, 6 KS22/KS20 Microcontroller, Rev. 3, 04/2016 65 NXP Semiconductors Electrical characteristics Table 45. Power consumption operating behaviors (continued) Symbol Description IDD_RUN Run mode current in Compute operation -- code executing from flash @ 1.8V @ 3.0V IDD_RUN Run mode current -- all peripheral clocks disabled, code executing from flash @ 1.8V @ 3.0V · @ 25°C Min. Typ. Max. Unit -- 13.38 14.590 mA -- 13.42 14.687 mA -- 13.81 15.087 mA -- 13.87 15.158 mA · @ -40°C -- 13.72 15.050 mA · @ 70°C -- 14.03 15.267 mA · @ 85°C -- 14.12 15.347 mA · @ 105°C -- 14.31 15.529 mA IDD_RUN Run mode current -- all peripheral clocks enabled, code executing from flash @ 1.8V @ 3.0V · @ 25°C -- 18.00 20.042 mA -- 18.08 20.145 mA · @ -40°C -- 17.88 20.022 mA · @ 70°C -- 18.27 20.229 mA · @ 85°C -- 18.35 20.321 mA · @ 105°C -- 18.55 20.544 mA IDD_RUN Run mode current -- Compute operation, code executing from flash @ 1.8V -- @ 3.0V · @ 25°C -- 12.68 13.763 mA 12.62 13.714 mA · @ -40°C -- 12.53 13.652 mA · @ 70°C -- 12.76 13.827 mA · @ 85°C -- 12.84 13.895 mA · @ 105°C -- 13.02 14.078 mA IDD_WAIT Wait mode high frequency current at 3.0 V -- -- all peripheral clocks disabled IDD_WAIT Wait mode reduced frequency current at 3.0 V -- -- all peripheral clocks disabled 6.56 7.022 mA 3.80 4.118 mA Table continues on the next page... Notes 6 7 8 9 7 10 66 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics Table 45. Power consumption operating behaviors (continued) Symbol Description Min. Typ. IDD_VLPR Very-low-power run mode current in Compute operation -- CoreMark benchmark code executing from flash @ 1.8V -- @ 3.0V -- IDD_VLPR Very-low-power run mode current in Compute operation, code executing from flash @ 1.8V -- @ 3.0V -- IDD_VLPR Very-low-power run mode current at 3.0 V -- all -- peripheral clocks disabled IDD_VLPR Very-low-power run mode current at 3.0 V -- all -- peripheral clocks enabled IDD_VLPW Very-low-power wait mode current at 3.0 V -- -- all peripheral clocks disabled IDD_STOP Stop mode current at 3.0 V @ 25°C -- @ -40°C -- @ 70°C -- @ 85°C -- @ 105°C -- IDD_VLPS Very-low-power stop mode current at 3.0 V @ 25°C -- @ -40°C -- @ 70°C -- @ 85°C -- @ 105°C -- IDD_LLS3 Low leakage stop mode 3 current at 3.0 V @ 25°C -- @ -40°C -- @ 70°C -- @ 85°C -- @ 105°C -- IDD_LLS2 Low leakage stop mode 2 current at 3.0 V @ 25°C -- @ -40°C -- @ 70°C -- @ 85°C -- @ 105°C -- IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V @ 25°C -- 967.09 973.06 449.10 462.61 520.34 845.46 240.81 269.63 253.73 309.98 347.88 450.05 3.48 2.47 15.20 28.62 65.48 2.78 2.14 7.72 13.30 29.50 2.56 2.10 6.14 10.34 22.68 2.01 Table continues on the next page... Max. 1031.341 1040.294 513.351 529.844 592.022 1005.706 269.275 292.223 280.001 346.335 401.693 565.013 6.005 3.740 30.384 52.396 115.129 3.778 2.881 12.481 21.607 47.202 3.293 2.802 8.758 15.242 33.393 2.769 Unit A A A A A A A A A A A A µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA Notes 3, 4, 11 11 12 13 14 KS22/KS20 Microcontroller, Rev. 3, 04/2016 67 NXP Semiconductors Electrical characteristics Table 45. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit @ -40°C -- 1.55 2.485 µA @ 70°C -- 5.81 9.658 µA @ 85°C -- 10.06 16.695 µA @ 105°C -- 22.30 35.783 µA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V @ 25°C -- 1.76 2.298 µA @ -40°C -- 1.51 1.963 µA @ 70°C -- 3.73 5.221 µA @ 85°C -- 6.12 8.624 µA @ 105°C -- 13.22 18.408 µA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V @ 25°C -- 0.64 0.835 µA @ -40°C -- 0.55 0.795 µA @ 70°C -- 1.88 2.427 µA @ 85°C -- 3.52 4.640 µA @ 105°C -- 8.62 11.273 µA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled @ 25°C -- 0.36 0.525 µA @ -40°C -- 0.29 0.513 µA @ 70°C -- 1.58 2.108 µA @ 85°C -- 3.19 4.289 µA @ 105°C -- 8.20 10.838 µA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled @ 25°C -- 0.093 0.249 µA @ -40°C -- 0.016 0.145 µA @ 70°C -- 1.30 1.821 µA @ 85°C -- 2.91 3.994 µA @ 105°C -- 7.92 10.501 µA IDD_VBAT Average current with RTC and 32kHz disabled at 3.0 V @ 25°C -- 0.21 0.245 µA @ -40°C -- 0.14 0.163 µA @ 70°C -- 1.15 1.498 µA @ 85°C -- 2.44 3.596 µA @ 105°C -- 6.49 9.557 µA IDD_VBAT Average current when CPU is not accessing RTC registers at 3.0 V · @ 25°C -- 0.76 0.899 µA Notes VDD is off. VDD is off. Table continues on the next page... 68 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics Table 45. Power consumption operating behaviors (continued) Symbol Description · @ -40°C Min. Typ. Max. Unit -- 0.63 0.745 µA · @ 70°C -- 1.80 2.346 µA · @ 85°C -- 3.11 4.575 µA · @ 105°C -- 7.24 10.653 µA Notes 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 120MHz core and system clock, 60MHz bus clock, and 24MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 3. Cache on and prefetch on, low compiler optimization. 4. Coremark benchmark compiled using IAR 7.2 with optimization level high. 5. 120MHz core and system clock, 60MHz bus clock, and 24MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled. 6. 80 MHz core and system clock, 40 MHz bus clock, and 26.67 MHz flash clock. MCG configured for PEE mode. Compute operation. 7. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. All peripheral clocks disabled. 8. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled. 9. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. Compute operation. 10. 25MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. 11. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. Compute operation. Code executing from flash. 12. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 13. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 14. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 5.3.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: · MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at frequencies between 50 MHz and 100MHz. · No GPIOs toggled · Code execution from flash with cache enabled · For the ALLOFF curve, all peripheral clocks are disabled except FTFA KS22/KS20 Microcontroller, Rev. 3, 04/2016 69 NXP Semiconductors Electrical characteristics Figure 16. Run mode supply current vs. core frequency 70 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics Figure 17. VLPR mode supply current vs. core frequency 5.3.2.6 EMC performance Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components, and MCU software operation play a significant role in the EMC performance. The system designer can consult the following Freescale applications notes, available on freescale.com for advice and guidance specifically targeted at optimizing EMC performance. · AN2321: Designing for Board Level Electromagnetic Compatibility · AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers · AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers KS22/KS20 Microcontroller, Rev. 3, 04/2016 71 NXP Semiconductors Electrical characteristics · AN2764: Improving the Transient Immunity Performance of MicrocontrollerBased Applications · AN1259: System Design and Layout Techniques for Noise Reduction in MCUBased Systems 5.3.2.6.1 EMC radiated emissions operating behaviors Table 46. EMC radiated emissions operating behaviors for 64 LQFP package Parame Conditions ter Clocks VEME Device configuration, test FSYS = 120 MHz conditions and EM testing per standard IEC FBUS = 60 MHz 61967-2. External crystal = 8 MHz Supply voltages: · VDD = 3.3 V Frequency range 150 kHz50 MHz 50 MHz150 MHz 150 MHz500 MHz 500 MHz1000 MHz IEC level Level (Typ.) 14 23 23 9 L Unit dBuV Notes 1, 2 3 Temp = 25°C 1. Measurements were made per IEC 61967-2 while the device was running typical application code. 2. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 3. IEC Level Maximums: M 18dBmV, L 24dBmV, K 30dBmV, I 36dBmV, H 42dBmV . 5.3.2.6.2 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for "EMC design." 5.3.2.7 Capacitance attributes Table 47. Capacitance attributes Symbol CIN_A CIN_D Description Input capacitance: analog pins Input capacitance: digital pins Min. Max. Unit -- 7 pF -- 7 pF 5.3.3 Switching specifications 72 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics 5.3.3.1 Device clock specifications Table 48. Device clock specifications Symbol Description High Speed run mode fSYS System and core clock fBUS Bus clock Normal run mode fSYS fSYS_USB fBUS fFLASH fLPTMR System and core clock System and core clock when Full Speed USB in operation Bus clock Flash clock LPTMR clock VLPR and VLPS modes1 fSYS fBUS fFLASH fERCLK fLPTMR_pin fLPTMR_ERCLK fI2S_MCLK fI2S_BCLK fFlexIO fLPI2C fFlexCAN System and core clock Bus clock Flash clock External reference clock LPTMR clock LPTMR external reference clock I2S master clock I2S bit clock FlexIO clock LPI2C clock FlexCAN clock Min. -- -- -- 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 120 60 80 -- 50 26.67 25 4 4 1 16 25 16 12.5 4 16 16 4 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN or from VLPR. 5.3.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, and timers. Table 49. General switching specifications Symbol Description GPIO pin interrupt pulse width (digital glitch filter disabled) -- Synchronous path External RESET and NMI pin interrupt pulse width -- Asynchronous path Min. 1.5 100 Table continues on the next page... Max. -- -- Unit Bus clock cycles ns Notes 1, 2 3 KS22/KS20 Microcontroller, Rev. 3, 04/2016 73 NXP Semiconductors Electrical characteristics Table 49. General switching specifications (continued) Symbol Description Min. Max. Unit GPIO pin interrupt pulse width (digital glitch filter 50 -- ns disabled, passive filter disabled) -- Asynchronous path Port rise and fall time · Slew disabled -- · 1.71 VDD 2.7V · 2.7 VDD 3.6V · Slew enabled -- 10 ns 5 ns -- · 1.71 VDD 2.7V · 2.7 VDD 3.6V -- 30 ns 16 ns Notes 4 5 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater of synchronous and asynchronous timing must be met. 3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be recognized. 4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized. 5. 25 pF load 5.3.4 Thermal specification 5.3.4.1 Thermal operating requirements Table 50. Thermal operating requirements Symbol TJ TA Description Die junction temperature Ambient temperature Min. 40 40 Max. 125 105 Unit Notes °C °C 1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to determine TJ is: TJ = TA + RJA × chip power dissipation. 5.3.4.2 Thermal attributes Table 51. Thermal attributes Board type Symbol Description Single-layer (1s) RJA Thermal resistance, junction to ambient (natural convection) 100 LQFP 58 64 LQFP 48 QFN 61 81 Table continues on the next page... Unit °C/W Notes 1, 2, 3 74 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics Board type Four-layer (2s2p) Single-layer (1s) Four-layer (2s2p) -- -- -- -- Table 51. Thermal attributes (continued) Symbol Description RJA RJMA RJMA RJB RJC JT JB Thermal resistance, junction to ambient (natural convection) Thermal resistance, junction to ambient (200 ft./min. air speed) Thermal resistance, junction to ambient (200 ft./min. air speed) Thermal resistance, junction to board Thermal resistance, junction to case Thermal characterization parameter, junction to package top outside center (natural convection) Thermal characterization parameter, junction to package bottom (natural convection) 100 LQFP 46 64 LQFP 48 QFN 43 28 48 49 66 40 36 23 31 25 11 16 13 1.3 2 2 2 - - - Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W Notes 1, 2, 3,4 1, 4, 5 1, 4, 5 6 7 8 9 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. 4. Per JEDEC JESD51-6 with the board horizontal. 5. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. 6. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 7. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 8. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 9. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB. 5.4 Peripheral operating requirements and behaviors 5.4.1 Debug modules KS22/KS20 Microcontroller, Rev. 3, 04/2016 75 NXP Semiconductors Electrical characteristics 5.4.1.1 SWD electricals Table 52. SWD full voltage range electricals Symbol S1 Description Operating voltage SWD_CLK frequency of operation · Serial wire debug Min. 1.71 0 S2 SWD_CLK cycle period S3 SWD_CLK clock pulse width · Serial wire debug 1/S1 15 S4 SWD_CLK rise and fall times -- S9 SWD_DIO input data setup time to SWD_CLK rise 8 S10 SWD_DIO input data hold time after SWD_CLK rise 1.4 S11 SWD_CLK high to SWD_DIO data valid -- S12 SWD_CLK high to SWD_DIO high-Z 5 Max. 3.6 33 -- -- 3 -- -- 25 -- Unit V MHz ns ns ns ns ns ns ns SWD_CLK (input) S2 S3 S3 S4 S4 Figure 18. Serial wire clock input timing 76 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics SWD_CLK SWD_DIO S11 SWD_DIO S12 SWD_DIO S11 SWD_DIO S9 S10 Input data valid Output data valid Output data valid Figure 19. Serial wire data timing 5.4.1.2 JTAG electricals Table 53. JTAG limited voltage range electricals Symbol J1 Description Operating voltage TCLK frequency of operation · Boundary Scan · JTAG and CJTAG Min. 2.7 0 0 Max. 3.6 10 20 J2 TCLK cycle period J3 TCLK clock pulse width · Boundary Scan · JTAG and CJTAG 1/J1 -- 50 -- 25 -- J4 TCLK rise and fall times J5 Boundary scan input data setup time to TCLK rise J6 Boundary scan input data hold time after TCLK rise J7 TCLK low to boundary scan output data valid J8 TCLK low to boundary scan output high-Z J9 TMS, TDI input data setup time to TCLK rise J10 TMS, TDI input data hold time after TCLK rise -- 3 20 -- 1 -- -- 25 -- 25 8 -- 1 -- Table continues on the next page... Unit V MHz ns ns ns ns ns ns ns ns ns ns KS22/KS20 Microcontroller, Rev. 3, 04/2016 77 NXP Semiconductors Electrical characteristics Table 53. JTAG limited voltage range electricals (continued) Symbol J11 J12 J13 J14 Description TCLK low to TDO data valid TCLK low to TDO high-Z TRST assert time TRST setup time (negation) to TCLK high Min. Max. Unit -- 19 ns -- 19 ns 100 -- ns 8 -- ns Symbol J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 Table 54. JTAG full voltage range electricals Description Operating voltage TCLK frequency of operation · Boundary Scan · JTAG and CJTAG Min. 1.71 0 0 TCLK cycle period 1/J1 TCLK clock pulse width · Boundary Scan 50 · JTAG and CJTAG 33 TCLK rise and fall times -- Boundary scan input data setup time to TCLK rise 20 Boundary scan input data hold time after TCLK rise 1.4 TCLK low to boundary scan output data valid -- TCLK low to boundary scan output high-Z -- TMS, TDI input data setup time to TCLK rise 8 TMS, TDI input data hold time after TCLK rise 1.4 TCLK low to TDO data valid -- TCLK low to TDO high-Z -- TRST assert time 100 TRST setup time (negation) to TCLK high 8 Max. 3.6 10 15 -- -- -- 3 -- -- 27 27 -- -- 26.2 26.2 -- -- Unit V MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns TCLK (input) J2 J3 J3 J4 J4 Figure 20. Test clock input timing 78 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics TCLK Data inputs Data outputs Data outputs Data outputs J5 J6 Input data valid J7 Output data valid J8 J7 Output data valid Figure 21. Boundary scan (JTAG) timing TCLK TDI/TMS TDO TDO TDO J9 J10 Input data valid J11 Output data valid J12 J11 Output data valid Figure 22. Test Access Port timing KS22/KS20 Microcontroller, Rev. 3, 04/2016 79 NXP Semiconductors Electrical characteristics TCLK TRST J14 J13 Figure 23. TRST timing 5.4.2 System modules There are no specifications necessary for the device's system modules. 5.4.3 Clock modules 5.4.3.1 MCG specifications Table 55. MCG specifications Symbol Description Min. Typ. fints_ft Internal reference frequency (slow clock) -- factory trimmed at nominal VDD and 25 °C -- 32.768 fints_t Total deviation of internal reference frequency (slow clock) over voltage and temperature -- +0.5/-0.7 fints_t Internal reference frequency (slow clock) -- user trimmed 31.25 -- fdco_res_t Resolution of trimmed average DCO output -- ± 0.3 frequency at fixed voltage and temperature -- using SCTRIM and SCFTRIM fdco_t Total deviation of trimmed average DCO output -- +0.5/-0.7 frequency over voltage and temperature fdco_t Total deviation of trimmed average DCO output -- frequency over fixed voltage and temperature range of 070°C ± 0.3 fintf_ft Internal reference frequency (fast clock) -- factory trimmed at nominal VDD and 25°C -- 4 fintf_ft Frequency deviation of internal reference clock -- (fast clock) over temperature and voltage -- factory trimmed at nominal VDD and 25 °C +1/-2 fintf_t Internal reference frequency (fast clock) -- user 3 -- trimmed at nominal VDD and 25 °C floc_low Loss of external clock minimum frequency -- (3/5) x -- RANGE = 00 fints_t Table continues on the next page... Max. -- ± 2 39.0625 ± 0.6 ± 2 ± 1.5 -- ± 5 5 -- Unit kHz % kHz %fdco %fdco %fdco MHz %fintf_ft MHz kHz Notes 1 1, 2 1 80 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics Table 55. MCG specifications (continued) Symbol Description Min. floc_high Loss of external clock minimum frequency -- RANGE = 01, 10, or 11 (16/5) x fints_t FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS=00) 640 × ffll_ref Mid range (DRS=01) 31.25 20 40 1280 × ffll_ref Mid-high range (DRS=10) 60 1920 × ffll_ref High range (DRS=11) 80 fdco_t_DMX3 DCO output 2 frequency 2560 × ffll_ref Low range (DRS=00) -- 732 × ffll_ref Mid range (DRS=01) -- 1464 × ffll_ref Mid-high range (DRS=10) -- 2197 × ffll_ref High range (DRS=11) -- 2929 × ffll_ref Jcyc_fll FLL period jitter -- · fVCO = 48 MHz · fVCO = 98 MHz -- tfll_acquire fvco Ipll Ipll fpll_ref Jcyc_pll FLL target frequency acquisition time -- PLL VCO operating frequency 48.0 PLL operating current · PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = -- 2 MHz, VDIV multiplier = 48) PLL operating current · PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = -- 2 MHz, VDIV multiplier = 24) PLL reference frequency range 2.0 PLL period jitter (RMS) -- · fvco = 48 MHz -- · fvco = 100 MHz Typ. -- -- 20.97 41.94 62.91 83.89 23.99 47.97 71.99 95.98 -- 180 150 -- -- 1060 600 -- 120 75 Max. -- 39.0625 25 50 75 100 -- -- -- -- -- -- 1 120 -- -- 4.0 -- -- Jacc_pll PLL accumulated jitter over 1µs (RMS) -- 1350 -- -- 600 -- Table continues on the next page... Unit kHz kHz MHz MHz MHz MHz MHz MHz MHz MHz ps ms MHz µA µA MHz ps ps ps ps Notes 3, 4 5, 6 7 8 8 9 9 KS22/KS20 Microcontroller, Rev. 3, 04/2016 81 NXP Semiconductors Electrical characteristics Table 55. MCG specifications (continued) Symbol Description · fvco = 48 MHz · fvco = 100 MHz Min. Typ. Max. Unit Dlock Dunl tpll_lock Lock entry frequency tolerance Lock exit frequency tolerance Lock detector detection time ± 1.49 ± 4.47 -- -- ± 2.98 % -- ± 5.97 % -- 150 × 10-6 s + 1075(1/ fpll_ref) Notes 10 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. 2.0 V <= VDD <= 3.6 V. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (fdco_t) over voltage and temperature should be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 5.4.3.2 IRC48M specifications Table 56. IRC48M specifications Symbol Description VDD Supply voltage IDD48M Supply current firc48m Internal reference frequency firc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over 0°C to 70°C Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) firc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over full temperature Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) firc48m_ol_lv Open loop total deviation of IRC48M frequency at low voltage (VDD=1.71V-1.89V) over full temperature Regulator disable (USB_CLK_RECOVER_IRC_EN[REG_EN]=0) Min. 1.71 -- -- -- -- -- -- Typ. -- 400 48 ± 0.2 ± 0.4 ± 0.4 Table continues on the next page... Max. 3.6 500 -- Unit V A MHz Notes ± 0.5 %firc48m 1 ± 1.0 %firc48m 1 1 ± 1.0 %firc48m 82 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics Table 56. IRC48M specifications (continued) Symbol firc48m_cl Jcyc_irc48m tirc48mst Description Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) Closed loop total deviation of IRC48M frequency over voltage and temperature Period Jitter (RMS) Startup time Min. -- -- -- -- Typ. ± 0.5 -- 35 2 Max. ± 1.5 ± 0.1 150 3 Unit Notes %fhost 2 ps s 3 1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard deviation (mean ± 3 sigma). 2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1). 3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the clock by one of the following settings: · USB_CLK_RECOVER_IRC_EN[IRC_EN]=1 or · MCG operating in an external clocking mode and MCG_C7[OSCSEL]=10 or MCG_C5[PLLCLKEN0]=1, or · SIM_SOPT2[PLLFLLSEL]=11 5.4.3.3 Oscillator electrical specifications 5.4.3.3.1 Oscillator DC electrical specifications Table 57. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDOSC Supply current -- low-power mode (HGO=0) · 32 kHz -- 500 -- nA · 4 MHz -- 200 -- A · 8 MHz (RANGE=01) -- 300 -- A · 16 MHz -- 950 -- A · 24 MHz -- 1.2 -- mA · 32 MHz -- 1.5 -- mA IDDOSC Supply current -- high-gain mode (HGO=1) · 32 kHz -- 25 -- A · 4 MHz -- 400 -- A · 8 MHz (RANGE=01) -- 500 -- A · 16 MHz -- 2.5 -- mA -- 3 -- mA Table continues on the next page... Notes 1 1 KS22/KS20 Microcontroller, Rev. 3, 04/2016 83 NXP Semiconductors Electrical characteristics Table 57. Oscillator DC electrical specifications (continued) Symbol Description · 24 MHz · 32 MHz Min. Typ. Max. Unit -- 4 -- mA Cx EXTAL load capacitance -- -- -- Cy XTAL load capacitance -- -- -- RF Feedback resistor -- low-frequency, low-power -- -- -- M mode (HGO=0) Feedback resistor -- low-frequency, high-gain -- 10 -- M mode (HGO=1) Feedback resistor -- high-frequency, lowpower mode (HGO=0) -- -- -- M Feedback resistor -- high-frequency, high-gain -- 1 -- M mode (HGO=1) RS Series resistor -- low-frequency, low-power -- -- -- k mode (HGO=0) Series resistor -- low-frequency, high-gain mode (HGO=1) -- 200 -- k Series resistor -- high-frequency, low-power -- -- -- k mode (HGO=0) Series resistor -- high-frequency, high-gain mode (HGO=1) -- 0 -- k Vpp5 Peak-to-peak amplitude of oscillation (oscillator -- 0.6 -- V mode) -- low-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator -- VDD -- V mode) -- low-frequency, high-gain mode (HGO=1) Peak-to-peak amplitude of oscillation (oscillator -- 0.6 -- V mode) -- high-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator -- VDD -- V mode) -- high-frequency, high-gain mode (HGO=1) Notes 2, 3 2, 3 2, 4 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation 3. Cx and Cy can be provided by using either integrated capacitors or external components. 4. When low-power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other device. 84 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics 5.4.3.3.2 Oscillator frequency specifications Table 58. Oscillator frequency specifications Symbol Description fosc_lo Oscillator crystal or resonator frequency -- lowfrequency mode (MCG_C2[RANGE]=00) fosc_hi_1 Oscillator crystal or resonator frequency -- high-frequency mode (low range) (MCG_C2[RANGE]=01) fosc_hi_2 Oscillator crystal or resonator frequency -- high frequency mode (high range) (MCG_C2[RANGE]=1x) fec_extal tdc_extal tcst Input clock frequency (external clock mode) Input clock duty cycle (external clock mode) Crystal startup time -- 32 kHz low-frequency, low-power mode (HGO=0) Crystal startup time -- 32 kHz low-frequency, high-gain mode (HGO=1) Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) Min. 32 3 8 -- 40 -- -- -- -- Typ. -- -- -- -- 50 750 250 0.6 1 Max. 40 8 32 50 60 -- -- -- -- Unit kHz MHz MHz MHz % ms ms ms ms Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 5.4.3.4 32 kHz oscillator electrical characteristics 5.4.3.4.1 32 kHz oscillator DC electrical specifications Table 59. 32kHz oscillator DC electrical specifications Symbol VBAT RF Cpara Vpp1 Description Supply voltage Internal feedback resistor Parasitical capacitance of EXTAL32 and XTAL32 Peak-to-peak amplitude of oscillation Min. Typ. Max. Unit 1.71 -- 3.6 V -- 100 -- M -- 5 7 pF -- 0.6 -- V 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. KS22/KS20 Microcontroller, Rev. 3, 04/2016 85 NXP Semiconductors Electrical characteristics 5.4.3.4.2 32 kHz oscillator frequency specifications Table 60. 32 kHz oscillator frequency specifications Symbol Description fosc_lo tstart fec_extal32 vec_extal32 Oscillator crystal Crystal start-up time Externally provided input clock frequency Externally provided input clock amplitude Min. Typ. Max. Unit -- 32.768 -- kHz -- 1000 -- ms -- 32.768 -- kHz 700 -- VBAT mV Notes 1 2 2, 3 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock must be within the range of VSS to VBAT. 5.4.4 Memories and memory interfaces 5.4.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 5.4.4.1.1 Flash timing specifications -- program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 61. NVM program/erase timing specifications Symbol thvpgm4 thversscr thversall Description Longword Program high-voltage time Sector Erase high-voltage time Erase All high-voltage time Min. -- -- -- Typ. 7.5 13 104 Max. 18 113 904 Unit Notes s -- ms 1 ms 1 1. Maximum time based on expectations at cycling end-of-life. 5.4.4.1.2 Flash timing specifications -- commands Table 62. Flash command timing specifications Symbol Description Min. Typ. trd1sec2k Read 1s Section execution time (flash sector) -- -- tpgmchk Program Check execution time -- -- trdrsrc Read Resource execution time -- -- Table continues on the next page... Max. 60 45 30 Unit Notes s 1 s 1 s 1 86 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics Table 62. Flash command timing specifications (continued) Symbol tpgm4 tersscr trd1all trdonce tpgmonce tersall tvfykey Description Program Longword execution time Erase Flash Sector execution time Read 1s All Blocks execution time Read Once execution time Program Once execution time Erase All Blocks execution time Verify Backdoor Access Key execution time Min. Typ. Max. Unit -- 65 145 s -- 14 114 ms -- -- 1.8 ms -- -- 30 s -- 100 -- s -- 175 1300 ms -- -- 30 s Notes -- 2 1 1 -- 2 1 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 5.4.4.1.3 Flash high voltage current behaviors Table 63. Flash high voltage current behaviors Symbol Description Min. Typ. Max. Unit IDD_PGM Average current adder during high voltage -- 2.5 6.0 mA flash programming operation IDD_ERS Average current adder during high voltage -- 1.5 4.0 mA flash erase operation 5.4.4.1.4 Reliability specifications Table 64. NVM reliability specifications Symbol Description tnvmretp10k tnvmretp1k nnvmcycp Data retention after up to 10 K cycles Data retention after up to 1 K cycles Cycling endurance Min. Program Flash 5 20 10 K Typ.1 50 100 50 K Max. -- -- -- Unit years years cycles Notes -- -- 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at 40 °C Tj 125 °C. 5.4.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. KS22/KS20 Microcontroller, Rev. 3, 04/2016 87 NXP Semiconductors Electrical characteristics 5.4.6 Analog 5.4.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 65 and Table 66 are achievable on the differential pins ADCx_DPx, ADCx_DMx. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 5.4.6.1.1 16-bit ADC operating conditions Table 65. 16-bit ADC operating conditions Symbol VDDA VDDA VSSA VREFH VREFL VADIN Description Supply voltage Supply voltage Ground voltage ADC reference voltage high ADC reference voltage low Input voltage Conditions Absolute Delta to VDD (VDD VDDA) Delta to VSS (VSS VSSA) · 16-bit differential mode · All other modes CADIN Input capacitance · 16-bit mode · 8-bit / 10-bit / 12-bit modes Min. 1.71 -100 -100 1.13 VSSA VREFL VREFL -- -- Typ.1 -- 0 0 VDDA VSSA -- -- 8 4 Max. 3.6 +100 +100 VDDA VSSA 31/32 * VREFH VREFH 10 5 RADIN RAS Input series resistance Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz -- 2 5 -- -- 5 fADCK ADC conversion 13-bit mode 1.0 clock frequency fADCK ADC conversion 16-bit mode 2.0 clock frequency Crate ADC conversion 13-bit modes rate No ADC hardware averaging 20 Continuous conversions enabled, subsequent conversion time Crate ADC conversion 16-bit mode rate No ADC hardware averaging 37 -- 24.0 -- 12.0 -- 1200 -- 461 Unit V mV mV V V V pF k k MHz MHz Ksps Ksps Notes 2 2 3 4 4 5 5 88 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics Symbol Description Table 65. 16-bit ADC operating conditions Conditions Continuous conversions enabled, subsequent conversion time Min. Typ.1 Max. Unit Notes 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. ZAS RAS SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE VAS CAS VADIN INPUT PIN INPUT PIN INPUT PIN RADIN RADIN RADIN CADIN Figure 24. ADC input impedance equivalency diagram 5.4.6.1.2 16-bit ADC electrical characteristics Table 66. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description Conditions1 Min. Typ.2 Max. Unit IDDA_ADC Supply current 0.215 -- 1.7 mA fADACK ADC asynchronous clock source · ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz Table continues on the next page... Notes 3 tADACK = 1/ fADACK KS22/KS20 Microcontroller, Rev. 3, 04/2016 89 NXP Semiconductors Electrical characteristics Table 66. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description Conditions1 · ADLPC = 1, ADHSC = 1 Min. 2.4 Typ.2 4.0 Max. 6.1 Unit MHz Notes · ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz · ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error · 12-bit modes · <12-bit modes -- ±4 ±6.8 LSB4 5 -- ±1.4 ±2.1 DNL Differential nonlinearity · 12-bit modes · <12-bit modes INL Integral non-linearity · 12-bit modes · <12-bit modes EFS Full-scale error EQ Quantization error · 12-bit modes · <12-bit modes · 16-bit modes · 13-bit modes -- ±0.7 1.1 to LSB4 5 +1.9 -- ±0.2 0.3 to 0.5 -- ±1.0 2.7 to LSB4 5 +1.9 -- ±0.5 0.7 to +0.5 -- 4 5.4 LSB4 VADIN = VDDA5 -- 1.4 1.8 -- 1 to 0 -- LSB4 -- -- ±0.5 ENOB Effective number of 16-bit differential mode bits · Avg = 32 6 12.8 14.5 -- bits · Avg = 4 11.9 13.8 -- bits 16-bit single-ended mode · Avg = 32 · Avg = 4 12.2 13.9 -- 11.4 13.1 bits -- bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode · Avg = 32 dB 7 -- -94 -- dB 16-bit single-ended mode · Avg = 32 -- -85 -- SFDR Spurious free dynamic range 16-bit differential mode · Avg = 32 82 95 -- dB 7 -- dB 16-bit single-ended mode 78 90 · Avg = 32 Table continues on the next page... 90 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics Table 66. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature 1.55 1.62 1.69 mV/°C 8 range of the device VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. 8. ADC conversion clock < 3 MHz ENOB 15.00 Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 Hardware Averaging Disabled 12.30 12.00 Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 25. Typical ENOB vs. ADC_CLK for 16-bit differential mode KS22/KS20 Microcontroller, Rev. 3, 04/2016 91 NXP Semiconductors Electrical characteristics ENOB 14.00 Typical ADC 16-bit Single-Ended ENOB vs ADC Clock 100Hz, 90% FS Sine Input 13.75 13.50 13.25 13.00 12.75 12.50 12.25 12.00 11.75 11.50 11.25 Averaging of 4 samples 11.00 Averaging of 32 samples 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 26. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 5.4.6.2 CMP and 6-bit DAC electrical specifications Table 67. Comparator and 6-bit DAC electrical specifications Symbol VDD IDDHS IDDLS VAIN VAIO VH Description Supply voltage Supply current, High-speed mode (EN=1, PMODE=1) Supply current, low-speed mode (EN=1, PMODE=0) Analog input voltage Analog input offset voltage Analog comparator hysteresis1 · CR0[HYSTCTR] = 00 · CR0[HYSTCTR] = 01 · CR0[HYSTCTR] = 10 · CR0[HYSTCTR] = 11 Min. 1.71 -- -- VSS 0.3 -- Typ. -- -- -- -- -- -- 5 -- 10 -- 20 -- 30 Max. 3.6 200 20 VDD 20 -- -- -- -- VCMPOh Output high VDD 0.5 -- -- VCMPOl Output low -- -- 0.5 tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 Analog comparator initialization delay2 -- -- 40 IDAC6b INL 6-bit DAC current adder (enabled) 6-bit DAC integral non-linearity -- 7 -- 0.5 -- 0.5 DNL 6-bit DAC differential non-linearity 0.3 -- 0.3 Unit V A A V mV mV mV mV mV V V ns ns s A LSB3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD0.6 V. 92 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 0.08 0.07 CMP Hystereris (V) 0.06 0.05 0.04 0.03 HYSTCTR Setting 00 01 10 11 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 27. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) KS22/KS20 Microcontroller, Rev. 3, 04/2016 93 NXP Semiconductors Electrical characteristics CMP Hysteresis (V) 0.18 0.16 0.14 0.12 HYSTCTR Setting 0.1 00 01 0.08 10 11 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 28. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 5.4.6.3 12-bit DAC electrical characteristics 5.4.6.3.1 12-bit DAC operating requirements Table 68. 12-bit DAC operating requirements Symbol VDDA VDACR CL IL Desciption Supply voltage Reference voltage Output load capacitance Output load current Min. 1.71 1.13 -- -- Max. 3.6 3.6 100 1 Unit Notes V V 1 pF 2 mA 1. The DAC reference can be selected to be VDDA or VREFH. 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC 94 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics 5.4.6.3.2 12-bit DAC operating behaviors Table 69. 12-bit DAC operating behaviors Symbol Description IDDA_DACL Supply current -- low-power mode P IDDA_DACH Supply current -- high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) -- low-power mode tDACHP Full-scale settling time (0x080 to 0xF7F) -- high-power mode tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) -- low-power mode and highspeed mode Vdacoutl DAC output voltage range low -- highspeed mode, no load, DAC set to 0x000 Vdacouth DAC output voltage range high -- highspeed mode, no load, DAC set to 0xFFF INL Integral non-linearity error -- high speed mode DNL Differential non-linearity error -- VDACR > 2 V DNL Differential non-linearity error -- VDACR = VREF_OUT VOFFSET EG PSRR TCO TGE Rop Offset error Gain error Power supply rejection ratio, VDDA 2.4 V Temperature coefficient offset voltage Temperature coefficient gain error Output resistance (load = 3 k) SR Slew rate -80h F7Fh 80h · High power (SPHP) · Low power (SPLP) Min. -- -- -- -- -- -- VDACR -100 -- -- -- -- -- 60 -- -- -- 1.2 0.05 Typ. -- -- 100 15 0.7 -- -- -- -- -- ±0.4 ±0.1 -- 3.7 0.000421 -- 1.7 0.12 Max. 330 1200 200 30 1 100 VDACR ±8 ±1 ±1 ±0.8 ±0.6 90 -- -- 250 -- -- BW 3dB bandwidth · High power (SPHP) · Low power (SPLP) 550 -- -- 40 -- -- Unit A A s s s mV mV LSB LSB LSB %FSR %FSR dB V/C %FSR/C V/s kHz Notes 1 1 1 2 3 4 5 5 6 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR -100 mV 3. The DNL is measured for 0 + 100 mV to VDACR -100 mV 4. The DNL is measured for 0 + 100 mV to VDACR -100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR - 100 mV 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device KS22/KS20 Microcontroller, Rev. 3, 04/2016 95 NXP Semiconductors Electrical characteristics DAC12 INL (LSB) 8 6 4 2 0 -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 29. Typical INL error vs. digital code 96 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics 1.499 1.4985 DAC12 Mid Level Code Voltage 1.498 1.4975 1.497 1.4965 1.496 -40 25 55 85 105 125 Temperature °C Figure 30. Offset at half scale vs. temperature 5.4.7 Timers See General switching specifications. 5.4.8 Communication interfaces 5.4.8.1 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-todate standards, visit usb.org. KS22/KS20 Microcontroller, Rev. 3, 04/2016 97 NXP Semiconductors Electrical characteristics NOTE The MCGPLLCLK meets the USB jitter and signaling rate specifications for certification with the use of an external clock/crystal for both Device and Host modes. The MCGFLLCLK does not meet the USB jitter or signaling rate specifications for certification. The IRC48M meets the USB jitter and signaling rate specifications for certification in Device mode when the USB clock recovery mode is enabled. It does not meet the USB signaling rate specifications for certification in Host mode operation. 5.4.8.2 DSPI switching specifications (limited voltage range) The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the SPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 70. Master mode DSPI timing (limited voltage range) Num DS1 DS2 DS3 Description Operating voltage Frequency of operation DSPI_SCK output cycle time DSPI_SCK output high/low time DSPI_PCSn valid to DSPI_SCK delay DS4 DSPI_SCK to DSPI_PCSn invalid delay DS5 DSPI_SCK to DSPI_SOUT valid DS6 DSPI_SCK to DSPI_SOUT invalid DS7 DSPI_SIN to DSPI_SCK input setup DS8 DSPI_SCK to DSPI_SIN input hold Min. 2.7 -- 2 x tBUS (tSCK/2) - 2 (tBUS x 2) - 2 (tBUS x 2) - 2 -- -2 16.2 0 Max. 3.6 30 -- (tSCK/2) + 2 -- -- 8.5 -- -- -- Unit V MHz ns ns ns ns ns ns ns ns Notes 1 2 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. 98 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics DSPI_PCSn DSPI_SCK (CPOL=0) DSPI_SIN DSPI_SOUT DS3 DS2 DS1 DS4 DS8 DS7 First data DS5 First data Data Last data DS6 Data Last data Num DS9 DS10 DS11 DS12 DS13 DS14 DS15 DS16 Figure 31. DSPI classic SPI timing -- master mode Table 71. Slave mode DSPI timing (limited voltage range) Description Operating voltage Frequency of operation DSPI_SCK input cycle time DSPI_SCK input high/low time DSPI_SCK to DSPI_SOUT valid DSPI_SCK to DSPI_SOUT invalid DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSPI_SIN input hold DSPI_SS active to DSPI_SOUT driven DSPI_SS inactive to DSPI_SOUT not driven Min. Max. 2.7 3.6 -- 15 4 x tBUS (tSCK/2) - 2 -- -- (tSCK/2) + 2 21.4 0 -- 2.6 -- 7 -- -- 17 -- 17 Unit V MHz ns ns ns ns ns ns ns ns Notes 1 1. The maximum operating frequency is measured with noncontinuous CS and SCK. When DSPI is configured with continuous CS and SCK, the SPI clock must not be greater than 1/6 of the bus clock. For example, when the bus clock is 60 MHz, the SPI clock must not be greater than 10 MHz. DSPI_SS DSPI_SCK (CPOL=0) DSPI_SOUT DSPI_SIN DS10 DS15 DS13 First data DS14 First data DS12 Data Data DS9 DS11 DS16 Last data Last data Figure 32. DSPI classic SPI timing -- slave mode KS22/KS20 Microcontroller, Rev. 3, 04/2016 99 NXP Semiconductors Electrical characteristics 5.4.8.3 DSPI switching specifications (full voltage range) The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the SPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 72. Master mode DSPI timing (full voltage range) Num DS1 DS2 DS3 Description Operating voltage Frequency of operation DSPI_SCK output cycle time DSPI_SCK output high/low time DSPI_PCSn valid to DSPI_SCK delay DS4 DSPI_SCK to DSPI_PCSn invalid delay DS5 DSPI_SCK to DSPI_SOUT valid DS6 DSPI_SCK to DSPI_SOUT invalid DS7 DSPI_SIN to DSPI_SCK input setup DS8 DSPI_SCK to DSPI_SIN input hold Min. 1.71 -- 4 x tBUS (tSCK/2) - 4 (tBUS x 2) - 4 (tBUS x 2) - 4 -- -4.5 24.6 0 Max. 3.6 15 -- (tSCK/2) + 4 -- -- 10 -- -- -- Unit V MHz ns ns ns ns ns ns ns ns Notes 1 2 3 1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DSPI_SCK (CPOL=0) DSPI_SIN DSPI_SOUT DS3 DS2 DS1 DS4 DS7 DS8 First data DS5 First data Data Last data DS6 Data Last data Figure 33. DSPI classic SPI timing -- master mode 100 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics Num DS9 DS10 DS11 DS12 DS13 DS14 DS15 DS16 Table 73. Slave mode DSPI timing (full voltage range) Description Operating voltage Frequency of operation DSPI_SCK input cycle time DSPI_SCK input high/low time DSPI_SCK to DSPI_SOUT valid DSPI_SCK to DSPI_SOUT invalid DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSPI_SIN input hold DSPI_SS active to DSPI_SOUT driven DSPI_SS inactive to DSPI_SOUT not driven Min. 1.71 -- 8 x tBUS (tSCK/2) - 4 -- 0 3.2 7 -- -- Max. 3.6 7.5 -- (tSCK/2) + 4 29.5 -- -- -- 25 25 Unit V MHz ns ns ns ns ns ns ns ns DSPI_SS DSPI_SCK (CPOL=0) DSPI_SOUT DSPI_SIN DS10 DS15 DS13 First data DS14 First data DS12 Data Data DS9 DS11 DS16 Last data Last data Figure 34. DSPI classic SPI timing -- slave mode 5.4.8.4 LPI2C Table 74. LPI2C specifications Symbol Description fSCL SCL clock frequency Min. Max. Unit Notes Standard mode (Sm) 0 100 kHz 1 Fast mode (Fm) 0 400 1, 2 Fast mode Plus (Fm+) 0 1000 1, 3 Ultra Fast mode (UFm) 0 5000 1, 4 High speed mode (Hs-mode) 0 3400 1, 5 1. See General switching specifications, measured at room temperature. 2. Measured with the maximum bus loading of 400pF at 3.3V VDD with pull-up Rp = 220 , and at 1.8V VDD with Rp = 880. For all other cases, select appropriate Rp per I2C Bus Specification and the pin drive capability. 3. Fm+ is only supported on high drive pin with high drive enabled. It is measured with the maximum bus loading of 400pF at 3.3V VDD with Rp = 220. For all other cases, select appropriate Rp per I2C Bus Specification and the pin drive capability. KS22/KS20 Microcontroller, Rev. 3, 04/2016 101 NXP Semiconductors Electrical characteristics 4. UFm is only supported on high drive pin with high drive enabled and push-pull output only mode. It is measured at 3.3V VDD with the maximum bus loading of 400pF. For 1.8V VDD, the maximum speed is 4Mbps. 5. Hs-mode is only supported in slave mode and on the high drive pins with high drive enabled. 5.4.8.5 UART switching specifications See General switching specifications. 5.4.8.6 I2S/SAI switching specifications This section provides the AC timing for the I2S/SAI module in master mode (clocks are driven) and slave mode (clocks are input). All timing is given for noninverted serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) signal shown in the following figures. 5.4.8.6.1 Normal Run, Wait and Stop mode performance over a limited operating voltage range This section provides the operating performance over a limited operating voltage for the device in Normal Run, Wait and Stop modes. Table 75. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage range) Num. S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 Characteristic Min. Operating voltage 2.7 I2S_MCLK cycle time 40 I2S_MCLK pulse width high/low 45% I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ -- I2S_RX_FS output valid I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ 0 I2S_RX_FS output invalid I2S_TX_BCLK to I2S_TXD valid -- I2S_TX_BCLK to I2S_TXD invalid 0 I2S_RXD/I2S_RX_FS input setup before 18 I2S_RX_BCLK I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 Max. 3.6 -- 55% -- 55% 15 -- 15 -- -- -- Unit V ns MCLK period ns BCLK period ns ns ns ns ns ns 102 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics I2S_MCLK (output) I2S_TX_BCLK/ I2S_RX_BCLK (output) I2S_TX_FS/ I2S_RX_FS (output) I2S_TX_FS/ I2S_RX_FS (input) I2S_TXD I2S_RXD S1 S2 S2 S3 S4 S4 S5 S9 S7 S9 S10 S7 S8 S6 S10 S8 Figure 35. I2S/SAI timing -- master modes Table 76. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage range) Num. S11 S12 S13 S14 S15 S16 S17 S18 S19 Characteristic Min. Operating voltage 2.7 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% (input) I2S_TX_FS/I2S_RX_FS input setup before 4.5 I2S_TX_BCLK/I2S_RX_BCLK I2S_TX_FS/I2S_RX_FS input hold after 2 I2S_TX_BCLK/I2S_RX_BCLK I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output 0 invalid I2S_RXD setup before I2S_RX_BCLK 4.5 I2S_RXD hold after I2S_RX_BCLK 2 I2S_TX_FS input assertion to I2S_TXD output valid1 -- Max. 3.6 -- 55% -- -- 20 -- -- -- 25 Unit V ns MCLK period ns ns ns ns ns ns ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear KS22/KS20 Microcontroller, Rev. 3, 04/2016 103 NXP Semiconductors Electrical characteristics I2S_TX_BCLK/ I2S_RX_BCLK (input) I2S_TX_FS/ I2S_RX_FS (output) I2S_TX_FS/ I2S_RX_FS (input) I2S_TXD I2S_RXD S11 S12 S15 S13 S19 S15 S12 S15 S16 S17 S18 S16 S14 S16 Figure 36. I2S/SAI timing -- slave modes 5.4.8.6.2 Normal Run, Wait and Stop mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 77. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 Characteristic Min. Operating voltage 1.71 I2S_MCLK cycle time 40 I2S_MCLK pulse width high/low 45% I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ -- I2S_RX_FS output valid I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ -1.0 I2S_RX_FS output invalid I2S_TX_BCLK to I2S_TXD valid -- I2S_TX_BCLK to I2S_TXD invalid 0 I2S_RXD/I2S_RX_FS input setup before 27 I2S_RX_BCLK I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 Max. 3.6 -- 55% -- 55% 15 -- 15 -- -- -- Unit V ns MCLK period ns BCLK period ns ns ns ns ns ns 104 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics I2S_MCLK (output) I2S_TX_BCLK/ I2S_RX_BCLK (output) I2S_TX_FS/ I2S_RX_FS (output) I2S_TX_FS/ I2S_RX_FS (input) I2S_TXD I2S_RXD S1 S2 S2 S3 S4 S4 S5 S9 S7 S9 S10 S7 S8 S6 S10 S8 Figure 37. I2S/SAI timing -- master modes Table 78. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. S11 S12 S13 S14 S15 S16 S17 S18 S19 Characteristic Min. Operating voltage 1.71 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% (input) I2S_TX_FS/I2S_RX_FS input setup before 5.8 I2S_TX_BCLK/I2S_RX_BCLK I2S_TX_FS/I2S_RX_FS input hold after 2 I2S_TX_BCLK/I2S_RX_BCLK I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output 0 invalid I2S_RXD setup before I2S_RX_BCLK 5.8 I2S_RXD hold after I2S_RX_BCLK 2 I2S_TX_FS input assertion to I2S_TXD output valid1 -- Max. 3.6 -- 55% -- -- 28.5 -- -- -- 26.3 Unit V ns MCLK period ns ns ns ns ns ns ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear KS22/KS20 Microcontroller, Rev. 3, 04/2016 105 NXP Semiconductors Electrical characteristics I2S_TX_BCLK/ I2S_RX_BCLK (input) I2S_TX_FS/ I2S_RX_FS (output) I2S_TX_FS/ I2S_RX_FS (input) I2S_TXD I2S_RXD S11 S12 S15 S13 S19 S15 S12 S15 S16 S17 S18 S16 S14 S16 Figure 38. I2S/SAI timing -- slave modes 5.4.8.6.3 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. Table 79. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 Characteristic Min. Operating voltage 1.71 I2S_MCLK cycle time 62.5 I2S_MCLK pulse width high/low 45% I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ -- I2S_RX_FS output valid I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ -1 I2S_RX_FS output invalid I2S_TX_BCLK to I2S_TXD valid -- I2S_TX_BCLK to I2S_TXD invalid I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 Max. 3.6 -- 55% -- 55% 45 -- 45 -- -- -- Unit V ns MCLK period ns BCLK period ns ns ns ns ns ns 106 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Electrical characteristics I2S_MCLK (output) I2S_TX_BCLK/ I2S_RX_BCLK (output) I2S_TX_FS/ I2S_RX_FS (output) I2S_TX_FS/ I2S_RX_FS (input) I2S_TXD I2S_RXD S1 S2 S2 S3 S4 S4 S5 S9 S7 S9 S10 S7 S8 S6 S10 S8 Figure 39. I2S/SAI timing -- master modes Table 80. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. S11 S12 S13 S14 S15 S16 S17 S18 S19 Characteristic Min. Operating voltage 1.71 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% (input) I2S_TX_FS/I2S_RX_FS input setup before 30 I2S_TX_BCLK/I2S_RX_BCLK I2S_TX_FS/I2S_RX_FS input hold after 7 I2S_TX_BCLK/I2S_RX_BCLK I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output 0 invalid I2S_RXD setup before I2S_RX_BCLK 30 I2S_RXD hold after I2S_RX_BCLK 4 I2S_TX_FS input assertion to I2S_TXD output valid1 -- Max. 3.6 -- 55% -- -- -- -- -- 72 Unit V ns MCLK period ns ns ns ns ns ns ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear KS22/KS20 Microcontroller, Rev. 3, 04/2016 107 NXP Semiconductors Design considerations I2S_TX_BCLK/ I2S_RX_BCLK (input) I2S_TX_FS/ I2S_RX_FS (output) I2S_TX_FS/ I2S_RX_FS (input) I2S_TXD I2S_RXD S11 S12 S15 S13 S19 S15 S12 S15 S16 S17 S18 Figure 40. I2S/SAI timing -- slave modes S16 S14 S16 6 Design considerations 6.1 Hardware design considerations This device contains protective circuitry to guard against damage due to high static voltage or electric fields. However, take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. 6.1.1 Printed circuit board recommendations · Place connectors or cables on one edge of the board and do not place digital circuits between connectors. · Drivers and filters for I/O functions must be placed as close to the connectors as possible. Connect TVS devices at the connector to a good ground. Connect filter capacitors at the connector to a good ground. · Physically isolate analog circuits from digital circuits if possible. · Place input filter capacitors as close to the MCU as possible. · For best EMC performance, route signals as transmission lines; use a ground plane directly under LQFP packages; and solder the exposed pad (EP) to ground directly under QFN packages. 108 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Design considerations 6.1.2 Power delivery system Consider the following items in the power delivery system: · Use a plane for ground. · Use a plane for MCU VDD supply if possible. · Always route ground first, as a plane or continuous surface, and never as sequential segments. · Route power next, as a plane or traces that are parallel to ground traces. · Place bulk capacitance, 10 F or more, at the entrance of the power plane. · VPlDacDe/bVySpSaspsacira,piancciltuodrsinfgorVMDCDUA/pVoSwSeAr domain as close as possible and VREFH/VREFL. to each · The minimum bypass requirement is to place 0.1 F capacitors positioned as near as possible to the package supply pins. · The USB_V DD voltage range is 3.0 V to 3.6 V. It is recommended to include a filter circuit with one bulk capacitor (no less than 2.2 F) and one 0.1 F capacitor at the USB_VDD pin to improve USB performance. 6.1.3 Analog design Each ADC input must have an RC filter as shown in the following figure. The mreqaxuiimreudm. TvhaeluvealoufeRofmCusmt ubset RAS max if fast sampling and high resolution be chosen to ensure that the RC time constant are is very small compared to the sample period. Input signal MCU 1 2 R C ADCx 21 Figure 41. RC circuit for ADC input High voltage measurement circuits require voltage division, current limiting, and over-voltage protection as shown the following figure. The voltage divider formed by R1 R4 must limited to less ythiealnd a voltage less than or equal to VREFH. The current must be the injection current limit. Since the ADC pins do not have diodes to VDD, external clamp diodes must be included to protect against transient over- voltages. KS22/KS20 Microcontroller, Rev. 3, 04/2016 109 NXP Semiconductors Design considerations D Analog input 1 2 R 1 ADCx C 2 R1 1 2 MCU VDD OSCILL EXTAL 1 RF High voltage input R2 1 2 R3 1 2 MCU 2 1 R44 1 3 R5 1 2 2 BAT54SW 2 1 ADCx C OSCILLATOR EXTAL XTAL 1 3 CRY OSCILLAT EXTAL Figure 42. High voltage measurement with an ADC inp1ut 2 CRYSTAL Analog input 1 2 ADCx VDD 1 R 6.1.4 Digital designC 2 1 1 VDD MCU 10k Ensure that C 2 1 1 2 aVDRlDlDEoI/SnOEoTpt ip_nrbsopvc0iai.1ndunF.enVDopDtogwMeetCrUp35791tuoHDlJRlI1C_e/5OXd2A246810apUbiTnosvSSRIWWEOeSpDDE__TrNDCV_ILiObKoDrDto(VMDaxD,I/eROEsSpETie_sbEcXViTaOADl1SLlDyCIL+tRLhFA0eT1.0O3k02.R1VuFX)T.AL 2 12 1 RESET_b 10k RS 2 · RESET_b 1pinR5 2 ADCx 2 1 2 1 2 1 CRYST Cx 2 OSCILLAT EXTAL 1 RF 1 2 1 3 1 2 1 R4 The RESET_b pin is an open-drain I/O pin that has an internal pullCuRYpSTrAeLsistor. An Cx CRYST 2 1 external2RC circuit isCrecommended to filter noise as shown in the following figure. 2 The resistor cBAaTp54aSWcitance value value must is 0.1 be in the F. The range of 4.7 kSupteorvis1or0Chikp ; the recomVDmD ended MCU RESET_b pin also has a selectable digital filter to 1 reject spurious noise. 10k VDD OUT 1 2 RESET_b 12 1 VDD MCAoUpcetivnedhraiginh, RS VDD 0.1uF MCU 2 1 1 10k J1 1 2 3 4 5 6 7 8 9 10 HDR_5X2 1 2 SWD_DIO SWD_CLK RESET_bB 10k 2 RESET_b 12 10k 0.1uF RESET_b 2 10k NMI_b 2 Figure 43. Reset circuit Supervisor Chip 110 NXP Semiconductors OUT 1 2 1 VDD 10k 2 MCU KS22/KS20 Microcontroller, Rev. 3, 04/2016 RESET_b J1 1 2 3 4 5 6 7 8 9 10 2 SWD_DIO SWD_CLK RESET_b RESET_b 12 10k 10k 2 0.1uF RESET_b Design considerations 1 2 HDR_5X2 When an external supervisor chip is connected to the RESET_b pin, a series re10skistor must be used to avoid damaging the supervisor chip or the RESET_b pin, 2 as shown in the following figure. The series resistor value (RS below) must be in the range of 100 to 1 k depending on the external reset chip drive strength. 4 The supervisor chip must have an active high, op3en-drain output. MCU DCx MCU DCx Supervisor ChOipSCILLATOR VDD OSCILLATOR MCU OSCILLATOR EXTAL XTAL EXTAL XTAL EXTAL XTAL 1 1 2 1 2 1 3 1 CRYSTAL 10k 1 CRYSTAL Cx Cy 2 RESONATOR 2 2 12 OUT 1 2 RESET_b Active high, RS open drain 0.1uF 2 OSCILLATOR OSCILLATOR OSCILLATOR EXTAL XTAL EXTAL XTAL EXTAL XTAL Figure 44. R1eset si2gnal connection to e1xternal2 reset chip 1 · NMI pin RF 1 RF 1 2 RF 1 RS RS RS Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low 2 2 level on this pin will trig1ger2non-maskable interrupt1. W2hen this pin is enable1d as 3 12 1 2 the NMI function, an extCeRYrSnTaALl pull-up resistCoxr (10 kCR)YSaTAsLshowCny in the following RESONATOR figure is recommended for robustness. 2 2 If the NMI_b pin is used as an I/O pin, the non-maskable interrupt handler is required to disable the NMI function by remapping to another function. The NMI function is disabled by programming the FOPT[NMI_DIS] bit to zero. 1 VDD MCU 10k RESET_b 0.1uF 2 1 VDD 10k MCU NMI_b 12 2 · Debug interface Figure 45. NMI pin biasing VDD MCU KS22/KS20 Microcontroller, Rev. 3, 04/2016 10k 1 2 RESET_b 111 NXP Semiconductors 12 Design considerations R1 1 2 MCU VDD This MCU uses the standard High voltage input AR1 MR2 S2WD interface protoco1 l aR5s s2hown iAnDCtxhe 3 1 following figure. While pull-up or pull-downR4 resistors are not required (SWD_DIO 1 has an internal pull-up and SWD1 _RC3 L2K has an1internal p2 ull-down), Cexternal 10 k 2 2 pull resistors are recommended for system robustness. The RESET_b pin BAT54SW recommendations mentioned above must also be considered. VDD VDD MCU 1 1 10k VDD J1 10k 2 C 1 2 SWD_DIO 3 4 SWD_CLK 12 1 5 6 7 8 RESET_b RESET_b 0.1uF 9 10 RESET_b 0.1uF 1 2 2 HDR_5X2 10k 2 Figure 46. SWD debug interface · Low leakage stop mode wakeup Supervisor Chip VDD 1 Select low leakage wakeup pins (LLWU_Px) to wake the MCU from one of the 10k low leakage stop modes (LLS/VLLSx). See the pinout table for pin selection. 12 OUT 1 2 · Unused pin Active high, RS open drain 0.1uF 2 Unused GPIO pins must be left floating (no electrical connections) with the MUX field of the pin's PORTx_PCRn register equal to 0:0:0. This disables the digital input path tBo the MCU. If the USB module is not used, leave the USB data pins (USB0_DP, USB0_DM) floating. Connect USB_VDD to ground through a 10 k resistor if the USB module is not used. MCU RESET_b 6.1.5 Crystal oscillator When using an external crystal or ceramic resonator as the frequency reference for the MCU clock system, refer to the following table and diagrams. The feedback resistor, RF, is incorporated internally with the low power oscillators. An external feedback is required when using high gain (HGO=1) mode. A 112 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Design considerations Internal load capacitors (Cx, Cy) are provided in the low frequency (32.786 kHz) mode. Use the SCxP bits in the OSC0_CR register to adjust the load capacitance for the crystal. Typically, values of 10pf to 16 pF are sufficient for 32.768 kHz crystals that have a 12.5 pF CL specification. The internal load capacitor selection must not be used for high frequency crystals and resonators. Table 81. External crystal/resonator connections Oscillator mode Oscillator mode Low frequency (32.768 kHz), low power Diagram 1 Low4frequency (32.768 kHz), high gain Diagram 2, Diagram 4 3 High frequency (3-32 MHz), low power Diagram 3 MCU High frequency (3-32 MHz), high gain 4 Diagram 4 OSCILLATOR EXTAL XTAL 3 OSCILLATOR EXTAL XTAL MCU ADCx ADCx OSCILLATOR EXTAL 1 2 XTAL CRYSTAL 1 2 OSCILLATOR EXTAL 1 X2TAL 1 CRYSTAL Cx 1 2 1 2 1 CRYSTAL Cx Figure 47. Crystal connection Diagram 1 2 CRYSTAL Cy 2 2 1 EXT Cy C MCU MCU OSCILLATOR EXTAOLSCILLATOR XTAL EXTAL XTAL 1 2 1 2 RF RF 11 RS RS OSCILLATOR OESXCTIALLLATOR XTAL EXTAL XTAL 1 2 1 1 2 RF 1 RF RS RS EXT 12 22 ADCx ADCx C 4 12 11 22 1 12 2 1 1 CCRYSSTTAALL CRYSTCARLYSTAL Cx Cx Cy Cy 2 2 Figure 438. Crystal connection Diagram 2 2 2 2 OSCILLATOR EXTAL XTAL 1 2 CRYSTAL OSCILLATOR EXTAL XTAL 1 2 1 1 CRYSTAL Cx Cy OSCILLATOR EXTAL XTAL 1 3 2 RESONATOR 2 2 RESET_b 2 1 VDD 1 VDD MCFUigure 49. Crystal conVnDeDction DiagraMmCU3 OSCILLATOR OSCILLATOR OSCILLATOR EXTAL MXTCALU EXTAL XTAL VDDEXTAL XTAL MCU 21 1 1 2 1 2 1 KS22/KS1200k MicrocRoF ntroller, Rev. 3, 04/2016 RF 1 12 12 RS RS 10k 2 RESET_b 1 2 1 2 1 CRYSTAL 0.1uF RESET_b Cx CRYSTAL Cy 2 1 2 10k RF 1 10k 1 2 RS NMI_b 3 2 RESONATORNMI_b 113 NXP Semiconductors 1 2 CRYSTAL Part identification OSCILLATOR EXTAL XTAL 1 2 1 RF RS 2 1 2 CRYSTAL 1 2 1 1 CRYSTAL Cx Cy 1 3 2 RESONATOR 2 2 OSCILLATOR EXTAL XTAL 1 2 1 RF RS 12 1 2 1 CRYSTAL Cx Cy OSCILLATOR EXTAL XTAL 1 2 1 RF RS 2 1 3 2 RESONATOR 2 2 Figure 50. Crystal connection Diagram 4 1 2 6.2 Software considerations AllVKDDinetis MCUs MarCeU supported by comprehensive Freescale and third-party hardware and software enablement solutions, which can reduce development costs and time to marke1t0.kFeatured software and tools are listed below. Visit http://www.freescale.com/ kinetis/sw for more information and supporting collateral. NMI_b Evaluation and Prototyping Hardware · MAPS Development Kit: http://www.freescale.com/KS IDEs for Kinetis MCUs · Kinetis Design Studio IDE: http://www.freescale.com/kds · Partner IDEs: http://www.freescale.com/kide Run-time Software · Kinetis SDK: http://www.freescale.com/ksdk · Kinetis Bootloader: http://www.freescale.com/kboot · ARM mbed Development Platform: http://www.freescale.com/mbed For all other partner-developed software and tools, visit http://www.freescale.com/ partners. 7 Part identification 114 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 Part identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 7.2 Format Part numbers for this device have the following format: Q KS## A FFF R T PP CC N 7.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Q KS## A FFF R T PP CC N Table 82. Part number fields description Description Qualification status Kinetis family Key attribute Program flash memory size Silicon revision Temperature range (°C) Package identifier Maximum CPU frequency (MHz) Packaging type Values · M = Fully qualified, general market flow · P = Prequalification · KS20 · KS22 · F = Cortex-M4 with DSP and FPU · 128 = 128 KB · 256 = 256 KB · (Blank) = Main · A = Revision after main · V = 40 to 105 · FT = 48 QFN (7 mm x 7 mm) · LH = 64 LQFP (10 mm x 10 mm) · LL = 100 LQFP (14 mm x 14 mm) · 12 = 120 MHz · R = Tape and reel · (Blank) = Trays 7.4 Example This is an example part number: MKS22FN256VLL12 KS22/KS20 Microcontroller, Rev. 3, 04/2016 115 NXP Semiconductors Revision history 8 Revision history The following table provides a revision history for this document. Table 83. Revision history Rev. No. 2 3 Date 12/2015 04/2016 Substantial Changes Initial public release. Added 48-pin QFN package. 116 NXP Semiconductors KS22/KS20 Microcontroller, Rev. 3, 04/2016 How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/SalesTermsandConditions. NXP, the NXP logo, Freescale, the Freescale logo and Kinetis are trademarks of NXP B.V.All other product or service names are the property of their respective owners. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. ©2016 NXP B.V. Document Number KS22P100M120SF0 Revision 3, 04/2016NXP USA v1