AD1981B AC '97 SoundMAX Codec
AC '97 2.3 Compatible Features
- S/PDIF output, 20-bit data format, supporting 48 kHz and 44.1 kHz sample rates
- Integrated stereo headphone amplifier
- Variable sample rate audio
- External audio power-down control
- >90 dB dynamic range
- Stereo full-duplex codec
- 20-bit PCM DAC
- 3 analog line-level stereo inputs for line-in, AUX, and CD
- Mono line-level phone input
- Dual MIC input with built-in programmable preamplifier
- High quality CD input with ground sense
- Mono output for speakerphone or internal speaker
- Power management support
- 48-lead LQFP package, Pb-free available
Enhanced Features
- Stereo MIC preamplifier support
- Built-in digital equalizer function for optimized speaker sound
- Full-duplex variable sample rates from 7040 Hz to 48 kHz with 1 Hz resolution
- Jack sense pins for automatic output switching
- Software-programmed Vmrout output for biasing microphone and external power amplifier
- Split power supplies: 3.3 V digital and 5 V analog
- Multiple codec configuration options
Functional Block Diagram
The functional block diagram illustrates the AD1981B's internal architecture, showing connections between the MIC preamp, record selector, CODEC core (ADC and DAC sections), AC '97 interface, PLL, EQ core storage, analog mixing control logic, and various output drivers.
Specifications
The specifications section details the performance characteristics of the AD1981B under standard test conditions. Key parameters include input/output voltage levels, impedance, dynamic range, signal-to-noise ratio, total harmonic distortion, and power supply requirements.
Test Conditions
Standard test conditions are applied unless otherwise noted:
- Temperature: 25°C
- Digital Supply (DV_DD): 3.3 V
- Analog Supply (AV_DD): 5.0 V
- Sample Rate (f_s): 48 kHz
- Input Signal: 1008 Hz
- Analog Output Pass Band: 20 Hz to 20 kHz
- DAC: Calibrated, -3 dB Attenuation Relative to Full Scale, 0 dB Input, 10 kΩ Output Load (LINE_OUT), 32 Ω Output Load (HP_OUT)
- ADC: Calibrated, 0 dB Gain, Input -3.0 dB Relative to Full Scale
General Specifications
This table outlines various analog and digital parameters:
| Parameter | Min | Typ | Max | Unit |
| ANALOG INPUT | ||||
| Input Voltage (RMS Values Assume Sine Wave Input) | ||||
| LINE_IN, AUX, CD, PHONE_IN | 1 | V rms | ||
| 2.83 | V p-p | |||
| MIC_IN with 20 dB Gain | 0.1 | V rms | ||
| 0.283 | V p-p | |||
| MIC_IN with 0 dB Gain | 1 | V rms | ||
| 2.83 | V p-p | |||
| Input Impedance¹ | 20 | kΩ | ||
| Input Capacitance¹ | 5 | 7.5 | pF | |
| MASTER VOLUME | ||||
| Step Size (0 dB to -46.5 dB): LINE_OUT_L, LINE_OUT_R | 1.5 | dB | ||
| Output Attenuation Range¹ | 46.5 | dB | ||
| Step Size (0 dB to -46.5 dB): MONO_OUT | 1.5 | dB | ||
| Output Attenuation Range¹ | 46.5 | dB | ||
| Step Size (0 dB to -46.5 dB): HP_OUT_R, HP_OUT_L | 1.5 | dB | ||
| Output Attenuation Range Span¹ | 46.5 | dB | ||
| Mute Attenuation of 0 dB Fundamental¹ | 80 | dB | ||
| PROGRAMMABLE GAIN AMPLIFIER—ADC | ||||
| Step Size (0 dB to 22.5 dB) | 1.5 | dB | ||
| PGA Gain Range | 22.5 | dB | ||
| ANALOG MIXER-INPUT GAIN/AMPLIFIERS/ATTENUATORS | ||||
| Signal-to-Noise Ratio (SNR) | ||||
| CD to LINE_OUT | 90 | dB | ||
| Other to LINE_OUT¹ | 90 | dB | ||
| Step Size (+12 dB to -34.5 dB) (All Steps Tested): MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC | 1.5 | dB | ||
| Input Gain/Attenuation Range: MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC | 46.5 | dB | ||
| DIGITAL DECIMATION AND INTERPOLATION FILTERS¹ | ||||
| Pass Band | 0 | 0.4 × f₅ | Hz | |
| Pass-Band Ripple | ±0.09 | dB | ||
| Transition Band | 0.4 × f₅ | 0.6 × f₅ | Hz | |
| Stop Band | 0.6 × f₅ | ∞ | Hz | |
| Stop-Band Rejection | -74 | dB | ||
| Group Delay | 16 / f₅ | s | ||
| Group Delay Variation over Pass Band | 0 | μs | ||
| ANALOG-TO-DIGITAL CONVERTERS | ||||
| Resolution | 16 | Bits | ||
| Total Harmonic Distortion (THD) | -84 | dB | ||
| Dynamic Range (-60 dB Input THD + N Referenced to Full Scale, A-Weighted) | 80 | 85 | dB | |
| Signal-to-Intermodulation Distortion¹ (CCIF Method) | 85 | dB | ||
| ADC Crosstalk¹ Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) | -80 | -80 | dB | |
| Line_In to Other | -100 | -80 | dB | |
| Gain Error² (Full-Scale Span Relative to Nominal Input Voltage) | ±10 | % | ||
| Interchannel Gain Mismatch (Difference of Gain Errors) | ±0.5 | dB | ||
| ADC Offset Error¹ | ±5 | mV | ||
| DIGITAL-TO-ANALOG CONVERTERS | ||||
| Resolution | 20 | Bits | ||
| Total Harmonic Distortion (THD) LINE_OUT | -85 | dB | ||
| Total Harmonic Distortion (THD) HP_OUT | -75 | dB | ||
| Dynamic Range (-60 dB Input THD + N Referenced to Full Scale, A-Weighted) | 85 | 90 | dB | |
| Signal-to-Intermodulation Distortion¹ (CCIF Method) | -100 | dB | ||
| Gain Error² (Output FS Voltage Relative to Nominal Output FS Voltage) | ±10 | % | ||
| Interchannel Gain Mismatch (Difference of Gain Errors) | ±0.7 | dB | ||
| DAC Crosstalk¹ (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) | -80 | dB | ||
| Total Audible Out-of-Band Energy¹ (Measured from 0.6 × f₅ to 20 kHz) | -40 | dB | ||
| ANALOG OUTPUT | ||||
| Full-Scale Output Voltage; LINE_OUT and MONO_OUT | 1 | V rms | ||
| 2.83 | V p-p | |||
| Output Impedance¹ | 800 | Ω | ||
| External Load Impedance¹ | 10 | kΩ | ||
| Output Capacitance¹ | 15 | pF | ||
| External Load Capacitance¹ | 100 | pF | ||
| Full-Scale Output Voltage; HP_OUT (0 dB Gain) | 1 | V rms | ||
| External Load Impedance¹ | 32 | Ω | ||
| V_REF | 2.05 | 2.25 | 2.45 | V |
| VREFOUT (Programmable to 3.70 V Nominal) | 2.25 | V | ||
| VREFOUT Current Drive | 5 | mA | ||
| Mute Click (Muted Output Minus Unmuted Midscale DAC Output) | ±5 | mV | ||
| STATIC DIGITAL SPECIFICATIONS | ||||
| High Level Input Voltage (V_IN): Digital Inputs | 0.65 × DV_DD | V | ||
| Low Level Input Voltage (V_LL) | 0.35 × DV_DD | V | ||
| High Level Output Voltage (V_OH), I_OH=2 mA | 0.9 × DV_DD | V | ||
| Low Level Output Voltage (V_OL), I_OL=2 mA | 0.1 × DV_DD | V | ||
| Input Leakage Current | -10 | +10 | μA | |
| Output Leakage Current | -10 | +10 | μA | |
| POWER SUPPLY | ||||
| Power Supply Range-Analog (AV_DD) | 4.5 | 5.5 | V | |
| Power Supply Range-Digital (DV_DD) | 3.0 | 3.47 | V | |
| Power Dissipation-5 V/3.3 V | 400 | mW | ||
| Analog Supply Current-5 V (AV_DD) | 50 | mA | ||
| Digital Supply Current-3.3 V (DV_DD) | 46 | mA | ||
| Power Supply Rejection (100 mV p-p Signal @ 1 kHz)¹ (At Both Analog and Digital Supply Pins, Both ADCs and DACs) | 40 | dB | ||
| CLOCK SPECIFICATIONS¹ | ||||
| Input Clock Frequency | 24.576 | MHz | ||
| Recommended Clock Duty Cycle | 40 | 50 | 60 | % |
¹Guaranteed but not tested.
²Measurements reflect main ADC.
Power-Down States
This section details the power consumption in various operating modes:
| Parameter | Set Bits | DV_DD Typ | AV_DD Typ | Unit |
| Fully Active | No Bits Value | 42 | 51 | mA |
| ADC | PR0 | 36 | 45 | mA |
| DAC | PR1 | 29 | 35 | mA |
| ADC + DAC | PR1, PR0 | 12 | 28 | mA |
| Mixer | PR2 | 42 | 24 | mA |
| ADC + Mixer | PR2, PR0 | 36 | 18 | mA |
| DAC + Mixer | PR2, PR1 | 29 | 9 | mA |
| ADC + DAC + Mixer | PR2, PR1, PR0 | 12 | 1.5 | mA |
| Standby | PR5, PR4, PR3, PR2, PR1, PR0 | 0 | 0 | mA |
| Headphone Standby | PR6 | 42 | 44 | mA |
Timing Parameters
Timing parameters are guaranteed over the operating temperature range. Key timing diagrams illustrate clock, signal rise/fall times, and AC-Link low power mode behavior.
| Parameter | Symbol | Min | Typ | Max | Unit |
| RESET Active Low Pulse Width | t_RST_LOW | 1.0 | ms | ||
| RESET Inactive to BIT_CLK Start-Up Delay | t_RST2CLK | 162.8 | ns | ||
| SYNC Active High Pulse Width | t_SYNC_HIGH | 1.3 | ms | ||
| SYNC Low Pulse Width | t_SYNC_LOW | 19.5 | μs | ||
| SYNC Inactive to BIT_CLK Start-Up Delay | t_SYNC2CLK | 162.8 | ns | ||
| BIT_CLK Frequency | 12.288 | MHz | |||
| BIT_CLK Frequency Accuracy | ±1 | ppm | |||
| BIT_CLK Period | tCLK_PERIOD | 81.4 | ns | ||
| BIT_CLK Output Jitter¹,² | 750 | 2000 | ps | ||
| BIT_CLK High Pulse Width | tCLK_HIGH | 32.56 | 42 | 48.84 | ns |
| BIT_CLK Low Pulse Width | tCLK_LOW | 32.56 | 38 | ns | |
| SYNC Frequency | 48.0 | kHz | |||
| SYNC Period | tSYNC_PERIOD | 20.8 | ms | ||
| Setup to Falling Edge of BIT_CLK | tSETUP | 5 | 2.5 | ns | |
| Hold from Falling Edge of BIT_CLK | tHOLD | 5 | ns | ||
| BIT_CLK Rise Time | tRISECLK | 2 | 4 | 6 | ns |
| BIT_CLK Fall Time | tFALLCLK | 2 | 4 | 6 | ns |
| SYNC Rise Time | tRISESYNC | 2 | 4 | 6 | ns |
| SYNC Fall Time | tFALLSYNC | 2 | 4 | 6 | ns |
| SDATA_IN Rise Time | tRISEDIN | 2 | 4 | 6 | ns |
| SDATA_IN Fall Time | tFALLDIN | 2 | 4 | 6 | ns |
| SDATA_OUT Rise Time | tRISEDOUT | 2 | 4 | 6 | ns |
| SDATA_OUT Fall Time | tFALLDOUT | 2 | 4 | 6 | ns |
| End of Slot 2 to BIT_CLK, SDATA_IN Low | tSZ_PDOWN | 0 | 1.0 | ms | |
| Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) | tSETUP2RST | 15 | ns | ||
| Rising Edge of RESET to High Z Delay | tOFF | 25 | ns | ||
| Propagation Delay | 15 | ns | |||
| RESET Rise Time | 50 | ns | |||
| Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid | 15 | ns |
¹Guaranteed but not tested.
²Output jitter is directly dependent on crystal input jitter.
³Maximum jitter specification for non-crystal operation only. Crystal operation maximum is much lower.
Timing diagrams illustrate the behavior of RESET, BIT_CLK, SYNC, SDATA_IN, and SDATA_OUT signals during various operations, including cold reset, clocking, signal transitions, AC-Link low power modes, and ATE test modes.
Absolute Maximum Ratings
Exposure to conditions beyond these ratings may cause permanent damage:
| Parameter | Rating |
| Power Supplies | |
| Digital (DV_DD) | -0.3 V to +3.6 V |
| Analog (AVDD) | -0.3 V to +6.0 V |
| Input Current (Except Supply Pins) | ±10 mA |
| Signals Pins | -0.3 V to DV_DD + 0.3 V |
| Digital Input Voltage | -0.3 V to AV_DD + 0.3 V |
| Analog Input Voltage | 0°C to 70°C |
| Ambient Temperature Range (Operating) | -40°C to 85°C, DV_DD, 3.3 V ±5% |
Environmental Conditions
Thermal resistance values for the LQFP package are provided:
| Package | θ_IA | θ_IC |
| LQFP | 50.1°C/W | 17.8°C/W |
ESD (electrostatic discharge) sensitive device. Proper ESD precautions are recommended.
Pin Configuration and Function Descriptions
The AD1981B is available in a 48-lead LQFP package. Pin descriptions cover digital I/O, chip selects, jack sense and EAPD, analog I/O, filter/reference, power, and ground signals.
Digital I/O: XTL_IN, XTL_OUT, SDATA_OUT, BIT_CLK, SDATA_IN, SYNC, RESET, SPDIF.
Chip Selects: ID0, ID1.
Jack Sense and EAPD: JS0, JS1, EAPD.
Analog I/O: PHONE_IN, AUX_L, AUX_R, CD_L, CD_GND_REF, CD_R, MIC1, MIC2, LINE_IN_L, LINE_IN_R, LINE_OUT_L, LINE_OUT_R, MONO_OUT, HP_OUT_L, HP_OUT_R.
Filter/Reference: V_REF, V_REFOUT, AFILT1, AFILT2, AFILT3, AFILT4.
Power and Ground Signals: Multiple DV_DD, DV_SS, AV_DD, and AV_SS pins for digital and analog supplies.
No Connects: NC pins.
Indexed Control Registers
The AD1981B features a comprehensive set of control registers for managing its various functions. These include registers for Reset, Master Volume, Headphone Volume, Mono Volume, Phone Volume, MIC Volume, Line-In Volume, CD Volume, AUX Volume, PCM-Out Volume, Record Select, Record Gain, General-Purpose, Power-Down Control/Status, Extended Audio ID, Extended Audio Status/Control, PCM Front DAC Rate, PCM L/R ADC Rate, SPDIF Control, EQ Control, EQ Data, Mixer ADC Volume, Jack Sense/Audio Interrupt/Status, Serial Configuration, Miscellaneous Control Bit, and Vendor ID registers.
Each register is detailed with its index, name, bit fields, and default values. For example:
- Reset Register (0x00): Controls reset functions and identifies codec capabilities.
- Master Volume Register (0x02): Manages Line_Out volume for stereo channels and mute functions.
- Power-Down Control/Status Register (0x26): Allows control over various power-down modes for ADC, DAC, analog sections, and the AC-link interface.
Control Register Details
Detailed descriptions of key control registers are provided:
Reset Register (Index 0x00)
Writing to this register performs a register reset. Reading it returns the part's ID code and stereo enhancement type. SE[4:0] bits are for stereo enhancement, and ID[9:0] bits decode AD1981B capabilities, including 20-bit DAC resolution (ID7=1) and Headphone Out Support (ID4=1).
Master Volume Register (Index 0x02)
Controls Line_Out volume for left and right channels with 32 levels (1.5 dB steps). Includes mute bits (MM for both channels, RM for right channel if MSPLT is set).
Headphone Volume Register (Index 0x04)
Controls headphone volume for left and right channels, similar to the Master Volume register, with mute functionality.
Mono Volume Register (Index 0x06)
Controls mono output volume with 32 levels and a mute bit (MVM).
Phone Volume Register (Index 0x0C)
Controls phone input volume with 32 levels and a mute bit (PHM). Gain range is +12 dB to -34.5 dB.
MIC Volume Register (Index 0x0E)
Controls MIC input gain with 32 levels and a mute bit (MCM). Includes a MIC Gain Boost bit (M20) for increased sensitivity.
Line-In Volume Register (Index 0x10)
Controls Line-In volume for left and right channels with 32 levels and mute bits (LVM, RM).
CD Volume Register (Index 0x12)
Controls CD input volume for left and right channels with 32 levels and mute bits (CVM, RM).
AUX Volume Register (Index 0x16)
Controls AUX input volume for left and right channels with 32 levels and mute bits (AM, RM).
PCM-Out Volume Register (Index 0x18)
Controls PCM output volume for left and right channels with 32 levels and mute bits (OM, RM).
Record Select Control Register (Index 0x1A)
Selects the record source independently for right (RS[2:0]) and left (LS[2:0]) channels. Default is MIC In.
Record Gain Register (Index 0x1C)
Controls input mixer gain for left (LIM[3:0]) and right (RIM[3:0]) channels, with a range of 0 dB to 22.5 dB. Includes mute bits (IM, RM).
General-Purpose Register (Index 0x20)
Provides Loopback Control (LPBK), MIC Select (MS), and Mono Output Select (MIX).
Power-Down Control/Status Register (Index 0x26)
Manages power-down modes for various subsections (ADC, DAC, Analog, Reference) via PR[6:0] bits. EAPD controls the External Audio Power-Down pin.
Extended Audio ID Register (Index 0x28)
Identifies supported extended audio features, including Variable Rate PCM Audio Support (VRAS), SPDIF Support (SPDIF), DAC Slot Assignments (DSA), AC '97 Revision Compliance (REVC), and Codec Configuration (IDC).
Extended Audio Status and Control Register (Index 0x2A)
Provides status and control for extended audio features. VRA enables variable rate audio. SPDIF controls the SPDIF transmitter subsystem. SPSA bits handle SPDIF slot assignments. SPCV indicates SPDIF configuration validity. VFORCE controls the validity flag.
PCM Front DAC Rate Register (Index 0x2C)
Configures the sample rate for the PCM Front DAC.
PCM L/R ADC Rate Register (Index 0x32)
Configures the sample rate for the PCM L/R ADC.
SPDIF Control Register (Index 0x3A)
Controls SPDIF functionality, including Professional/Consumer mode (PRO), Nonaudio data (AUD), Copyright assertion (COPY), Pre-emphasis (PRE), Category Code (CC), Generation Level (L), and SPDIF Transmit Sample Rate (SPSR).
EQ Control Register (Index 0x60)
Controls equalizer functionality and coefficient addressing. Features Biquad and Coefficient Address Pointer (BCA), Channel Select (CHS), Symmetry (SYM), Mixer ADC Loopback Enable (MAD LBEN), and Equalizer Mute (EQM).
EQ Data Register (Index 0x62)
Used to transfer EQ biquad coefficients into memory. Coefficients are in fixed-point format.
Mixer ADC, Input Gain Register (Index 0x64)
Controls gain into the mixer ADC for left (LMG[3:0]) and right (RMG[3:0]) channels. Includes mute bits (MXM, RM).
Jack Sense/Audio Interrupt/Status Register (Index 0x72)
Manages jack sense inputs (JS0, JS1) and their interrupt/mode configurations. Includes interrupt status bits (JS0INT, JS1INT), state bits (JSOST, JS1ST), mode bits (JS0MD, JS1MD), timer enables (JS0TMR, JS1TMR), EQ bypass enables (JS0EQB, JS1EQB), and mute select bits (JSMT[2:0]).
Serial Configuration Register (Index 0x74)
Configures serial interface parameters, including SPDIF Link (SPLNK), SPDIF DACZ (SPDZ), SPDIF ADC Loop-Around (SPAL), Interrupt Mode Select (INTS), Chain Enable (CHEN), and Master Codec Register Mask bits (REGM[2:0]). Also supports 16-Bit Slot Mode (SLOT16).
Miscellaneous Control Bit Register (Index 0x76)
Contains various control bits such as DAC Zero-Fill (DACZ), Mute Split (MSPLT), MIC Boost Gain Change (MBG[1:0]), MIC Select (MS), 2-Channel MIC Select (2CMIC), Mixer ADC Power-Down (MADPD), Front DAC into Mixer Enable (FMXE), LINE_OUT Disable (LODIS), and Digital Audio Mode (DAM).
Vendor ID Registers (Index 0x7C-0x7E)
Provide vendor and revision information. Vendor ID1 contains ASCII 'AD', and Vendor ID2 contains ASCII 'ST' and revision information.
Outline Dimensions
The AD1981B is supplied in a 48-lead Low Profile Quad Flat Package (LQFP), compliant with JEDEC standards MS-026BBC. Dimensions are provided in millimeters.
Ordering Guide
Various part numbers are available for different temperature ranges and package options, including Pb-free (Z) versions. Specifications for lead-free compatibility and soldering temperatures are noted.
